- 12 Sep, 2016 2 commits
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Monk Liu authored
sync switch buffer scheme with windows kmd for gfx v8, step2: Insert 128NOP after&before VM flush to prevent CE vm fault. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Maruthi Srinivas Bayyavarapu authored
This adds VCE VM mode support from Stoney onwards. Session tracking is an open issue, yet to be supported. v2: Fixed warnings from checkpatch.pl Signed-off-by:
Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by:
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- 02 Sep, 2016 24 commits
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Tom St Denis authored
Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
Various whitespace and logical simplifications for gfx6. Signed-off-by:
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Tom St Denis authored
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Tom St Denis authored
Add missing lock around SE/SH/INSTANCE selections. Signed-off-by:
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Rex Zhu authored
power state table was set based on vbios and should not be changed. when client need to change power state, just make a copy and send to smu. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
delete useless member. Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
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Christian König authored
As last resort try to evict BOs from the current working set into other memory domains. This effectively prevents command submission failures when VM page tables have been swapped out. v2: fix typos Signed-off-by:
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Christian König authored
All other errors can't be fixed by using a different memory domain. Signed-off-by:
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Alex Deucher authored
Normally on shutdown or reboot we don't care about necessarily making sure the hw is in a good state because the system is about to be powered down or reset. However, after a shutdown or reboot in a VM, it's best to tear down the hw properly otherwise there can be problems with the next VM use. Reviewed-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by:
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Alex Deucher authored
Normally on shutdown or reboot we don't care about necessarily making sure the hw is in a good state because the system is about to be powered down or reset. However, after a shutdown or reboot in a VM, it's best to tear down the hw properly otherwise there can be problems with the next VM use. Reviewed-by:
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Alex Deucher authored
Close was not handled correctly. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Alex Deucher authored
Close was not handled correctly. Reviewed-by:
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Alex Deucher authored
Need to fix the error paths. Reviewed-by:
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Alex Deucher authored
Need to fix the error paths. Reviewed-by:
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Alex Deucher authored
Missed this case previously. No need to do anything if the device is already off. runtime pm will handle it. Acked-by:
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Alex Deucher authored
The sbios always powers up the dGPU on resume. Acked-by:
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Alex Deucher authored
Missed this case previously. No need to do anything if the device is already off. runtime pm will handle it. Acked-by:
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Alex Deucher authored
The sbios always powers up the dGPU on resume. Acked-by:
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Alex Deucher authored
The mqd is only used on CI and newer. Reviewed-by:
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- 31 Aug, 2016 14 commits
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Chunming Zhou authored
V2: a. gart recovery should be ahead of ring test. b. rename to amdgpu_ttm_recover_gart Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
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Chunming Zhou authored
V2: spin lock instead of mutex for gtt list Signed-off-by:
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Ken Wang authored
Acked-by:
Ken Wang <Qingqing.Wang@amd.com> Signed-off-by:
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Alex Deucher authored
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Ken Wang authored
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Maruthi Srinivas Bayyavarapu authored
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Huang Rui authored
Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Maruthi Bayyavarapu authored
v2: corrected register offset shift v3: rebase fixes v4: fix firmware paths add SI smc firmware versions for sysfs dump remove unused function forward define fix the tahiti specific value of DEEP_SLEEP_CLK_SEL field fix to miss adding thermal controller use vram_type instead of checking mem_gddr5 flag fix incorrect index of CG_FFCT_0 register fix incorrect reading method at si_get_current_pcie_speed Signed-off-by: -
Maruthi Srinivas Bayyavarapu authored
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Maruthi Srinivas Bayyavarapu authored
v2: renamed _atom_ to _atombios_ for consistency added ulClockParams to _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 and _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 to avoid build break Signed-off-by: -
Ken Wang authored
v3: guard doorbell_fini as well Reviewed-by:
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Ken Wang authored
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Ken Wang authored
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Huang Rui authored
This patch adds pcie port read/write entry, because it will be also used on si dpm part. Acked-by:
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