- 18 Jan, 2013 1 commit
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Kukjin Kim authored
Now, PINCTRL_SAMSUNG should be enabled with PINCTRL_EXYNOS so we don't need to add 'depends on' condition already added in PINCTRL_EXYNOS. Cc: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 01 Dec, 2012 1 commit
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Axel Lin authored
These drivers do not need to select PINCONF. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 22 Nov, 2012 1 commit
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Thomas Abraham authored
Add a new pinctrl driver for Samsung EXYNOS5440 SoC. The pin controller module in EXYNOS5440 is different from the pin controller found on other Samsung SoC. Hence, the pin controller driver for EXYNOS5440 SoC is independent of the Samsung pinctrl framework. Signed-off-by:
Thomas Abraham <thomas.abraham@linaro.org> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- 15 Nov, 2012 2 commits
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Arnd Bergmann authored
The main samsung pinctrl module references the specific exynos4210 pinctrl driver, which selects the main driver in Kconfig. Making the main driver a silent "bool" option avoid this potential build error if CONFIG_PINCTRL_SAMSUNG=y && CONFIG_PINCTRL_EXYNOS4=n: drivers/built-in.o:(.rodata+0x4e4): undefined reference to `exynos4210_pin_ctrl' Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by:
Kukjin Kim <kgene.kim@samsung.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Axel Lin authored
Then we can remove "select PINMUX && PINCONF" from PINCTRL_TEGRA{20,30}. This simplifies the dependency. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 13 Nov, 2012 1 commit
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Axel Lin authored
Then we can remove "select PINMUX && PINCONF" from PINCTRL_IMX{23,28}. This simplifies the dependency. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 11 Nov, 2012 3 commits
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Barry Song authored
The driver supports old up SiRFprimaII SoCs, this patch makes it support the new SiRFmarco as well. SiRFmarco, as a SMP SoC, adds new SIRFSOC_GPIO_PAD_EN_CLR registers, to disable GPIO pad, we should write 1 to the corresponding bit in the new CLEAR register instead of writing 0 to SIRFSOC_GPIO_PAD_EN. Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Thomas Petazzoni authored
Like the spear platform, the mvebu platform has multiple files: one core file, and then one file per SoC family. More files will be added later, as support for mach-orion5x and mach-mv78xx0 SoCs is added to pinctrl-mvebu. For those reasons, having a separate subdirectory, drivers/pinctrl/mvebu/ makes sense, and it had already been suggested by Linus Wallej when the driver was originally submitted. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Thomas Petazzoni authored
The mach-kirkwood and mach-dove architectures have not yet been integrated into the mach-mvebu directory, which should ultimately contain the support for all Marvell SoCs from the Engineering Business Unit. However, before this can happen, we need to let mach-kirkwood and mach-dove use the pinctrl-mvebu driver, which supports the kirkwood and dove SoC families. In order to do that, we make this driver available as soon as PLAT_ORION is selected, instead of using ARCH_MVEBU as a condition. In the long term, PLAT_ORION should disappear and be fully replaced by ARCH_MVEBU, but the plan is to make the migration step by step, by first having the existing mach-* directories for Marvell SoCs converge on several infrastructures, including the pinctrl one. Also, like the spear pinctrl driver, we put all pinctrl-mvebu Kconfig options under a if, in order to avoid having certain options (PINCTRL_DOVE, PINCTRL_KIRKWOOD, etc.) selecting an option (PINCTLR_MVEBU) which itself has a dependency (on ARCH_MVEBU). In this a construct, the dependency is in fact ignored due to the selects. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 06 Nov, 2012 1 commit
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Axel Lin authored
This patch fixes below build error when !CONFIG_OF_GPIO. CC drivers/pinctrl/pinctrl-samsung.o drivers/pinctrl/pinctrl-samsung.c: In function 'samsung_pinctrl_parse_dt_pins': drivers/pinctrl/pinctrl-samsung.c:557:19: warning: unused variable 'prop' [-Wunused-variable] drivers/pinctrl/pinctrl-samsung.c: In function 'samsung_gpiolib_register': drivers/pinctrl/pinctrl-samsung.c:797:5: error: 'struct gpio_chip' has no member named 'of_node' make[2]: *** [drivers/pinctrl/pinctrl-samsung.o] Error 1 make[1]: *** [drivers/pinctrl] Error 2 make: *** [drivers] Error 2 The samsung pinctrl driver supports only device tree enabled platforms. Thus make PINCTRL_SAMSUNG depend on OF && GPIOLIB. The reason to depend on GPIOLIB is CONFIG_OF_GPIO only available when GPIOLIB is selected. Since PINCTRL_EXYNOS4 select PINCTRL_SAMSUNG, thus also make PINCTRL_EXYNOS4 depend on OF && GPIOLIB. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 13 Oct, 2012 1 commit
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Jean-Christophe PLAGNIOL-VILLARD authored
This is also include the gpio controller as the IP share both. Each soc will have to describe the SoC limitation and pin configuration via DT. This will allow to do not need to touch the C code when adding new SoC if the IP version is supported. Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- 01 Oct, 2012 1 commit
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Simon Arlott authored
The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt controller, and pinmux/control device. Original driver by Simon Arlott. Rewrite including GPIO chip device by Chris Boot. Upstreaming changes by Stephen Warren: * Wrote DT binding documentation. * Changed brcm,function to an integer to more directly match the datasheet, and to match brcm,pins being an integer. * Implemented pull-up/down pin config. * Removed read-only DT property and related code. The restriction this implemented are driven by the board, not the GPIO HW block, so don't really make sense of a HW block binding, were in general incomplete (since they could only know about the few pins hard-coded into the Raspberry Pi B board design and not the uncommitted GPIOS), and are better represented simply by not writing incorrect data into pin configuration nodes. * Don't set GPIO_IN function select in gpio_request_enable() to avoid glitches; defer this to gpio_set_direction(). Consequently, removed empty bcm2835_pmx_gpio_request_enable(). * Simplified enabled_irq_map[]; make it explicitly 1 entry per bank. * Lifted use of enabled_irq_map[] outside the per-interrupt loop in IRQ handler, thus fixing an issue where the code was indexing into enabled_irq_map[] by intra-bank GPIO ID, not global GPIO ID. * Removed locking in IRQ handler, since all other code uses spin_lock_irqsave() and so guarantees it doesn't run concurrently with the handler. * Moved duplicated BUILD_BUG_ON()s into probe(). Also check size of bcm2835_gpio_pins[]. * Remove range-checking from bcm2835_pctl_get_groups_count() since we've decided to trust the pinctrl core. * Made bcm2835_pmx_gpio_disable_free() call bcm2835_pinctrl_fsel_set() directly for simplicity. * Fixed body of dt_free_map() to match latest dt_node_to_map(). * Removed GPIO ownership check from bcm2835_pmx_enable() since the pinctrl core owns doing this. * Made irq_chip and pinctrl_gpio_range .name == MODULE_NAME so it's more descriptive. * Simplified remove(); removed call to non-existent pinctrl_remove_gpio_range(), remove early return on error. * Don't force gpiochip's base to 0. Set gpio_range.base to gpiochip's base GPIO number. * Error-handling cleanups in probe(). * Switched to module_platform_driver() rather than open-coding. * Made pin, group, and function names lower-case. * s/broadcom/brcm/ in DT property names. * s/2708/2835/. * Fixed a couple minor checkpatch warnings, and other minor cleanup. Signed-off-by:
Simon Arlott <simon@fire.lp0.eu> Signed-off-by:
Chris Boot <bootc@bootc.net> Signed-off-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 22 Sep, 2012 5 commits
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Thomas Petazzoni authored
This pinctrl driver is not a full-blown pinctrl driver from scratch: it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Thomas Petazzoni authored
This pinctrl driver is not a full-blown pinctrl driver from scratch: it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by:
Stephen Warren <swarren@wwwdotorg.org> Tested-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Jason Cooper <jason@lakedaemon.net> Conflicts: arch/arm/Kconfig
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- 13 Sep, 2012 2 commits
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John Crispin authored
Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks of up to 32 pins. Signed-off-by:
John Crispin <blogic@openwrt.org> Signed-off-by:
Thomas Langer <thomas.langer@lantiq.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
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John Crispin authored
Implement support for pinctrl on lantiq/xway socs. The IO core found on these socs has the registers for pinctrl, pinconf and gpio mixed up in the same register range. As the gpio_chip handling is only a few lines, the driver also implements the gpio functionality. This obseletes the old gpio driver that was located in the arch/ folder. Signed-off-by:
John Crispin <blogic@openwrt.org> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
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- 06 Sep, 2012 2 commits
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Thomas Abraham authored
Add information about the Exynos4210 pin banks and driver data which is used by the Samsung pinctrl driver. In addition to this, the support for external gpio and wakeup interrupt support is included and hooked up with the Samsung pinctrl driver. Signed-off-by:
Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Thomas Abraham authored
Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by:
Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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- 03 Sep, 2012 3 commits
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Uwe Kleine-König authored
This is mostly cut'n'paste from the imx51 pinctrl driver. The data was generated using sed and awk on arch/arm/plat-mxc/include/mach/iomux-mx35.h. Changes since (implicit) v1 - remove references to file names in binding documentation - remove sed commands from comments in driver - add explicit numbers for pins and functions Acked-by:
Shawn Guo <shawn.guo@linaro.org> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Acked-by:
Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
This adds support for the STN8815 ASIC for the Nomadik pin controller. Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Patrice Chotard authored
This implements a subdriver for the DB8540 ASIC for the Nomadik pin controller. Signed-off-by:
Patrice Chotard <patrice.chotard@stericsson.com> Reviewed-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 14 Jul, 2012 1 commit
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Tony Lindgren authored
Add one-register-per-pin type device tree based pinctrl driver. This driver has been tested on omap2+ series of processors, where there is either an 8 or 16-bit padconf register for each pin. Support for other similar pinmux controllers can be added. Signed-off-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 03 Jul, 2012 1 commit
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Linus Walleij authored
The Kconfig entry for the COH901 pin controller depended on PINMUX_U300 which is stale, use PINCTRL_U300 as it is called these days. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 20 May, 2012 2 commits
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Dong Aisheng authored
ChangeLog v1->v2: * change PIN_FUNC_ID base in binding doc to 0 from 1. Acked-by:
Shawn Guo <shawn.guo@linaro.org> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Dong Aisheng authored
ChangeLog v1->v2: * change PIN_FUNC_ID base in binding doc to 0 from 1. Acked-by:
Shawn Guo <shawn.guo@linaro.org> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 15 May, 2012 1 commit
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Arnd Bergmann authored
The nomadik gpio code has been converted to pinctrl, but the nomadik platform still expects the old code to be present. Change it to use the new one instead. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org>
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- 11 May, 2012 3 commits
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Linus Walleij authored
This implements the pin configuration interface for the Nomadik pin controller. As part of the exercise we add a bit in the pin_cfg_t for the Nomadik pinctrl driver that indicates if the pin should be forced into GPIO mode. This is not done to go behind the back of the GPIO subsystem, but to ensure that default modes can be set by hogs on boot and system suspend/resume states. It was used implicitly by the old code defining all config settings and modes in a single config word but we now have a split between pinmux and pinconf leading to the need to have this. We also add a bit for explicitly setting sleepmode of the pin. This was previously handled by custom calls with the _sleep() suffix, but we now have one single interface into the configuration so we replace this with a bit indicating that the pin shall be configured into sleep mode. Some of the configuration can be refactored later to use less custom fields on the pin_cfg_t but we are currently leaving the old function calls in place so we stay compatible. ChangeLog v1->v2: - Drop a hunk changing pinmuxing for GPIO and move it over to the preceding pinmux patch. Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
Implements basic pinmux for the Nomadik pin controller. The plan is to split the existing singular pin config interface nmk_config_pin(), nmk_config_pins(), that will configure muxing and other settings at the same time, into two interfaces by splitting the code in pinmux and pinctrl and eventually deleting the old interface and its helper functions when all users are gone. nmk_gpio_set_mode() and nmk_gpio_get_mode() are two older interfaces for just configuring muxing/altfunctions that will also be replaced in the end. We take some extra care to handle the glitch-avoidance here, but it is simpler now since there is only one altsetting per pingroup so we know immediately if we need to avoid altfunc C glitches for a certain group. As part of the makeover implement the .request() and .free() calls on the GPIO chips and have them call back into the pinctrl layer to reserve GPIOs. ChangeLog v1->v2: - Rebased on pinctrl-mergebase-20120418 so we get the latest driver infrastructure where function count is done by a fixed value and we can drop a few range checks since this is now handled by the core. - Include a GPIO muxing hunk erroneously part of the pin config patch. Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
This adds a scratch pin control interface to the Nomadik pinctrl driver, and defines the pins and groups in the DB8500 ASIC. We define GPIO ranges to cover the pins exposed. The DB8500 has more pins than this but we restrict the driver to the pins that can be controlled from the combined GPIO and pin control hardware to begin with. ChangeLog v1->v2: - Base on the latest pinctrl development from pinctrl-mergebase-20120418 so we can get rid of legacy group count mechanism. Also drop the range checks for group index, this is handled by the core now. Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 01 May, 2012 3 commits
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Shawn Guo authored
Add pinctrl support for Freescale MXS SoCs, i.MX23 and i.MX28. The driver supports device tree probe only. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Dong Aisheng authored
Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Dong Aisheng authored
The driver has mux and config support while the gpio is still not supported. For select input setting, the driver will handle it internally and do not need user to take care of it. The pinctrl-imx core driver will parse the dts file and dynamically create the pinmux functions and groups. Each IMX SoC pinctrl driver should register pins with a pin register map including mux register and config register and select input map to core for proper operations. Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 22 Apr, 2012 1 commit
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Viresh Kumar authored
This adds pinctrl driver for SPEAr platform. It also updates MAINTAINERS file for SPEAr pinctrl drivers. Signed-off-by:
Viresh Kumar <viresh.kumar@st.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Reviewed-by:
Stephen Warren <swarren@wwwdotorg.org>
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- 18 Apr, 2012 1 commit
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Linus Walleij authored
With the finalization of the external driver API and the device tree support, this subsystem is now mature and can be promoted to non-experimental status. Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 12 Mar, 2012 2 commits
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Linus Walleij authored
This adds pin configuration support for the U300 driver pair, we can now read out the biasing and drive mode in debugfs and configure it using the new configuration API. ChangeLog v1->v2: - Migrate to pin config and generic pin config changes. ChangeLog v2->v3: - Adjust to generic pin config changes in v7 patch set. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
This is a split-off from the earlier patch set which adds generic pin configuration for the pin controllers that want it. Since we may have a system with mixed generic and custom pin controllers, we pass a boolean in the pin controller ops vtable to indicate if it is generic. ChangeLog v1->v5: - Follow parent patch versioning number system. - Document the semantic meaning of return values from pin config get functions, so we can iterate over pins and check their properties from debugfs as part of the generic config code. - Use proper cast functions in the generic debugfs pin config file. - Expand generic config to optionally cover groups too. ChangeLog v5->v6: - Update to match underlying changes. ChangeLog v6->v7: - Drop DRIVE_OFF parameter, use bias high impedance for this - Delete argument for drive modes push-pull, od and os. These are now just state transitions. - Delete slew rate rising/falling due to discussions on on proper semantics - Drop config wakeup, struct irq_chip does this for now, add back if need be. - Set PIN_CONFIG_END to 0x7fff making room for custom config parameters from 0x8000 and up. - Prefix accessor functions with pinconf_
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- 06 Mar, 2012 1 commit
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Stephen Warren authored
This adds a driver for the Tegra pinmux, and required parameterization data for Tegra20 and Tegra30. The driver is initially added with driver name and device tree compatible value that won't cause this driver to be used. A later change will switch the pinctrl driver to use the correct values, switch the old pinmux driver to be disabled, and update all code that uses the old pinmux APIs to use the new pinctrl APIs. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Olof Johansson <olof@lixom.net> [squashed "fix case of Tegra30's foo_groups[] arrays"] Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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