- 01 Jun, 2013 8 commits
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git://git.linaro.org/people/nico/linuxOlof Johansson authored
From Nicolas Pitre: This is the first MCPM backend submission for VExpress running on RTSM aka Fast Models implementing the big.LITTLE system architecture. This enables SMP secondary boot as well as CPU hotplug on this platform. A big prerequisite for this support is the CCI driver from Lorenzo included in this pull request. Also included is Rob Herring's set_auxcr/get_auxcr allowing nicer code. Signed-off-by:
Olof Johansson <olof@lixom.net> * 'VExpress_DCSCB' of git://git.linaro.org/people/nico/linux: ARM: vexpress: Select multi-cluster SMP operation if required ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI ARM: vexpress/dcscb: do not hardcode number of CPUs per cluster ARM: vexpress/dcscb: add CPU use counts to the power up/down API implementation ARM: vexpress: introduce DCSCB support ARM: introduce common set_auxcr/get_auxcr functions drivers/bus: arm-cci: function to enable CCI ports from early boot code drivers: bus: add ARM CCI support
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Olof Johansson authored
Pulling in base dependencies from rmk's devel-stable branch needed by the CCI patches for vexpress. Signed-off-by: -
git://git.infradead.org/users/jcooper/linuxOlof Johansson authored
From Jason Cooper: mvebu clock restructuring for v3.11 - clk: mvebu - reorganize by SoC to remove built up #ifdefs - add clk flags per clock gate * tag 'seb_clk-3.11' of git://git.infradead.org/users/jcooper/linux: clk: mvebu: disintegrate obsolete file ARM: mvebu: move DT boards to SoC-centric clock init ARM: kirkwood: move DT boards to SoC-centric clock init ARM: dove: move DT boards to SoC-centric clock init clk: mvebu: add Armada XP SoC-centric clock init clk: mvebu: add Armada 370 SoC-centric clock init clk: mvebu: add Kirkwood SoC-centric clock init clk: mvebu: add Dove SoC-centric clock init clk: mvebu: add common clock functions for core clk and clk gating clk: mvebu: introduce per-clock-gate flags -
git://git.infradead.org/users/jcooper/linuxOlof Johansson authored
From Jason Cooper: mvebu pcie driver (bridge) for v3.11 - mvebu - allow enumeration of devices beyond physical bridges - remove faking the slot location - fix status register emulation Signed-off-by: -
git://git.infradead.org/users/jcooper/linuxOlof Johansson authored
From Jason Cooper: mvebu pcie driver (kirkwood) for v3.11 - kirkwood - enable pcie driver - migrate boards over to pcie dt init depends - mvebu/pcie - mvebu/of_pci Signed-off-by: -
git://git.infradead.org/users/jcooper/linuxOlof Johansson authored
PCI-e driver for mvebu. * tag 'pcie-3.11-2' of git://git.infradead.org/users/jcooper/linux: pci: mvebu: fix return value check in mvebu_pcie_probe() arm: mvebu: PCIe support is now available on mvebu pci: PCIe driver for Marvell Armada 370/XP systems clk: mvebu: add more PCIe clocks for Armada XP clk: mvebu: create parent-child relation for PCIe clocks on Armada 370 of/pci: Add of_pci_parse_bus_range() function of/pci: Add of_pci_get_devfn() function of/pci: Provide support for parsing PCI DT ranges property Signed-off-by:
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git://git.infradead.org/users/jcooper/linuxOlof Johansson authored
From Jason Cooper, mvebu defconfig changes for v3.11. Signed-off-by:
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git://git.infradead.org/users/jcooper/linuxOlof Johansson authored
From Jason Cooper, mvebu soc changes for v3.11 Signed-off-by:
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- 29 May, 2013 19 commits
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Jon Medhurst authored
Signed-off-by:
Jon Medhurst <tixy@linaro.org> Signed-off-by:
Nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Pawel Moll <pawel.moll@arm.com>
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Dave Martin authored
Add the required code to properly handle race free platform coherency exit to the DCSCB power down method. The power_up_setup callback is used to enable the CCI interface for the cluster being brought up. This must be done in assembly before the kernel environment is entered. Thanks to Achin Gupta and Nicolas Pitre for their help and contributions. Signed-off-by:
Dave Martin <dave.martin@linaro.org> Signed-off-by:
Nicolas Pitre <nico@linaro.org> Reviewed-by:
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Nicolas Pitre authored
If 4 CPUs are assumed, the A15x1-A7x1 model configuration would never shut down the initial cluster as the 0xf reset bit mask will never be observed. Let's construct this mask based on the provided information in the DCSCB config register for the number of CPUs per cluster. Signed-off-by:
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Nicolas Pitre authored
It is possible for a CPU to be told to power up before it managed to power itself down. Solve this race with a usage count to deal with this possibility as mandated by the MCPM API definition. Signed-off-by:
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Nicolas Pitre authored
This adds basic CPU and cluster reset controls on RTSM for the A15x4-A7x4 model configuration using the Dual Cluster System Configuration Block (DCSCB). The cache coherency interconnect (CCI) is not handled yet. Signed-off-by:
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Rob Herring authored
Move the private set_auxcr/get_auxcr functions from drivers/cpuidle/cpuidle-calxeda.c so they can be used across platforms. Signed-off-by:
Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by:
Tony Lindgren <tony@atomide.com> Acked-by:
Will Deacon <will.deacon@arm.com>
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Nicolas Pitre authored
This provides cci_enable_port_for_self(). This is the counterpart to cci_disable_port_by_cpu(self). This is meant to be called from the MCPM machine specific power_up_setup callback code when the appropriate affinity level needs to be initialized. The code therefore has to be position independent as the MMU is still off and it cannot rely on any stack space. Signed-off-by:
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Lorenzo Pieralisi authored
On ARM multi-cluster systems coherency between cores running on different clusters is managed by the cache-coherent interconnect (CCI). It allows broadcasting of TLB invalidates and memory barriers and it guarantees cache coherency at system level through snooping of slave interfaces connected to it. This patch enables the basic infrastructure required in Linux to handle and programme the CCI component. Non-local variables used by the CCI management functions called by power down function calls after disabling the cache must be flushed out to main memory in advance, otherwise incoherency of those values may occur if they are sitting in the cache of some other CPU when power down functions execute. Driver code ensures that relevant data structures are flushed from inner and outer caches after the driver probe is completed. CCI slave port resources are linked to set of CPUs through bus masters phandle properties that link the interface resources to masters node in the device tree. Documentation describing the CCI DT bindings is provided with the patch. Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by:
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Andrew Lunn authored
Register a platform driver structure for the cpufreq driver. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Tested-by:
Adam Baker <linux@baker-net.org.uk> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
Switch from function-centric to soc-centric clock drivers now makes a bunch of files obsolete. This deletes all files and Kconfig options that are not required anymore. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by:
Mike Turquette <mturquette@linaro.org> Signed-off-by:
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Sebastian Hesselbarth authored
SoC centric clock init for Armada 370/XP can be used by calling of_clk_init. Use it and get rid of mvebu_clocks_init. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
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Sebastian Hesselbarth authored
SoC centric clock init for Kirkwood can be used by calling of_clk_init. Use it and get rid of mvebu_clocks_init. Signed-off-by:
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Sebastian Hesselbarth authored
SoC centric clock init for Dove can be used by calling of_clk_init. Use it and get rid of mvebu_clocks_init. Signed-off-by:
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Sebastian Hesselbarth authored
This is moving core clock and clock gating init for Armada XP to its own file and adds a Kconfig option. Also init functions are added and declared so they get called on of_clk_init. Signed-off-by:
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Sebastian Hesselbarth authored
This is moving core clock and clock gating init for Armada 370 to its own file and adds a Kconfig option. Also init functions are added and declared so they get called on of_clk_init. Signed-off-by:
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Sebastian Hesselbarth authored
This is moving core clock and clock gating init for Kirkwood to its own file and adds a Kconfig option. Also init functions are added and declared so they get called on of_clk_init. Signed-off-by:
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Sebastian Hesselbarth authored
This is moving core clock and clock gating init for Dove to its own file and adds a Kconfig option. Also init functions are added and declared so they get called on of_clk_init. Signed-off-by:
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Sebastian Hesselbarth authored
Based on the current common functions for core clocks and clock gating control, new common functions are joined in a single file. Given the opportunity, names of functions and structs are unified, and also a Kconfig entry is added. Signed-off-by:
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Sebastian Hesselbarth authored
Clock gates found on MVEBU SoCs get registered by a common function. To allow specific SoCs to provide tweaks introduce flags to the clock gate descriptor instead of filling up the common function SoC specific tweaks. Signed-off-by:
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- 27 May, 2013 12 commits
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Thomas Petazzoni authored
This commit converts the Marvell DB-88F6281/DB-88F6282 board to the Device Tree. In fact, the code was supporting two different boards: one with the 6281 SoC variant, and one with the 6282 SoC variant. The difference between the two being that the 6281 has one PCIe interface, and the 6282 has two PCIe interfaces. In order to handle that with the Device Tree, we create a 'kirkwood-db.dtsi' file that contains the definitions common to both boards, and 'kirkwood-db-88f6281.dts' and 'kirkwood-db-88f6282.dts' for the definitions specific to each board. This is similar to what is done for the QNAP TS219 Kirkwood platform. We have kept one single Kconfig option, just like it was before. Signed-off-by:
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Thomas Petazzoni authored
Now that the PCIe mvebu driver is usable on Kirkwood, use it instead of the legacy PCIe code, since it allows to describe the PCIe interfaces in the Device Tree. Signed-off-by:
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Thomas Petazzoni authored
Now that the PCIe mvebu driver is usable on Kirkwood, use it instead of the legacy PCIe code, since it allows to describe the PCIe interfaces in the Device Tree. Since it was the only device left that prevented this platform to use the Device Tree only, we remove the board-nsa310.c file and the related Kconfig/Makefile bits. Signed-off-by:
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Thomas Petazzoni authored
Now that the PCIe mvebu driver is usable on Kirkwood, use it instead of the legacy PCIe code, since it allows to describe the PCIe interfaces in the Device Tree. Signed-off-by:
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Thomas Petazzoni authored
Now that the PCIe mvebu driver is usable on Kirkwood, use it instead of the legacy PCIe code, since it allows to describe the PCIe interfaces in the Device Tree. Signed-off-by:
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Thomas Petazzoni authored
This commit adds Device Tree details to enable the PCIe interfaces on Kirkwood. The 6281 has one PCIe interface, the 6282 has two PCIe interfaces. Signed-off-by:
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Thomas Petazzoni authored
Since we are going to enable the usage of the mvebu PCIe driver on Kirkwood, we don't want the PCIe windows to be unconditionally created by kirkwood_setup_wins(). Therefore, we move the PCIe window initialization into the legacy PCIe driver (arch/arm/mach-kirkwood/pcie.c). The platforms using the legacy driver will see their windows statically allocated by arch/arm/mach-kirkwood/pcie.c:kirkwood_pcie_init(). The platforms using the new driver in drivers/pci/ will see their windows dynamically allocated directly by the driver. Signed-off-by:
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Thomas Petazzoni authored
We allow the pci-mvebu driver to be compiled on the Kirkwood platform, and add the 'marvell,kirkwood-pcie' as a compatible string supported by the driver. Signed-off-by:
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Thomas Petazzoni authored
The status register of the PCI configuration space of PCI-to-PCI bridges contain some read-only bits, and so write-1-to-clear bits. So, the Linux PCI core sometimes writes 0xffff to this status register, and in the current PCI-to-PCI bridge emulation code of the Marvell driver, we do take all those 1s being written. Even the read-only bits are being overwritten. For now, all the read-only bits should be emulated to have the zero value. The other bits, that are write-1-to-clear bits are used to report various kind of errors, and are never set by the emulated bridge, so there is no need to support this write-1-to-clear bits mechanism. As a conclusion, the easiest solution is to simply emulate this status register by returning zero when read, and ignore the writes to it. This has two visible effects: * The devsel is no longer 'unknown' in, i.e Flags: bus master, 66MHz, user-definable features, ?? devsel, latency 0 becomes: Flags: bus master, 66MHz, user-definable features, fast devsel, latency 0 in lspci -v. This was caused by a value of 11b being read for devsel, which is an invalid value. This 11b value being read was due to a previous write of 0xffff into the status register. * The capability list is no longer broken, because we indicate to the Linux PCI core that we don't have a Capabilities Pointer in the PCI configuration space of this bridge. The following message is therefore no longer visible in lspci -v: Capabilities: [fc] <chain broken> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Signed-off-by:
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Thomas Petazzoni authored
Until now, the Marvell PCIe driver was only allowing the enumeration of the devices in the secondary bus of the emulated PCI-to-PCI bridge. This works fine when a PCIe device is directly connected into a PCIe slot of the Marvell board. However, when the device connected in the PCIe slot is a physical PCIe bridge, beyond which a real PCIe device is connected, it no longer worked, as the driver was preventing the Linux PCI core from seeing such devices. This commit fixes that by ensuring that configuration transactions on subordinate busses are properly forwarded on the right PCIe interface. Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond the emulated PCI-to-PCI bridge is properly detected, with the following layout: -[0000:00]-+-01.0-[01]----00.0 +-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]-- | +-05.0-[05]-- | +-07.0-[06]-- | \-09.0-[07]----00.0 \-0a.0-[08]----00.0 Where the PCIe interface that sits beyond the emulated PCI-to-PCI bridge at 09.0 allows to access the secondary bus 02, on which there is a PCIe bridge that allows to access the 3 to 7 busses, that are subordinates to this bridge. And on one of this bus (bus 7), there is one real PCIe device connected. Signed-off-by: -
Thomas Petazzoni authored
By default, the Marvell hardware, for each PCIe interface, exhibits the following devices: * On slot 0, a "Marvell Memory controller", identical on all PCIe interfaces, and which isn't useful when the Marvell SoC is the PCIe root complex (i.e, the normal case when we run Linux on the Marvell SoC). * On slot 1, the real PCIe card connected into the PCIe slot of the board. So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge emulation is that when the Linux PCI core was trying to access the device in slot 0, we were in fact forwarding the configuration transaction to the device in slot 1. For all other slots, we were telling the Linux PCI core that there was no device connected. However, new versions of bootloaders from Marvell change the default PCIe configuration, and make the real device appear in slot 0, and the "Marvell Memory controller" in slot 1. Therefore, this commit modifies the Marvell PCIe driver to adjust the PCIe hardware configuration to make sure that this behavior (real device in slot 0, "Marvell Memory controller" in slot 1) is the one we'll see regardless of what the bootloader has done. It allows to remove the little hack that was forwarding configuration transactions on slot 0 to slot 1, which is nice. Signed-off-by:
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Wei Yongjun authored
In case of error, function of_clk_get_by_name() returns ERR_PTR() never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by:
Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by:
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- 26 May, 2013 1 commit
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Linus Torvalds authored
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