1. 01 Jan, 2010 1 commit
    • Haojian Zhuang's avatar
      [ARM] pxa: do not enable L2 after MMU is enabled · dc8601a2
      Haojian Zhuang authored
      Outer cache checked whether L2 is enabled or not. If L2 isn't enabled in XSC3,
      it would enable L2. This operation is evil that would make system hang.
      
      In XSC3 core document, these words are mentioned in below.
      
      "Following reset, the L2 Unified Cache Enable bit is cleared. To enable the L2
      Cache, software may set the bit to a '1' before or at the same time as enabling
      the MMU. Enabling the L2 Cache after the MMU has been enabled or disabling the
      L2 Cache after the L2 Cache has been enabled, may result in unpredictable
      behavior of the processor."
      
      When outer cache is initialized, the MMU is already enabled. We couldn't enable
      L2 after MMU enabled.
      Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@marvell.com>
      Signed-off-by: default avatarEric Miao <eric.y.miao@gmail.com>
      dc8601a2
  2. 29 Dec, 2009 10 commits
  3. 24 Dec, 2009 29 commits