- 22 Nov, 2019 4 commits
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Green Wan authored
There are several comments starting from "/**" but not for function comment purpose. It causes kernel-doc parsing wrong string. Replace "/**" with "/*" to fix them. Signed-off-by:
Green Wan <green.wan@sifive.com> Link: https://lore.kernel.org/r/20191118143554.16129-1-green.wan@sifive.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Chuhong Yuan authored
When devm_kcalloc fails, it forgets to call edma_free_slot. Replace direct return with failure handler to fix it. Fixes: 1be5336b ("dmaengine: edma: New device tree binding") Signed-off-by:
Chuhong Yuan <hslester96@gmail.com> Link: https://lore.kernel.org/r/20191118073802.28424-1-hslester96@gmail.comSigned-off-by:
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Chuhong Yuan authored
The driver calls of_dma_controller_register in probe but does not free it in remove. Add the call to fix it. Signed-off-by:
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Chuhong Yuan authored
The driver calls of_dma_controller_register in probe but does not free it in remove. Add the call to fix it. Signed-off-by:
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- 14 Nov, 2019 8 commits
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Eric Long authored
The Spreadtrum Audio compress offload mode will use 2-stage DMA transfer to save power. That means we can request 2 dma channels, one for source channel, and another one for destination channel. Once the source channel's transaction is done, it will trigger the destination channel's transaction automatically by hardware signal. In this case, the source channel will transfer data from IRAM buffer to the DSP fifo to decoding/encoding, once IRAM buffer is empty by transferring done, the destination channel will start to transfer data from DDR buffer to IRAM buffer. Since the destination channel will use link-list mode to fill the IRAM data, and IRAM buffer is allocated by 32K, and DDR buffer is larger to 2M, that means we need lots of link-list nodes to do a cyclic transfer, instead wasting lots of link-list memory, we can use wrap address support to reduce link-list node number, which means when the transfer address reaches the wrap address, the transfer address will jump to the wrap_to address specified by wrap_to register, and only 2 link-list nodes can do a cyclic transfer to transfer data from DDR to IRAM. Thus this patch adds wrap address to support this case. [Baolin Wang changes the commit message] Signed-off-by:
Eric Long <eric.long@unisoc.com> Signed-off-by:
Baolin Wang <baolin.wang@linaro.org> Link: https://lore.kernel.org/r/85a5484bc1f3dd53ce6f92700ad8b35f30a0b096.1571812029.git.baolin.wang@linaro.orgSigned-off-by:
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Vinod Koul authored
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Green Wan authored
Update MAINTAINERS for SiFive PDMA driver. Signed-off-by:
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Green Wan authored
Add PDMA driver, sf-pdma, to enable DMA engine on HiFive Unleashed Rev A00 board. - Implement dmaengine APIs, support MEM_TO_MEM async copy. - Tested by DMA Test client - Supports 4 channels DMA, each channel has 1 done and 1 err interrupt connected to platform-level interrupt controller (PLIC). - Depends on DMA_ENGINE and DMA_VIRTUAL_CHANNELS The datasheet is here: https://static.dev.sifive.com/FU540-C000-v1.0.pdf Follow the DMAengine controller doc, "./Documentation/driver-api/dmaengine/provider.rst" to implement DMA engine. And use the dma test client in doc, "./Documentation/driver-api/dmaengine/dmatest.rst", to test. Each DMA channel has separate HW regs and support done and error ISRs. 4 channels share 1 done and 1 err ISRs. There's no expander/arbitrator in DMA HW. ------ ------ | |--< done 23 >--|ch 0| | |--< err 24 >--| | (dma0chan0) | | ------ | | ------ | |--< done 25 >--|ch 1| | |--< err 26 >--| | (dma0chan1) |PLIC| ------ | | ------ | |--< done 27 >--|ch 2| | |--< err 28 >--| | (dma0chan2) | | ------ | | ------ | |--< done 29 >--|ch 3| | |--< err 30 >--| | (dma0chan3) ------ ------ Signed-off-by:
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Green Wan authored
Add DT bindings document for Platform DMA(PDMA) driver of board, HiFive Unleashed Rev A00. Reviewed-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Pragnesh Patel <pragnesh.patel@sifive.com> Signed-off-by:
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Satendra Singh Thakur authored
In the probe method dmam_pool_create is used. Therefore, there is no need to explicitly call dmam_pool_destroy in remove method as this will be automatically taken care by devres Signed-off-by:
Satendra Singh Thakur <sst2005@gmail.com> Link: https://lore.kernel.org/r/20191109113609.6159-1-sst2005@gmail.comSigned-off-by:
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Satendra Singh Thakur authored
When devm_request_irq fails, currently, the function dma_async_device_unregister gets called. This doesn't free the resources allocated by of_dma_controller_register. Therefore, we have called of_dma_controller_free for this purpose. Signed-off-by:
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Colin Ian King authored
There is a statement that is indented too deeply, remove the extraneous indentation. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20191112191143.282814-1-colin.king@canonical.comSigned-off-by:
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- 08 Nov, 2019 3 commits
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Vinod Koul authored
platform_get_irq() prints the error message, so caller need not do so, remove the error line in this driver for platform_get_irq() Reported-by:
kbuild test robot <lkp@intel.com> Signed-off-by:
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Vinod Koul authored
platform_get_irq() prints the error message, so caller need not do so, remove the error line in this driver for platform_get_irq() Reported-by:
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Chuhong Yuan authored
The remove misses to disable and unprepare jzdma->clk. Add a call to clk_disable_unprepare to fix it. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20191104161622.11758-1-hslester96@gmail.comSigned-off-by:
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- 06 Nov, 2019 8 commits
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Zhou Yanjie authored
Add support for probing the dma-jz4780 driver on the X1000 Soc. Signed-off-by:
Zhou Yanjie <zhouyanjie@zoho.com> Reviewed-by:
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Zhou Yanjie authored
Add the dmaengine bindings for the X1000 Soc from Ingenic. Signed-off-by:
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Radhey Shyam Pandey authored
Add support for AXI Multichannel Direct Memory Access (AXI MCDMA) core, which is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides scatter-gather interface with multiple independent transmit and receive channels. The driver supports device_prep_slave_sg slave transfer mode. Signed-off-by:
Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1571763622-29281-7-git-send-email-radhey.shyam.pandey@xilinx.comSigned-off-by:
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Radhey Shyam Pandey authored
Extend dma_config structure to store irq routine handle. It enables runtime handler selection based on xdma_ip_type and serves as preparatory patch for adding MCDMA IP support. Signed-off-by:
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Radhey Shyam Pandey authored
The AXI DMA multichannel support is deprecated in the IP and it is no longer actively supported. For multichannel support, refer to the AXI multichannel direct memory access IP product guide(PG228) and MCDMA driver. So inline with it remove axidma multichannel support from from the driver. Signed-off-by:
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Radhey Shyam Pandey authored
Add devicetree binding for Xilinx AXI Multichannel Direct Memory Access (AXI MCDMA) IP. The AXI MCDMA provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides a scatter-gather interface with multiple channel support with independent configuration. Signed-off-by:
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Radhey Shyam Pandey authored
Trivial formatting(keep compatible string one per line, caps change etc). It doesn't modify the content of the binding. Signed-off-by:
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Radhey Shyam Pandey authored
The AXI DMA multichannel support is deprecated in the IP and it is no longer actively supported. For multichannel support, refer to the AXI multichannel direct memory access IP product guide(PG228) and MCDMA driver(added in the subsequent commits). Inline with it remove axidma multichannel optional properties i.e xlnx,mcdma and dma-channels from the binding description. Signed-off-by:
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- 05 Nov, 2019 3 commits
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Peter Ujfalusi authored
Like paRAM slots, channels could be used by other cores and in this case we need to make sure that the driver do not alter these channels. Handle the generic dma-channel-mask property to mark channels in a bitmap which can not be used by Linux and convert the legacy rsv_chans if it is provided by platform_data. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20191025073056.25450-4-peter.ujfalusi@ti.comSigned-off-by:
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Peter Ujfalusi authored
Similarly to paRAM slots, channels can be used by other cores. The common dma-channel-mask property can be used for specifying the available channels. Signed-off-by:
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Peter Ujfalusi authored
Make the dma-channel-mask to be usable for controllers with more than 32 channels. Signed-off-by:
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- 02 Nov, 2019 2 commits
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Nathan Chancellor authored
Clang warns: drivers/dma/fsl-dpaa2-qdma/dpdmai.c:148:25: warning: variable 'cfg' is uninitialized when used within its own initialization [-Wuninitialized] DPDMAI_CMD_CREATE(cmd, cfg); ~~~~~~~~~~~~~~~~~~~~~~~^~~~ drivers/dma/fsl-dpaa2-qdma/dpdmai.c:42:24: note: expanded from macro 'DPDMAI_CMD_CREATE' typeof(_cfg) (cfg) = (_cfg); \ ~~~ ^~~~ 1 warning generated. Looking at the preprocessed source, we can see that this is true. int dpdmai_create(struct fsl_mc_io *mc_io, u32 cmd_flags, const struct dpdmai_cfg *cfg, u16 *token) { struct fsl_mc_command cmd = { 0 }; int err; cmd.header = mc_encode_cmd_header((((0x90E) << 4) | 0), cmd_flags, 0); do { typeof(cmd)(cmd) = (cmd); typeof(cfg)(cfg) = (cfg); ((cmd).params[0] |= mc_enc((8), (8), (cfg)->priorities[0])); ((cmd).params[0] |= mc_enc((16), (8), (cfg)->priorities[1])); } while (0); I cannot see a good reason to create another version of cfg when the parameter one will work perfectly fine and cmd can just be used as is. Remove them to fix this warning. Fixes: f2835adf ("dmaengine: fsl-dpaa2-qdma: Add the DPDMAI(Data Path DMA Interface) support") Link: https://github.com/ClangBuiltLinux/linux/issues/746Signed-off-by:Nathan Chancellor <natechancellor@gmail.com> Link: https://lore.kernel.org/r/20191022171648.37732-1-natechancellor@gmail.comSigned-off-by:
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Krzysztof Kozlowski authored
platform_get_irq_byname() might return -errno which later would be cast to an unsigned int and used in IRQ handling code leading to usage of wrong ID and errors about wrong irq_base. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by:
Peng Ma <peng.ma@nxp.com> Tested-by:
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- 23 Oct, 2019 2 commits
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Tony Lindgren authored
Yegor Yefremov <yegorslists@googlemail.com> reported that musb and ftdi uart can fail for the first open of the uart unless connected using a hub. This is because the first dma call done by musb_ep_program() must wait if cppi41 is PM runtime suspended. Otherwise musb_ep_program() continues with other non-dma packets before the DMA transfer is started causing at least ftdi uarts to fail to receive data. Let's fix the issue by waking up cppi41 with PM runtime calls added to cppi41_dma_prep_slave_sg() and return NULL if still idled. This way we have musb_ep_program() continue with PIO until cppi41 is awake. Fixes: fdea2d09 ("dmaengine: cppi41: Add basic PM runtime support") Reported-by:
Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com> Cc: stable@vger.kernel.org # v4.9+ Link: https://lore.kernel.org/r/20191023153138.23442-1-tony@atomide.comSigned-off-by:
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Peng Ma authored
The symbols were not exported leading to error: WARNING: modpost: missing MODULE_LICENSE() in drivers/dma/fsl-dpaa2-qdma/dpdmai.o see include/linux/module.h for more information GZIP arch/arm64/boot/Image.gz ERROR: "dpdmai_enable" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! ERROR: "dpdmai_set_rx_queue" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! ERROR: "dpdmai_get_tx_queue" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! ERROR: "dpdmai_get_rx_queue" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! ERROR: "dpdmai_get_attributes" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! ERROR: "dpdmai_open" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! ERROR: "dpdmai_close" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! ERROR: "dpdmai_disable" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! ERROR: "dpdmai_reset" [drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.ko] undefined! WARNING: "HYPERVISOR_platform_op" [vmlinux] is a static EXPORT_SYMBOL_GPL make[2]: *** [__modpost] Error 1 make[1]: *** [modules] Error 2 make[1]: *** Waiting for unfinished jobs.... make: *** [sub-make] Error 2 So export it. Signed-off-by:
Anders Roxell <anders.roxell@linaro.org> Link: https://lore.kernel.org/r/20191023045617.22764-1-peng.ma@nxp.comSigned-off-by:
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- 20 Oct, 2019 7 commits
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Nicholas Graumann authored
Whenever we reset the channel, we need to clear desc_pendingcount along with desc_submitcount. Otherwise when a new transaction is submitted, the irq coalesce level could be programmed to an incorrect value in the axidma case. This behavior can be observed when terminating pending transactions with xilinx_dma_terminate_all() and then submitting new transactions without releasing and requesting the channel. Signed-off-by:
Nicholas Graumann <nick.graumann@gmail.com> Signed-off-by:
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Nicholas Graumann authored
The driver should not run out of tx segments in normal operation. But, if the user attempts to prepare a transaction with a large sg list, the driver may not have enough free segments to accommodate the request. Log a message at the debug level to inform the user in case they are experiencing issues. Signed-off-by:
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Nicholas Graumann authored
Take advantage of dmaengine_desc_get_callback_invoke which allows either a callback or callback_result to be specified. This can be useful when using the AXI DMA transfer unknown quantities of data where the residue contained in the result can be used to calculate the number of bytes transferred. Signed-off-by:
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Nicholas Graumann authored
Introduce a function that can calculate residues for IPs that support it: AXI DMA and CDMA. Signed-off-by:
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Radhey Shyam Pandey authored
There is no use of storing channel data residue field. So clean it up. In tx_status simply pass calculated residue to dma_set_residue. Signed-off-by:
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Nicholas Graumann authored
The dma api provides a single interface to get the appropriate callback and invoke it directly. Prefer using it. Signed-off-by:
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Radhey Shyam Pandey authored
In descriptor cleanup the call to desc_callback_valid can be safely removed as both callback pointers i.e callback_result and callback are anyway checked in invoke(). There is no much benefit in having redundant checks. Signed-off-by:
Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Link: https://lore.kernel.org/r/1571150904-3988-2-git-send-email-radhey.shyam.pandey@xilinx.comSigned-off-by:
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- 18 Oct, 2019 3 commits
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Jassi Brar authored
Driver for Socionext Milbeaut XDMAC controller. The controller only supports Mem-To-Mem transfers over upto 8 configurable channels. Signed-off-by:
Jassi Brar <jaswinder.singh@linaro.org> Link: https://lore.kernel.org/r/20191015033219.14713-1-jassisinghbrar@gmail.comSigned-off-by:
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Jassi Brar authored
Document the devicetree bindings for Socionext Milbeaut XDMAC controller. Controller only supports Mem->Mem transfers. Number of physical channels are determined by the number of irqs registered. Reviewed-by:
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Jassi Brar authored
Driver for Socionext Milbeaut HDMAC controller. The controller has upto 8 floating channels, that need a predefined slave-id to work from a set of slaves. Signed-off-by:
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