- 02 Mar, 2018 9 commits
-
-
Linus Walleij authored
Merge tag 'sh-pfc-for-v4.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.17 - Add DU and VIN pin groups on R-Car D3, - Add HDMI, TMU, and VIN pin groups on R-Car H3 and M3-W, - Add support for the new R-Car M3-N SoC, - Small fixes and cleanups.
-
Richard Fitzgerald authored
Systems that don't have devicetree need pinctrl_register_mappings. It should be EXPORT_SYMBOL_GPL so that it can be called from pinctrl drivers built as modules. Signed-off-by:
Richard Fitzgerald <rf@opensource.cirrus.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
-
Martin Blumenstingl authored
Meson8b is a cost reduced variant of the Meson8 SoC. It's package size is smaller than Meson8. Unfortunately there are a few key differences which cannot be seen without close inspection of the code and the public S805 datasheet: - the GPIOX bank is missing the GPIOX_12, GPIOX_13, GPIOX_14 and GPIOX_15 GPIOs - the GPIOY bank is missing the GPIOY_2, GPIOY_4, GPIOY_5, GPIOY_15 and GPIOY_16 GPIOs - the GPIODV bank is missing all GPIOs except GPIODV_9, GPIODV_24, GPIODV_25, GPIODV_26, GPIODV_27, GPIODV_28 and GPIODV_29 - the GPIOZ bank is missing completely - there is a new GPIO bank called "DIF" This means that Meson8b only has 83 actual GPIO lines. Without any holes there would be 130 GPIO lines in total (120 are inherited from Meson8 plus 10 new from the DIF bank). GPIOs greater GPIOZ_3 (whose ID is 83 - as a reminder: this is exactly the number of actual GPIO lines on Meson8b and also the value of meson8b_cbus_pinctrl_data.num_pins) cannot berequested. Using CARD_6 (which used ID 100 prior to this patch, "base of the GPIO controller was 382) as an example: $ echo 482 > /sys/class/gpio/export export_store: invalid GPIO 482 This removes all non-existing pins from to dt-bindings header file (include/dt-bindings/gpio/meson8b-gpio.h). This allows us to have a consecutive numbering for the GPIO #defines (GPIOY_2 doesn't exist for example, so previously the GPIOY_3 ID was "GPIOY_1 + 2", after this patch it is "GPIOY_1 + 1"). As a nice side-effect this means that we get compile-time (instead of runtime) errors if Meson8b .dts uses a pin that only exists on Meson8. Additionally the pinctrl-meson8b driver has to be updated to handle this new GPIO numbering. By default a struct meson_bank only handles GPIO banks where the pins are numbered consecutively because it calculates the bit offsets based on the GPIO IDs. This is solved by taking the original BANK() definition and splitting it into consecutive subsets (X0..11 and X16..21). The bit offsets for each new bank includes the skipped GPIOs (the definition of the "X0..11" bank is identical to the old "X" bank apart from the "last IRQ" field, the definition of the new, split "X16..21" bank takes the original "X" bank and adds 16 - the start of the new split bank - to the "first IRQ", pullen bit, pull bit, dir bit, out bit and in bit). Commit 984cffde ("pinctrl: Fix gpio/pin mapping for Meson8b") fixed the same issue by setting "ngpio" (of the gpio_chip) to 130. Unfortunately this broke in db80f0e1 ("pinctrl: meson: get rid of unneeded domain structures"). The solution from this patch was considered to be better than the previous attempt at fixing this because it provides compile-time error checking for the GPIOs that exist on Meson8 but don't exist on Meson8b. The following pins were tested on an Odroid-C1 using the sysfs GPIO interface checking that their value (high or low) could be read: - GPIOX_0, GPIOX_1, GPIOX_2, GPIOX_3, GPIOX_4, GPIOX_5, GPIOX_6, GPIOX_7, GPIOX_8, GPIOX_9, GPIOX_10, GPIOX_11, GPIOX_18, GPIOX_19, GPIOX_20, GPIOX_21 - GPIOY_3, GPIOY_7, GPIOY_8 (some of these had to be pulled up because they were low by default, others were high by default so these had to be pulled down) Reported-by:
Linus Lüssing <linus.luessing@c0d3.blue> Suggested-by:
Jerome Brunet <jbrunet@baylibre.com> Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by:
-
Richard Fitzgerald authored
When dt_to_map_one_config() is called with a pinctrl_dev passed in, it should only be using this if the node being looked up is a hog. The code was always using the passed pinctrl_dev without checking whether the dt node referred to it. A pin controller can have pinctrl-n dependencies on other pin controllers in these cases: - the pin controller hardware is external, for example I2C, so needs other pin controller(s) to be setup to communicate with the hardware device. - it is a child of a composite MFD so its of_node is shared with the parent MFD and other children of that MFD. Any part of that MFD could have dependencies on other pin controllers. Because of this, dt_to_map_one_config() can't assume that if it has a pinctrl_dev passed in then the node it looks up must be a hog. It could be a reference to some other pin controller. Signed-off-by:
-
Sean Wang authored
Add missing pinctrl binding about I2C2 and SPI2 which would be used in devicetree related files. Signed-off-by:
Sean Wang <sean.wang@mediatek.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by:
-
Sean Wang authored
It should be good that no use "_" is in examples. Consequently, those nodes in certain files which have an inappropriate name containing "_" are all being replaced with "-". Signed-off-by:
-
Radoslaw Pietrzyk authored
- removes unneeded irq_chip.irq_eoi callback - adds irq_chip.irq_set_wake callback for possible in the future GPIO wakeup - adds irq_chip.irq_ack callback Signed-off-by:
Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com> Reviewed-by:
Ludovic Barre <ludovic.barre@st.com> Tested-by:
-
Niklas Cassel authored
Add group configuration for uarts that are cut down variants, the standard being full, i.e. all signals, flow control, i.e. rx/tx and cts/rts, and rx/tx only. This allows us to be more precise in which pins we're actually using. Unfortunately the existing naming scheme leaves things to be desired, e.g. uart3grp0 means RX/TX and CTS/RTS, yet uart0grp0 means all pins. Since the exising suffixes have different meaning for different uarts, and the fact that we cannot change the name of existing groups, makes it hard to use a descriptive name for the newly added groups. Signed-off-by:
Niklas Cassel <niklas.cassel@axis.com> Signed-off-by:
-
Niklas Cassel authored
Add missing pin group uart5nocts (all pins except cts), which has been supported by the artpec6 pinctrl driver since its initial submission. Fixes: 00df0582 ("pinctrl: Add pincontrol driver for ARTPEC-6 SoC") Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
-
- 01 Mar, 2018 2 commits
-
-
Jesper Nilsson authored
Add group configuration for uarts that are cut down variants, the standard being full, i.e. all signals, flow control, i.e. rx/tx and cts/rts, and rx/tx only. This allows us to be more precise in which pins we're actually using. Signed-off-by:
Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by:
-
James Hogan authored
Now that arch/metag/ has been removed, along with TZ1090 SoC support, remove the TZ1090 pinctrl drivers. They are of no value without the architecture and SoC platform code. Signed-off-by:
James Hogan <jhogan@kernel.org> Cc: linux-gpio@vger.kernel.org Cc: linux-metag@vger.kernel.org Signed-off-by:
-
- 28 Feb, 2018 1 commit
-
-
Takeshi Kihara authored
Most pins on the R8A77965 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On R8A77965 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". Based on a similar patch for the R8A7795 PFC driver by Magnus Damm <damm+renesas@opensource.se>. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
-
- 26 Feb, 2018 3 commits
-
-
Ulrich Hecht authored
This patch adds VIN4 pins, groups and function for the R8A77995 (D3) SoC. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by:
-
Ulrich Hecht authored
This patch adds VIN4 and VIN5 pins, groups and functions for the R8A7795 SoC. Signed-off-by:
-
Ulrich Hecht authored
This patch adds VIN4 and VIN5 pins, groups and functions for the R8A7796 SoC. Signed-off-by:
-
- 22 Feb, 2018 6 commits
-
-
Phil Reid authored
The mcp23s08 series device can be configured for wired and interrupts using an external pull-up and open drain output via the IOCON_ODR bit. And "drive-open-drain" property to enable this. Reviewed-by:
Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by:
Phil Reid <preid@electromag.com.au> Reviewed-by:
Jan Kundrát <jan.kundrat@cesnet.cz> Signed-off-by:
-
Phil Reid authored
This flag set the mcp23s08 device irq type to open drain active low. Acked-by:
-
Phil Reid authored
one_regmap_config is always null if mcp type is MCP_TYPE_S18. Remove the null check so that the mcp23s18 will probe. Fixes: 1781af56 ("pinctrl: mcp23s08: spi: Fix duplicate pinctrl debugfs entries") Signed-off-by:
-
Daniel Kurtz authored
On boot, gpiochip_add_data() initializes the FLAG_IS_OUT bit in desc->flags iff its gpio_chip does not have ->direction_input() handler, else it is initialized to 0, which implies the GPIO is an "input". Later, the sysfs "direction" handler will use gpiod_get_direction() to get the current direction, but if no ->get_direction() handler is installed, the result will just be the current (initial) value of flags, which will always be OUT irregardless of the initial register value. Add a get_direction() handler to pinctrl-amd to fix this and always provide the correct value for direction. Signed-off-by:
Daniel Kurtz <djkurtz@chromium.org> Signed-off-by:
-
Andy Shevchenko authored
...instead of open coding file operations followed by custom ->open() callbacks per each attribute. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
-
Colin Ian King authored
The function ocelot_pinctrl_probe is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: drivers/pinctrl/pinctrl-ocelot.c:465:5: warning: symbol 'ocelot_pinctrl_probe' was not declared. Should it be static? Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
-
- 20 Feb, 2018 13 commits
-
-
Jacopo Mondi authored
Add EtherAVB groups and functions definitions for R-Car M3-N. Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by:
-
Jacopo Mondi authored
Add SCIF[0-5] groups and pin function definitions for R-Car M3-N. Signed-off-by:
-
Jacopo Mondi authored
Add initial PFC support for R-Car M3-N (r8a77965) SoC. No groups or functions defined, just pin and registers enumeration. Signed-off-by:
-
Takeshi Kihara authored
This patch adds TMU TCLK{1,2} pins, groups and functions to the R8A7796 SoC. Signed-off-by:Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
-
Takeshi Kihara authored
This patch adds TMU TCLK{1,2} pins, groups and functions to the R8A7795 ES1.x SoC. Signed-off-by: -
Takeshi Kihara authored
This patch adds TMU TCLK{1,2} pins, groups and functions to the R8A7795 SoC. Signed-off-by: -
Takeshi Kihara authored
This patch adds HDMI0 CEC pin, group and function to the R8A7796 SoC. Signed-off-by:
-
Takeshi Kihara authored
This patch adds HDMI0 CEC pin, group and function to the R8A7795 ES1.x SoC. Signed-off-by:
-
Takeshi Kihara authored
This patch adds HDMI0 CEC pin, group and function to the R8A7795 SoC. Signed-off-by:
-
Takeshi Kihara authored
This patch fixes to set IPSR and MOD_SEL when using NFDATA{14,15}_A and NF{RB,WP}_N_A pin function is selected. And renamess MOD_SEL2 bit22 value definition name to SEL_NDFC. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: -
Takeshi Kihara authored
This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment for SSI pins group. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by:
-
Takeshi Kihara authored
This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment for SSI pins group. This is a correction because MOD_SEL register specification for R8A7795 ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: b205914c ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by:
-
Ulrich Hecht authored
This patch adds DU pins, groups and function for the R8A77995 (D3) SoC. Signed-off-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by:
-
- 13 Feb, 2018 1 commit
-
-
Linus Walleij authored
The MUSB block in the Nomadik has two pin settings: high speed or full speed. These correspond to two unique pin group settings: all pins set to function B for high speed and all set to function C for full speed. Full speed uses more pins than high speed. Signed-off-by:
-
- 12 Feb, 2018 5 commits
-
-
Markus Elfring authored
A string which did not contain a data format specification should be put into a sequence. Thus use the corresponding function "seq_puts". This issue was detected by using the Coccinelle software. Signed-off-by:
Markus Elfring <elfring@users.sourceforge.net> Signed-off-by:
-
Geert Uytterhoeven authored
R8A7778 is R-Car (not R-Mobile) M1. Signed-off-by:
-
Bjorn Andersson authored
The base of the TLMM gpiochip should not be statically defined as 0, fix this to not artificially restrict the existence of multiple pinctrl-msm devices. Fixes: f365be09 ("pinctrl: Add Qualcomm TLMM driver") Reported-by:
Timur Tabi <timur@codeaurora.org> Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
-
Jan Kundrát authored
This is a bit more involved because the pinctrl core so far always assumed that one device (with a unique dev_name) only contains a single pinctrl thing. This is not true for the mcp23s08 driver for chips connected over SPI. They have a "logical address" which means that several chips can share one physical CS signal. A downside of this patch are some possibly ugly names for the debugfs entries, such as "spi1.1-mcp23xxx-pinctrl.2", etc. Signed-off-by:
-
Jan Kundrát authored
When several devices are sharing one hardware SPI CS, there is no visual clue in `lsgpio` or in /sys/kernel/debug/gpio about which one is which one. Stuff depends on the enumeration order, and therefore lower chip addresses always go first, but that's just an implementation detail. This change includes the device-specific address in the debug output: gpiochip4: GPIOs 464-479, parent: spi/spi1.1, mcp23s17.2, can sleep: gpiochip3: GPIOs 480-495, parent: spi/spi1.1, mcp23s17.1, can sleep: Signed-off-by:
-
