- 01 Jul, 2020 40 commits
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Evan Quan authored
Thus redundant code can be dropped. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Evan Quan authored
And some minor changes as dropping unused parameter and label internal used API as static. Signed-off-by:
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Evan Quan authored
Those common operations(for all ASICs) are placed first and followed by ASIC specific ones. While the display related are placed at the last. Signed-off-by:
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Evan Quan authored
Then redundant code can be dropped. Signed-off-by:
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Evan Quan authored
Since smu_smc_table_hw_init() is needed for both .hw_init and .resume. By doing this, we can drop unnecessary operations on resume. Signed-off-by:
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Evan Quan authored
So that we do not need to perform those unnecessary operations again on resume. Signed-off-by:
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Evan Quan authored
Eliminate the buffer allocation and drop the unnecessary overdrive table uploading. Signed-off-by:
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Evan Quan authored
Combine and simplify the logics for setup pptable. Signed-off-by:
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Evan Quan authored
Combine and simplify the logics for retrieving bootup clocks. Signed-off-by:
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Evan Quan authored
To fit common design. And this can simplify the buffer deallocation. Signed-off-by:
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Evan Quan authored
So that code can be shared between .hw_fini and .suspend. Signed-off-by:
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Evan Quan authored
Minor code cleanups. Signed-off-by:
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Evan Quan authored
The macros check if the asic has the callback. So no need to explicitly check. Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in a dml_print message. Fix it. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
We may end up with no planes set yet, depending on the ordering, but we should have the proper blanking state which is either handled by either DPG or TG depending on the hardware generation. Check both to determine the proper blanked state. Bug: https://gitlab.freedesktop.org/drm/amd/issues/781 Fixes: 5fc0cbfa ("drm/amd/display: determine if a pipe is synced by plane state") Cc: nicholas.kazlauskas@amd.com Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Whenever we switch between tiled formats without also switching pixel formats or doing anything else that recreates the DC plane state we can run into underflow or hangs since we're not updating the DML parameters before committing to the hardware. [How] If the update type is FULL then call validate_bandwidth again to update the DML parmeters before committing the state. This is basically just a workaround and protective measure against update types being added DC where we could run into this issue in the future. We can only fully validate the state in advance before applying it to the hardware if we recreate all the plane and stream states since we can't modify what's currently in use. The next step is to update DM to ensure that we're creating the plane and stream states for whatever could potentially be a full update in DC to pre-emptively recreate the state for DC global validation. The workaround can stay until this has been fixed in DM. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
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Alex Deucher authored
Rather than checking the ring type manually. We already set this for MES and KIQ (and a few other special cases). Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
This reverts commit 4541ea81. This changes structs used by the hardware and breaks dpm on some cards. Acked-by:
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Nicholas Kazlauskas authored
To match previous behavior and to not hang the kernel if someone accidentally builds with KGDB enabled. Fixes: 1aad7078 ("drm/amd/display: Make BREAK_TO_DEBUGGER() a debug print") Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Huang Rui authored
Abstract powergate_vcn/jpeg functions, using smu_dpm_set* to implement it. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Acked-by:
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Tianci.Yin authored
The bounding box is still needed by Navi12, temporarily read it from gpu_info firmware. Should be droped when DAL no longer needs it. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
Signed-off-by:
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Alex Deucher authored
Need to guard some new DCN3.0 stuff. Reviewed-by:
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Dmytro Laktyushkin authored
This was done already done for other DCN blocks. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
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Bhawanpreet Lakha authored
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Bhawanpreet Lakha authored
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Bhawanpreet Lakha authored
Initilize function tables for hw programing Signed-off-by:
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Bhawanpreet Lakha authored
Video Package generator. used to prepare avi info, DP info etc Signed-off-by:
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Bhawanpreet Lakha authored
Audio formating Audio related code for setup/control Signed-off-by:
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Bhawanpreet Lakha authored
-Handle DCN3 cases for bios parser and command tables -Add command function tables for DCN3 Signed-off-by:
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Bhawanpreet Lakha authored
Add support for managing resources for DCN3 Signed-off-by:
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Bhawanpreet Lakha authored
Handle DCN3 in amdgpu_dm v2: fix num_pkrs handling Signed-off-by:
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Bhawanpreet Lakha authored
Add HW sequence programing for DCN3 Signed-off-by:
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Bhawanpreet Lakha authored
DMUB (Display Micro-Controller Unit) Used to read/write regs Signed-off-by:
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Bhawanpreet Lakha authored
Add support to program GPIO HW block Signed-off-by:
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Bhawanpreet Lakha authored
Add IWQ services for DCN3, This allows us to create/init and manage irqs for DCN3 Signed-off-by:
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Bhawanpreet Lakha authored
Add support for DML(Display mode library) for bandwidth calculations Signed-off-by:
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Bhawanpreet Lakha authored
Add support to program the DCN3 DWB (Display Writeback) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ | | OPP | | +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by:
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