- 25 Feb, 2010 14 commits
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Ben Skeggs authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
It's very useful to be able to access this without additional tools for debugging purposes. Signed-off-by: -
Luca Barbieri authored
Found by sparse. Signed-off-by:
Luca Barbieri <luca@luca-barbieri.com> Signed-off-by:
Francisco Jerez <currojerez@riseup.net> Signed-off-by:
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Marcin Slusarz authored
i2c_entries seems to be the number of i2c entries, so with index equal to this number, we could read invalid data from i2ctable. Fix it. Signed-off-by:
Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by:
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Marcin Slusarz authored
Reported-by:
Dan Carpenter <error27@gmail.com> Signed-off-by:
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Marcin Slusarz authored
get_tmds_index_reg reads some value from stack when mlv happens to be equal to size of pramdac_table array. Fix it. Reported-by:
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Ben Skeggs authored
This commit breaks the userspace interface, and requires a new libdrm for nouveau to operate again. The multiple GEM_PUSHBUF ioctls that were present in 0.0.15 for compatibility purposes are now gone, and replaced with the new ioctl which allows for multiple push buffers to be submitted (necessary for hw index buffers in the nv50 3d driver) and relocations to be applied on any buffer. A number of other ioctls (CARD_INIT, GEM_PIN, GEM_UNPIN) that were needed for userspace modesetting have also been removed. Signed-off-by:
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Ben Skeggs authored
This allows us to submit push buffers from any memtype to the hardware. We'll need this ability for VRAM index buffers at some point. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
PFIFO on G80 and up has a new mode where the main ring buffer is simply a ring of pointers to indirect buffers containing the actual command/data packets. In order to be able to implement index buffers in the 3D driver we need to be able to submit data-only push buffers right after the cmd packet header, which is only possible using the new command submission method. This commit doesn't make it possible to implement index buffers yet, some userspace interface changes will be required, but it does allow for testing/debugging of the hardware-side support in the meantime. Signed-off-by: -
Maarten Maathuis authored
The nv50 pgraph handler (for example) could reenable pgraph fifo access and that would be bad when pgraph context is being unloaded (we need the guarantee a ctxprog isn't running). Signed-off-by:
Maarten Maathuis <madman2003@gmail.com> Signed-off-by:
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- 23 Feb, 2010 6 commits
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Ben Skeggs authored
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Ben Skeggs authored
This also modifies the unused PRAMIN PT entries to be all zeroes, can't really recall why I used 9/0 initially, just that it didn't work for some reason. It was likely masking a bug elsewhere that's since been fixed. Signed-off-by: -
Ben Skeggs authored
This commit changes nouveau to construct PTEs which look very much like the ones the binary driver creates. I presume that filling multiple PTEs identically with length flags and the physical address of the start of a block of VRAM is a hint to the memory controller that it need not perform additional page table lookups for that range of addresses. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
GART is handled elsewhere, no reason to have the code for it here too. Signed-off-by: -
Francisco Jerez authored
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- 16 Feb, 2010 2 commits
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Francisco Jerez authored
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Ben Skeggs authored
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- 10 Feb, 2010 2 commits
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Matthew Garrett authored
Signed-off-by:
Matthew Garrett <mjg@redhat.com> Signed-off-by:
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Marcin Slusarz authored
Reported-by:
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- 09 Feb, 2010 16 commits
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Maarten Maathuis authored
Unset the bit that indicates that a ctxprog can continue at the end. Signed-off-by:
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Maarten Maathuis authored
ramfc is zero'ed upon destruction, so it's safer to do things in the right order. Signed-off-by:
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Maarten Maathuis authored
- We need to disable pgraph fifo access before checking the current channel, otherwise we could still hit a running ctxprog. - The writes to 0x400500 are already handled by pgraph->fifo_access and are therefore redundant, moreover pgraph fifo access should not be reenabled before current context is set as invalid. So remove them altogether. Signed-off-by:
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Maarten Maathuis authored
- In the current situation the padding that is added is dangerous to write to, userspace could potentially overwrite parts of another bo. - Depth and stencil buffers are supposed to be large enough in general so the waste of memory should be acceptable. - Alternatives are hiding the padding from users or splitting vram into 2 zones. Signed-off-by:
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Ben Skeggs authored
Fixes DVI+VGA on my 9400, and likely a lot of other configurations that got broken by the previos DVI-over-DP fix. Signed-off-by: -
Ben Skeggs authored
With DVI and DP plugged, the DVI clock change interrupts being run can cause DP link training to fail. This adds a spinlock around init table parsing to prevent this. Signed-off-by: -
Ben Skeggs authored
Writes don't return a count, and adding the check broke native DP. Signed-off-by: -
Ben Skeggs authored
It appears we aren't required to do memory sizing ourselves on nv40 either. NV40 init tables read a strap from PEXTDEV_BOOT_0 into a CRTC register, and then later use that value to select a memory configuration (written to PFB_CFG0, just like INIT_COMPUTE_MEM on earlier cards) with INIT_IO_RESTRICT_PROG. Signed-off-by: -
Marcin Kościelnicki authored
Signed-off-by:
Marcin Kościelnicki <koriakin@0x04.net> Signed-off-by:
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Marcin Kościelnicki authored
We used single shared fbops struct and patched it at fb init time with pointers to the right variant. On mixed multicard, this meant that it was either sending NV50-style commands to all cards, or NV04-style commands to all cards. Signed-off-by:
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Julia Lawall authored
Test the just-allocated value for NULL rather than some other value. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression x,y; statement S; @@ x = \(kmalloc\|kcalloc\|kzalloc\)(...); ( if ((x) == NULL) S | if ( - y + x == NULL) S ) // </smpl> Signed-off-by:
Julia Lawall <julia@diku.dk> Cc: David Airlie <airlied@linux.ie> Cc: Ben Skeggs <bskeggs@redhat.com> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Luca Barbieri authored
nouveau_gem_ioctl_cpu_prep calls ttm_bo_wait without the bo lock held. ttm_bo_wait unlocks that lock, and so must be called with it held. Currently this bug causes libdrm nouveau_bo_busy() to hang the machine. Signed-off-by: Luca Barbieri <luca at luca-barbieri.com> Acked-by:
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Francisco Jerez authored
Apparently, they generate a PFIFO interrupt each time one of the semaphore methods is executed if its ctxdma wasn't manually marked as valid. This patch makes it flip the valid bit in response to the DMA_SEMAPHORE method (which triggers the IRQ even for a valid ctxdma). Signed-off-by:
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Marcin Kościelnicki authored
On nv50, this will be needed by applications using CUDA to know how much stack/local memory to allocate. Signed-off-by:
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Marcin Kościelnicki authored
noaccel=1 disables all acceleration and doesn't even attempt initialising PGRAPH+PFIFO, nofbaccel=1 only makes fbcon unaccelerated. Signed-off-by:
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Ben Skeggs authored
Due to a thinko, these were previously forced to VRAM even if we allocated them in GART. This commit fixes that bug, but keeps the previous behaviour of using VRAM by default until it's been tested properly across more chipsets. Signed-off-by:
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