- 26 Sep, 2017 40 commits
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Christian König authored
Just set the CPU access required flag when we pin it. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Monk Liu authored
this fix memory leak due to request_firmware after driver unloaded v2: release gmc firmware for gmc6/7/8 as well Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Monk Liu authored
fix missing finish uvd enc_ring. v2: since the adev pointer check in already in ring_fini so drop the check outsider Signed-off-by:
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Monk Liu authored
this way after KIQ MQD released in drv unloading, CPC can still let KIQ access this MQD thus RLCV SAVE_VF will not fail v2: always use VRAM domain for KIQ MQD no matter BM or SRIOV Signed-off-by:
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Monk Liu authored
v2: move kcq_disable out of SRIOV, make it genearal Signed-off-by:
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Monk Liu authored
only with this way we can debug the VMC page fault issue Signed-off-by:
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Yong Zhao authored
Use it to replace the hard coded value in amdgpu_vm_bo_update_mapping(). Signed-off-by:
Yong Zhao <yong.zhao@amd.com> Reviewed-by:
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Yong Zhao authored
When max_bytes is not 8 bytes aligned and bo size is larger than max_bytes, the last 8 bytes in a ttm node may be left unchanged. For example, on pre SDMA 4.0, max_bytes = 0x1fffff, and the bo size is 0x200000, the problem will happen. In order to fix the problem, we separately store the max nums of PTEs/PDEs a single operation can set in amdgpu_vm_pte_funcs structure, rather than inferring it from bytes limit of SDMA constant fill, i.e. fill_max_bytes. Together with the fix, we replace the hard code value "10" in amdgpu_vm_bo_update_mapping() with the corresponding values from structure amdgpu_vm_pte_funcs. Signed-off-by:
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Yong Zhao authored
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Christian König authored
Use 2MB fragment size by default for older hardware generations as well. Signed-off-by:
John Bridgman <john.bridgman@amd.com> Reviewed-by:
Roger He <Hongbo.He@amd.com> Signed-off-by:
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Xiangliang.Yu authored
SRIOV doesn't implement PMC capability of PCIe, so it can't update power state by reading PMC register. Currently, amdgpu driver doesn't disable pci device when removing driver, the enable_cnt of pci device will not be decrease to 0. When reloading driver, pci_enable_device will do nothing as enable_cnt is not zero. And power state will not be updated as PMC is not support. So current_state of pci device is not D0 state and pci_enable_msi return fail. Add pci_disable_device when remmoving driver to fix the issue. Signed-off-by:
Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by:
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Rex Zhu authored
currently, not all asics implement this callback function so not return error to avoid powerplay initialize failed in those asices Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Evan Quan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Eric Huang authored
Change to more meaningful range that triggers thermal interrupts. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Eric Huang authored
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Eric Huang authored
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Eric Huang authored
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Tom St Denis authored
We discovered that on some devices even with iommu enabled you can access all of system memory through the iommu translation. Therefore, we revert the read method to the translation only service and drop the write method completely. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Evan Quan authored
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Evan Quan authored
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Monk Liu authored
GPU reset will require all hw doing hw_init thus ucode_init_bo will be invoked again, which lead to memory leak skip the fw_buf allocation during sriov gpu reset to avoid memory leak. Signed-off-by:
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Monk Liu authored
otherwise a gpu hang will make application couldn't be killed under timedout=0 mode v2: Fix memoryleak job/job->s_fence issue unlock mn remove the ERROR msg after waiting being interrupted Signed-off-by:
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Monk Liu authored
RLC need CSB registers initiated under SRIOV during world switch otherwise the clear state buffer behav will not be recovered to current VF scheme after switch back Signed-off-by:
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Horace Chen authored
increase timeout to 12 seconds,because there may have multiple FLR waiting for done, the waiting time of events may be long, increase to 12s to reduce timeout failure. Signed-off-by:
Horace Chen <horace.chen@amd.com> Acked-by:
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Monk Liu authored
bo_free on csa is too late to put in amdgpu_fini because that time ttm is already finished, Move it earlier to avoid the page fault. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
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Monk Liu authored
FRAME_CONTROL(begin) is needed for vega10 due to ucode logic change, it can fix some CTS random fail under gfx preemption enabled mode. Signed-off-by:
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Monk Liu authored
At least for SRIOV we found reload PSP fw during gpu reset cause PSP hang. Signed-off-by:
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Monk Liu authored
currently in_reset is only used in sriov gpu reset, and it will be used for other non-gfx hw component later, like PSP, so move it from gfx to adev and rename to in_sriov_reset make more sense. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
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Ken Wang authored
V2 Signed-off-by:
Ken Wang <Ken.Wang@amd.com> Reviewed-by:
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Rex Zhu authored
fix checkpatch.pl WARNING: Prefer 'unsigned int' to bare use of 'unsigned' Reviewed-by:
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Leo Liu authored
Requested by SRIOV, the clearance of the bit moved into firmware Signed-off-by:
Leo Liu <leo.liu@amd.com> Acked-by:
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Xiangliang.Yu authored
Port it from sdma4 for wptr polling usage. Signed-off-by:
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