- 24 Nov, 2014 29 commits
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Andrew Bresticker authored
The MIPS GIC supports 7 local interrupts, 2 of which are the GIC local watchdog and count/compare timer. The remainder are CPU interrupts which may optionally be re-routed through the GIC. GIC hardware IRQs 0-6 are now used for local interrupts while hardware IRQs 7+ are used for external (shared) interrupts. Note that the 5 CPU interrupts may not be re-routable through the GIC. In that case mapping will fail and the vectors reported in C0_IntCtl should be used instead. gic_get_c0_compare_int() and gic_get_c0_perfcount_int() will return the correct IRQ number to use for the C0 timer and perfcounter interrupts based on the routability of those interrupts through the GIC. A separate irq_chip, with callbacks that mask/unmask the local interrupt on all CPUs, is used for the C0 timer and performance counter interrupts since all other platforms do not use the percpu IRQ API for those interrupts. Malta, SEAD-3, and the GIC clockevent driver have been updated to use local interrupts and the R4K clockevent driver has been updated to poll for C0 timer interrupts through the GIC when the GIC is present. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Acked-by:
Jason Cooper <jason@lakedaemon.net> Reviewed-by:
Qais Yousef <qais.yousef@imgtec.com> Tested-by:
Ralf Baechle <ralf@linux-mips.org>
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Andrew Bresticker authored
GIC edge-triggered interrupts must be acknowledged by clearing the edge detector via a write to GIC_SH_WEDGE. Create a separate edge-triggered irq_chip with the appropriate irq_ack() callback. This also allows us to get rid of gic_irq_flags. Signed-off-by:
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Andrew Bresticker authored
Instead of requiring platforms to define the correct GIC_NUM_INTRS, use the value reported in GIC_SH_CONFIG. Signed-off-by:
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Andrew Bresticker authored
Now that the GIC properly uses IRQ domains, kill off the per-platform routing tables that were used to make the GIC appear transparent. This includes: - removing the mapping tables and the support for applying them, - moving GIC IPI support to the GIC driver, - properly routing the i8259 through the GIC on Malta, and - updating IRQ assignments on SEAD-3 when the GIC is present. Platforms no longer will pass an interrupt mapping table to gic_init. Instead, they will pass the CPU interrupt vector (2 - 7) that they expect the GIC to route interrupts to. Note that in EIC mode this value is ignored and all GIC interrupts are routed to EIC vector 1. Signed-off-by:
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Andrew Bresticker authored
Use a simple IRQ domain for the MIPS GIC. Remove the gic_platform_init callback as it's no longer necessary for it to set the irqchip. Signed-off-by:
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Andrew Bresticker authored
If the online CPU check in gic_set_affinity() fails, return a proper errno value instead of -1. Signed-off-by:
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Andrew Bresticker authored
Implement an irq_set_type callback for the GIC which is used to set the polarity and trigger type of GIC interrupts. Signed-off-by:
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Andrew Bresticker authored
There's no need for platforms to have their own GIC irq_ack/irq_eoi callbacks. irq_ack need only clear the GIC's edge detector on edge-triggered interrupts and there's no need at all for irq_eoi. Also get rid of the mask_ack callback since it's not necessary either. Signed-off-by:
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Andrew Bresticker authored
Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC. Signed-off-by:
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Andrew Bresticker authored
Define a generic MIPS_GIC_IRQ_BASE which should be suitable for all current boards in <mach-generic/irq.h>. Signed-off-by:
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Andrew Bresticker authored
The GIC on Malta boards supports a total of 47 interrupts (40 shared and 7 local) and is assigned a base of 24. This overlaps with the MSC01 interrupt assignments which have a base of 64, so move the MSC01 interrupt base back a bit to give the GIC some room. Signed-off-by:
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Andrew Bresticker authored
In preparation for GIC IRQ domain support, assign a GIC IRQ base that does not overlap with the CPU IRQs. Note that this breaks SEAD-3 when the GIC is in EIC mode, though I'm not convinced it was working before either. It will be fixed in the following patches. Signed-off-by:
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Andrew Bresticker authored
It's a duplicate of sead3-platform.c and is not even compiled. Remove it before we start fixing up IRQ assignments. Signed-off-by:
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Andrew Bresticker authored
Nothing calls gic_{enable,disable}_interrupt() any more. Signed-off-by: -
Andrew Bresticker authored
Currently interrupt vectors 2 and 5 are left disabled on secondary CPUs. Since systems using CPS must also have a GIC, which is responsible for routing all external interrupts and can map them to any hardware interrupt vector, enable the remaining vectors. The two software interrupt vectors are left disabled since they are not used with CPS. Signed-off-by:
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Andrew Bresticker authored
The hardware perf event driver and oprofile interpret the global cp0_perfcount_irq differently: in the hardware perf event driver it is an offset from MIPS_CPU_IRQ_BASE and in oprofile it is the actual IRQ number. This still works most of the time since MIPS_CPU_IRQ_BASE is usually 0, but is clearly wrong. Since the performance counter interrupt may vary from platform to platform like the C0 timer interrupt, add the optional get_c0_perfcount_int hook which returns the IRQ number of the performance counter. The hook should return < 0 if the performance counter interrupt is shared with the timer. If the hook is not present, the CPU vector reported in C0_IntCtl (cp0_perfcount_irq) is used. Signed-off-by:
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Andrew Bresticker authored
Create a legacy IRQ domain for the 16 i8259 interrupts. Signed-off-by:
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Andrew Bresticker authored
When mapping an interrupt in the CPU IRQ domain, set the vint handler for that interrupt if the CPU uses vectored interrupt handling. Signed-off-by:
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Andrew Bresticker authored
For platforms which boot with device-tree or have correctly chained all external interrupt controllers, a generic plat_irq_dispatch() can be used. Implement a plat_irq_dispatch() which simply handles all the pending interrupts as reported by C0_Cause. Signed-off-by:
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Andrew Bresticker authored
mips_cpu_intc_init() is used for DT-based initialization of the CPU IRQ domain. Give it a more appropriate name. Signed-off-by:
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Andrew Bresticker authored
Use an IRQ domain for the 8 CPU IRQs in both the DT and non-DT cases. Signed-off-by:
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Markos Chandras authored
Add new 'noftlb' kernel command line option to disable the FTLB. Since the kernel command line is not available when probing and enabling the CPU features in cpu_probe(), we let the kernel configure the FTLB during the config4 decode operation and we disable the FTLB later on, once the command line has become available to us. This should have no negative effects since FTLB isn't used so early in the boot process. FTLB increases the effective TLB size leading to less TLB misses. However, sometimes it's useful to be able to disable it when debugging memory related core features or other hardware components. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/7586/Signed-off-by:
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Joe Perches authored
Use the much more common pr_warn instead of pr_warning with the goal of removing pr_warning eventually. Other miscellanea: o Coalesce formats o Realign arguments Signed-off-by:
Joe Perches <joe@perches.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: LKML <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/7935/Signed-off-by:
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Sergey Ryazanov authored
Caller (generic PCI code) already do proper locking so no need to add another one here. Local PCI read/write functions are never called simultaneously, also they do not require synchronization with the PCI controller ops, since they are used before the controller registration. Signed-off-by:
Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Cc: Gabor Juhos <juhosg@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/7603/Signed-off-by:
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Sergey Ryazanov authored
Caller (generic PCI code) already do proper locking so no need to add another one here. Signed-off-by:
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Sergey Ryazanov authored
Caller (generic PCI code) already do proper locking so no need to add another one here. Signed-off-by:
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Sergey Ryazanov authored
Caller (generic PCI code) already do proper locking so no need to add another one here. Signed-off-by:
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Eunbong Song authored
Currently, arch_trigger_all_cpu_backtrace() is defined in only x86 and sparc which have an NMI. But in case of softlockup, it could be possible to dump backtrace of all cpus. and this could be helpful for debugging. for example, if system has 2 cpus. CPU 0 CPU 1 acquire read_lock() try to do write_lock() ,,, missing read_unlock() In this case, softlockup will occur becasuse CPU 0 does not call read_unlock(). And dump_stack() print only backtrace for "CPU 0". If CPU1's backtrace is printed it's very helpful. [ralf@linux-mips.org: Fixed whitespace and formatting issues.] Signed-off-by:
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Ralf Baechle authored
Based on the spatch @@ expression e; @@ - return (e); + return e; with heavy hand editing because some of the changes are either whitespace or identation only or result in excessivly long lines. Signed-off-by:
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- 23 Nov, 2014 11 commits
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Linus Torvalds authored
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Andy Lutomirski authored
x86 call do_notify_resume on paranoid returns if TIF_UPROBE is set but not on non-paranoid returns. I suspect that this is a mistake and that the code only works because int3 is paranoid. Setting _TIF_NOTIFY_RESUME in the uprobe code was probably a workaround for the x86 bug. With that bug fixed, we can remove _TIF_NOTIFY_RESUME from the uprobes code. Reported-by:
Oleg Nesterov <oleg@redhat.com> Acked-by:
Srikar Dronamraju <srikar@linux.vnet.ibm.com> Acked-by:
Borislav Petkov <bp@suse.de> Signed-off-by:
Andy Lutomirski <luto@amacapital.net> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Thomas Gleixner authored
Chris bisected a NULL pointer deference in task_sched_runtime() to commit 6e998916 'sched/cputime: Fix clock_nanosleep()/clock_gettime() inconsistency'. Chris observed crashes in atop or other /proc walking programs when he started fork bombs on his machine. He assumed that this is a new exit race, but that does not make any sense when looking at that commit. What's interesting is that, the commit provides update_curr callbacks for all scheduling classes except stop_task and idle_task. While nothing can ever hit that via the clock_nanosleep() and clock_gettime() interfaces, which have been the target of the commit in question, the author obviously forgot that there are other code paths which invoke task_sched_runtime() do_task_stat(() thread_group_cputime_adjusted() thread_group_cputime() task_cputime() task_sched_runtime() if (task_current(rq, p) && task_on_rq_queued(p)) { update_rq_clock(rq); up->sched_class->update_curr(rq); } If the stats are read for a stomp machine task, aka 'migration/N' and that task is current on its cpu, this will happily call the NULL pointer of stop_task->update_curr. Ooops. Chris observation that this happens faster when he runs the fork bomb makes sense as the fork bomb will kick migration threads more often so the probability to hit the issue will increase. Add the missing update_curr callbacks to the scheduler classes stop_task and idle_task. While idle tasks cannot be monitored via /proc we have other means to hit the idle case. Fixes: 6e998916 'sched/cputime: Fix clock_nanosleep()/clock_gettime() inconsistency' Reported-by:
Chris Mason <clm@fb.com> Reported-and-tested-by:
Borislav Petkov <bp@alien8.de> Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@kernel.org> Cc: Stanislaw Gruszka <sgruszka@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Signed-off-by:
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Linus Torvalds authored
Merge x86-64 iret fixes from Andy Lutomirski: "This addresses the following issues: - an unrecoverable double-fault triggerable with modify_ldt. - invalid stack usage in espfix64 failed IRET recovery from IST context. - invalid stack usage in non-espfix64 failed IRET recovery from IST context. It also makes a good but IMO scary change: non-espfix64 failed IRET will now report the correct error. Hopefully nothing depended on the old incorrect behavior, but maybe Wine will get confused in some obscure corner case" * emailed patches from Andy Lutomirski <luto@amacapital.net>: x86_64, traps: Rework bad_iret x86_64, traps: Stop using IST for #SS x86_64, traps: Fix the espfix64 #DF fixup and rewrite it in C -
Andy Lutomirski authored
It's possible for iretq to userspace to fail. This can happen because of a bad CS, SS, or RIP. Historically, we've handled it by fixing up an exception from iretq to land at bad_iret, which pretends that the failed iret frame was really the hardware part of #GP(0) from userspace. To make this work, there's an extra fixup to fudge the gs base into a usable state. This is suboptimal because it loses the original exception. It's also buggy because there's no guarantee that we were on the kernel stack to begin with. For example, if the failing iret happened on return from an NMI, then we'll end up executing general_protection on the NMI stack. This is bad for several reasons, the most immediate of which is that general_protection, as a non-paranoid idtentry, will try to deliver signals and/or schedule from the wrong stack. This patch throws out bad_iret entirely. As a replacement, it augments the existing swapgs fudge into a full-blown iret fixup, mostly written in C. It's should be clearer and more correct. Signed-off-by:
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Andy Lutomirski authored
On a 32-bit kernel, this has no effect, since there are no IST stacks. On a 64-bit kernel, #SS can only happen in user code, on a failed iret to user space, a canonical violation on access via RSP or RBP, or a genuine stack segment violation in 32-bit kernel code. The first two cases don't need IST, and the latter two cases are unlikely fatal bugs, and promoting them to double faults would be fine. This fixes a bug in which the espfix64 code mishandles a stack segment violation. This saves 4k of memory per CPU and a tiny bit of code. Signed-off-by:
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Andy Lutomirski authored
There's nothing special enough about the espfix64 double fault fixup to justify writing it in assembly. Move it to C. This also fixes a bug: if the double fault came from an IST stack, the old asm code would return to a partially uninitialized stack frame. Fixes: 3891a04aSigned-off-by:
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds authored
Pull ARM SoC fixes from Olof Johansson: "A collection of fixes this week: - A set of clock fixes for shmobile platforms - A fix for tegra that moves serial port labels to be per board. We're choosing to merge this for 3.18 because the labels will start being parsed in 3.19, and without this change serial port numbers that used to be stable since the dawn of time will change numbers. - A few other DT tweaks for Tegra. - A fix for multi_v7_defconfig that makes it stop spewing cpufreq errors on Arndale (Exynos)" * tag 'armsoc-for-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: multi_v7_defconfig: fix failure setting CPU voltage by enabling dependent I2C controller ARM: tegra: roth: Fix SD card VDD_IO regulator ARM: tegra: Remove eMMC vmmc property for roth/tn7 ARM: dts: tegra: move serial aliases to per-board ARM: tegra: Add serial port labels to Tegra124 DT ARM: shmobile: kzm9g legacy: Set i2c clks_per_count to 2 ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock ARM: shmobile: r8a7790: Fix SD3CKCR address to device tree ARM: shmobile: r8a7740 legacy: Correct IIC0 parent clock ARM: shmobile: r8a7740 legacy: Add missing INTCA clock for irqpin module ARM: shmobile: r8a7790: Fix SD3CKCR address ARM: dts: sun6i: Re-parent ahb1_mux to pll6 as required by dma controller -
git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpuLinus Torvalds authored
Pull percpu fix from Tejun Heo: "This contains one patch to fix a race condition which can lead to percpu_ref using a percpu pointer which is corrupted with a set DEAD bit. The bug was introduced while separating out the ATOMIC mode flag from the DEAD flag. The fix is pretty straight forward. I just committed the patch to the percpu tree but am sending out the pull request early as I'll be on vacation for a week. The patch should be fairly safe and while the latency will be higher I'll be checking emails" * 'for-3.18-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu: percpu-ref: fix DEAD flag contamination of percpu pointer
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git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux-btrfsLinus Torvalds authored
Pull btrfs deadlock fix from Chris Mason: "This has a fix for a long standing deadlock that we've been trying to nail down for a while. It ended up being a bad interaction with the fair reader/writer locks and the order btrfs reacquires locks in the btree" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux-btrfs: btrfs: fix lockups from btrfs_clear_path_blocking
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Tejun Heo authored
While decoupling ATOMIC and DEAD flags, f47ad457 ("percpu_ref: decouple switching to percpu mode and reinit") updated __ref_is_percpu() so that it only tests ATOMIC flag to determine whether the ref is in percpu mode or not; however, while DEAD implies ATOMIC, the two flags are set separately during percpu_ref_kill() and if __ref_is_percpu() races percpu_ref_kill(), it may see DEAD w/o ATOMIC. Because __ref_is_percpu() returns @ref->percpu_count_ptr value verbatim as the percpu pointer after testing ATOMIC, the pointer may now be contaminated with the DEAD flag. This can be fixed by clearing the flag bits before returning the pointer which was the fix proposed by Shaohua; however, as DEAD implies ATOMIC, we can just test for both flags at once and avoid the explicit masking. Update __ref_is_percpu() so that it tests that both ATOMIC and DEAD are clear before returning @ref->percpu_count_ptr as the percpu pointer. Signed-off-by:
Tejun Heo <tj@kernel.org> Reported-and-Reviewed-by:
Shaohua Li <shli@kernel.org> Link: http://lkml.kernel.org/r/995deb699f5b873c45d667df4add3b06f73c2c25.1416638887.git.shli@kernel.org Fixes: f47ad457 ("percpu_ref: decouple switching to percpu mode and reinit")
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