- 24 Jan, 2017 5 commits
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Arnd Bergmann authored
Since linux-4.3, SCSI_DH is a bool symbol, causing a warning in kernelci.org: arch/mips/configs/ip27_defconfig:136:warning: symbol value 'm' invalid for SCSI_DH This updates the defconfig to have the feature built-in. Fixes: 086b91d0 ("scsi_dh: integrate into the core SCSI code") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/15001/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Arnd Bergmann authored
Since linux-4.8, CPU_FREQ_STAT is a bool symbol, causing a warning in kernelci.org: arch/mips/configs/lemote2f_defconfig:42:warning: symbol value 'm' invalid for CPU_FREQ_STAT This updates the defconfig to have the feature built-in. Fixes: 1aefc75b ("cpufreq: stats: Make the stats code non-modular") Signed-off-by:
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Arnd Bergmann authored
In linux-4.10-rc, NF_CT_PROTO_UDPLITE and NF_CT_PROTO_DCCP are bool symbols instead of tristate, and kernelci.org reports a bunch of warnings for this, like: arch/mips/configs/malta_kvm_guest_defconfig:63:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE arch/mips/configs/malta_defconfig:62:warning: symbol value 'm' invalid for NF_CT_PROTO_DCCP arch/mips/configs/malta_defconfig:63:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE arch/mips/configs/ip22_defconfig:70:warning: symbol value 'm' invalid for NF_CT_PROTO_DCCP arch/mips/configs/ip22_defconfig:71:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE This changes all the MIPS defconfigs with these symbols to have them built-in. Fixes: 9b91c96c ("netfilter: conntrack: built-in support for UDPlite") Fixes: c51d3901 ("netfilter: conntrack: built-in support for DCCP") Signed-off-by:
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Jaedon Shin authored
Adds SPI device nodes to BCM7xxx MIPS based SoCs. Signed-off-by:
Jaedon Shin <jaedon.shin@gmail.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14990/Signed-off-by:
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James Hogan authored
64-bit pre-r6 kernels output the following broken printk continuation lines during boot: Checking for the multiply/shift bug... no. Checking for the daddiu bug... no. Checking for the daddi bug... no. Fix the printk continuations in cpu-bugs64.c to use pr_cont to restore the correct output: Checking for the multiply/shift bug... no. Checking for the daddiu bug... no. Checking for the daddi bug... no. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14916/Signed-off-by:
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- 03 Jan, 2017 35 commits
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Ralf Baechle authored
Al Viro noticed that we were using two different methods to filter out flags from KBUILD_CFLAGS. Signed-off-by:
Al Viro <viro@zeniv.linux.org.uk>
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Colin Ian King authored
ralink_soc sould be assigned to RT3883_SOC, replace incorrect comparision with assignment. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Fixes: 418d29c8 ("MIPS: ralink: Unify SoC id handling") Cc: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14903/Signed-off-by:
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Paul Burton authored
In systems with CM3 & higher, the L2 cache is inclusive of the L1 dcache. Indicate this such that cpu_has_inclusive_pcaches evaluates true and we avoid some unnecessary cache ops during DMA cache maintenance. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14018/Signed-off-by:
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Paul Burton authored
Physically indexed caches cannot suffer from virtual aliasing, so clear the MIPS_CACHE_ALIASES bit in order to ensure we don't do extra work avoiding aliasing that cannot happen. Signed-off-by:
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Paul Burton authored
The L1 data cache in I6400 CPUs is indexed by physical address bits if an entry for the address is present in the DTLB early enough in the pipelined execution of a memory access instruction. If an entry is not present then it's indexed by virtual address bits, but hardware will check in a later pipeline stage when a DTLB entry has been created whether the virtual address bits used match the physical address bits, and if not will transparently restart the memory access instruction. This means that although it isn't always physically indexed, it appears so to software & we can treat the I6400 L1 data cache as being physically indexed in order to avoid considering aliasing. Signed-off-by:
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Kelvin Cheung authored
This patch changes the OSC clock name to "osc_clk" as expected by all clock users. Signed-off-by:
Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13903/Signed-off-by:
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Paul Burton authored
The netlogic platform can be built for either MIPS32 or MIPS64, and when built for MIPS32 (as by nlm_xlr_defconfig) the use of the dla pseudo-instruction leads to warnings such as the following from recent versions of the GNU assembler: arch/mips/netlogic/common/smpboot.S: Assembler messages: arch/mips/netlogic/common/smpboot.S:62: Warning: dla used to load 32-bit register; recommend using la instead arch/mips/netlogic/common/smpboot.S:63: Warning: dla used to load 32-bit register; recommend using la instead Avoid these warnings by using the PTR_LA macro to make use of the appropriate la or dla pseudo-instruction for the build. Signed-off-by:
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Paul Burton authored
Now that EXPORT_SYMBOL can be used from assembly source, move the EXPORT_SYMBOL invocations for the copy_page & clear_page functions to be alongside their definitions. With this change there are no longer any symbols exported from mips_ksyms.c so remove the file. Signed-off-by:
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Paul Burton authored
Now that EXPORT_SYMBOL can be used from assembly source, move the EXPORT_SYMBOL invocations for the memcpy & memset functions & variants thereof to be alongside their definitions. Signed-off-by:
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Paul Burton authored
Now that EXPORT_SYMBOL can be used from assembly source, move the EXPORT_SYMBOL invocations for the strlen*, strnlen* & strncpy* functions to be alongside their definitions. Signed-off-by:
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Paul Burton authored
Now that EXPORT_SYMBOL can be used from assembly source, move the EXPORT_SYMBOL invocations for the csum_partial_* functions to be alongside their definitions. Signed-off-by:
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Paul Burton authored
It's unclear to me why this wasn't always the case, but move the EXPORT_SYMBOL invocation for invalid_pte_table to be alongside its definition. Signed-off-by:
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Paul Burton authored
Now that EXPORT_SYMBOL can be used from assembly source, move the EXPORT_SYMBOL invocation for _mcount to be alongside its definition. Signed-off-by:
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Paul Burton authored
Now that EXPORT_SYMBOL can be used from assembly source, move the EXPORT_SYMBOL invocations for _save_fp & _save_msa to be alongside their definitions. Signed-off-by:
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Paul Burton authored
When building a kernel targeting a microMIPS ISA, recent GNU linkers will fail the link if they cannot determine that the target of a branch or jump is microMIPS code, with errors such as the following: mips-img-linux-gnu-ld: arch/mips/built-in.o: .text+0x542c: Unsupported jump between ISA modes; consider recompiling with interlinking enabled. mips-img-linux-gnu-ld: final link failed: Bad value or: ./arch/mips/include/asm/uaccess.h:1017: warning: JALX to a non-word-aligned address Placing anything other than an instruction at the start of a function written in assembly appears to trigger such errors. In order to prepare for allowing us to follow function prologue macros with an EXPORT_SYMBOL invocation, end the prologue macros (LEAD, NESTED & FEXPORT) with a .insn directive. This ensures that the start of the function is marked as code, which always makes sense for functions & safely prevents us from hitting the link errors described above. Signed-off-by:Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14508/Signed-off-by:
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Paul Burton authored
When generating TLB exception handling code we write to memory reserved at the handle_tlbl, handle_tlbm & handle_tlbs symbols. Up until now the ISA bit has always been clear simply because the assembly code reserving the space for those functions places no instructions in them. In preparation for marking all LEAF functions as containing code, explicitly clear the ISA bit when calculating the addresses at which to write TLB exception handling code. Signed-off-by:
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Paul Burton authored
Include export.h in the list of generic headers used by the MIPS architecture for use by later patches. Signed-off-by:
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Paul Burton authored
When allocating a struct alias_prop, of_alias_scan() only requested that it be aligned on a 4 byte boundary. The struct contains pointers which leads to us attempting 64 bit writes on 64 bit systems, and if the CPU doesn't support unaligned memory accesses then this causes problems - for example on some MIPS64r2 CPUs including the "mips64r2-generic" QEMU emulated CPU it will trigger an address error exception. Fix this by requesting alignment for the struct alias_prop allocation matching that which the compiler expects, using the __alignof__ keyword. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Grant Likely <grant.likely@secretlab.ca> Cc: Frank Rowand <frowand.list@gmail.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14306/Signed-off-by:
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Ralf Baechle authored
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Marcin Nowakowski authored
Arch-specific implementation of arch_uprobe_copy_ixol is expected to override the weak implementation in generic code. As currently both implementations are marked as weak, it is up to the linker to chose one. Remove the __weak attribute from MIPS code to make sure the correct version is used. Fixes: 40e084a5 ("MIPS: Add uprobes support.") Signed-off-by:
Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14660/Signed-off-by:
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John Crispin authored
Over the years the code has been changed various times leading to argc/argv being defined in a different function to where we actually use the variables. Clean this up by moving them to prom_init_cmdline(). Signed-off-by:
John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14902/Signed-off-by:
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John Crispin authored
MT7621 has highmem. this was previously not working as the required symbol was not selected in the Kconfig file. Signed-off-by:
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John Crispin authored
As we dont use the common clock api yet we need to add this stub to allow building drivers that use the API. Signed-off-by:
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John Crispin authored
There is a typo inside the pinmux setup code. The function is really called utif and not util. This was recently discovered when people were trying to make the UTIF interface work. Signed-off-by:
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John Crispin authored
The mt7620 has a pin that can be used to generate an external reference clock. The pinmux setup was missing the definition of said pin. This patch adds it. Signed-off-by:
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John Crispin authored
This patch adds two additional clocks required by the audio interface of the SoCs. Signed-off-by:
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John Crispin authored
The code does not set the SoC type properly. This went unnoticed until now as the SoC does not share any of the driver code with the other SoCs, until we made the mmc driver work. Signed-off-by:
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Justin Chen authored
Add cacheinfo support for MIPS architectures. Use information from the cpuinfo_mips struct to populate the cacheinfo struct. This allows an architecture agnostic approach, however this also means if cache information is not properly populated within the cpuinfo_mips struct, there is nothing we can do. (I.E. c-r3k.c) Signed-off-by:
Justin Chen <justin.chen@broadcom.com> Cc: f.fainelli@gmail.com Cc: linux-mips@linux-mips.org Cc: bcm-kernel-feedback-list@broadcom.com Patchwork: https://patchwork.linux-mips.org/patch/14650/Signed-off-by:
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Marcin Nowakowski authored
Signed-off-by:
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Marcin Nowakowski authored
Print details of the new kexec image loaded. Based on the original code from commit 221f2c77 ("arm64/kexec: Add pr_debug output") Signed-off-by:
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Marcin Nowakowski authored
Do not reserve memory for the crashkernel if the commandline argument points to a wrong location. This can happen if the location is specified wrong or if the same commandline is reused when starting the crashkernel - in the latter case the reserved memory would point to the location from which the crashkernel is executing. Signed-off-by:
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Marcin Nowakowski authored
When a memory offset is specified through the commandline, add the memory in range PHYS_OFFSET:Y as reserved memory area. Otherwise the bootmem allocator is initialised with low page equal to min_low_pfn = PHYS_OFFSET, and in free_all_bootmem will process pages starting from min_low_pfn instead of PFN(Y). Signed-off-by:
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Marcin Nowakowski authored
If the DTB is located in the target memory area for the relocated kernel it needs to be relocated as well before kernel relocation takes place. After copying the DTB use the new plat_fdt_relocated() API from the relocated kernel to ensure the relocated kernel updates any information that it may have cached about the location of the DTB. plat_fdt_relocated is declared as a weak symbol so that platforms that do not require it do not need to implement the method. Signed-off-by:
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Marcin Nowakowski authored
Add plat_fdt_relocated(void*) API to allow the kernel relocation code to update platform's information about the DTB location if the DTB had to be moved due to being placed in a location used by the relocated kernel. Signed-off-by:
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Marcin Nowakowski authored
early_init_fdt_reserve_self is used to tell the boot memory allocator that a memory is occupied by the DTB, so add it in the MIPS init code to ensure information about the DTB is added to the boot memory array. Signed-off-by:
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