1. 01 Sep, 2017 2 commits
    • Paul Mackerras's avatar
      powerpc: Don't check MSR FP/VMX/VSX enable bits in analyse_instr() · ee0a54d7
      Paul Mackerras authored
      This removes the checks for the FP/VMX/VSX enable bits in the MSR
      from analyse_instr() and adds them to emulate_step() instead.
      
      The reason for this is that we may want to use analyse_instr() in
      a situation where the FP/VMX/VSX register values are stored in the
      current thread_struct and the FP/VMX/VSX enable bits in the MSR
      image in the pt_regs are zero.  Since analyse_instr() doesn't make
      any changes to register state, it is reasonable for it to indicate
      what the effect of an instruction would be even though the relevant
      enable bit is off.
      Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      ee0a54d7
    • Paul Mackerras's avatar
      powerpc: Change analyse_instr so it doesn't modify *regs · 3cdfcbfd
      Paul Mackerras authored
      The analyse_instr function currently doesn't just work out what an
      instruction does, it also executes those instructions whose effect
      is only to update CPU registers that are stored in struct pt_regs.
      This is undesirable because optprobes uses analyse_instr to work out
      if an instruction could be successfully emulated in future.
      
      This changes analyse_instr so it doesn't modify *regs; instead it
      stores information in the instruction_op structure to indicate what
      registers (GPRs, CR, XER, LR) would be set and what value they would
      be set to.  A companion function called emulate_update_regs() can
      then use that information to update a pt_regs struct appropriately.
      
      As a minor cleanup, this replaces inline asm using the cntlzw and
      cntlzd instructions with calls to __builtin_clz() and __builtin_clzl().
      Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
      Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      3cdfcbfd
  2. 31 Aug, 2017 38 commits