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  1. 17 Dec, 2013 1 commit
  2. 25 Nov, 2013 1 commit
    • Emmanuel Grumbach's avatar
      iwlwifi: pcie: fix interrupt coalescing for 7260 / 3160 · 6960a059
      Emmanuel Grumbach authored
      We changed the timeout for the interrupt coealescing for
      calibration, but that wasn't effective since we changed
      that value back before loading the firmware. Since
      calibrations are notification from firmware and not Rx
      packets, this doesn't change anyway - the firmware will
      fire an interrupt straight away regardless of the interrupt
      coalescing value.
      Also, a HW issue has been discovered in 7000 devices series.
      The work around is to disable the new interrupt coalescing
      timeout feature - do this by setting bit 31 in
      CSR_INT_COALESCING.
      This has been fixed in 7265 which means that we can't rely
      on the device family and must have a hint in the iwl_cfg
      structure.
      
      Cc: stable@vger.kernel.org [3.10+]
      Fixes: 99cd4714 ("iwlwifi: add 7000 series device configuration")
      Reviewed-by: default avatarJohannes Berg <johannes.berg@intel.com>
      Signed-off-by: default avatarEmmanuel Grumbach <emmanuel.grumbach@intel.com>
      6960a059
  3. 11 Oct, 2013 1 commit
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  9. 16 Apr, 2012 1 commit
  10. 24 Jan, 2012 1 commit
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  16. 25 Mar, 2011 1 commit
  17. 31 Jan, 2011 1 commit
    • Wey-Yi Guy's avatar
      iwlagn: add IQ inversion support for 2000 series devices · 52e6b85f
      Wey-Yi Guy authored
      The I/Q swapping is extremely important and should be dealt with extra care.
      It will affects OFDM and CCK differently.
      
      For 6000/6005/6030 series devices, the I/Q were swapped, and for 2000 series
      devices, it is in non-swapped status (but its swapped with respected to 6000/6005/6030).
      so the CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER register need to be set to support
      the correct behavior.
      Signed-off-by: default avatarWey-Yi Guy <wey-yi.w.guy@intel.com>
      52e6b85f
  18. 21 Jan, 2011 2 commits
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  25. 21 Dec, 2009 1 commit
    • Reinette Chatre's avatar
      iwlwifi: power up all devices for EEPROM read · f8701fe3
      Reinette Chatre authored
      Recent commits "iwlwifi: remove power-wasting calls to apm_ops.init()" and
      "iwlagn: power up device before initializing EEPROM" had the goal of
      reducing device power consumption from the time the module is loaded until
      the interface is brought up and the device's power saving mechanisms kick
      in. The idea is that once the module is loaded there is no need for the
      device to consume power until the interface is brought up.
      
      With the current solution the device is only powered up during EEPROM read,
      and then so also only if the EEPROM type is OTP. We have found that on
      certain platforms even non-OTP devices require power to be up during EEPROM
      read. On these platforms the driver never loads and the system log contains
      the following:
      
      iwlagn 0000:03:00.0: MAC is in deep sleep!.  CSR_GP_CNTRL = 0x080403D8
      
      We thus now power up all devices during EEPROM read.
      Signed-off-by: default avatarReinette Chatre <reinette.chatre@intel.com>
      Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
      f8701fe3
  26. 23 Nov, 2009 1 commit
    • Ben Cahill's avatar
      iwlagn: Use iwl_write8() for CSR_INT_COALESCING register · 74ba67ed
      Ben Cahill authored
      CSR_INT_COALESCING previously had only one, but now has two single-byte fields.
      With only one single-byte field (lowest order byte) it was okay to write via
      iwl_write32(), but now with two, an iwl_write32() to the lower order field
      clobbers the other field (odd-address CSR_INT_PERIODIC_REG, offset 0x5), and an
      iwl_write32() to CSR_INT_PERIODIC_REG could clobber the lowest byte of the
      next-higher register (CSR_INT, offset 0x8).
      
      Fortunately, no bad side effects have been produced by the iwl_write32()
      usage, due to order of execution (low order byte was always written before
      higher order byte), and the fact that writing "0" to the low byte of the
      next higher register has no effect (only action is when writing "1"s).
      
      Nonetheless, this cleans up the accesses so no bad side effects might occur
      in the future, if execution order changes, or more bit fields get added to
      CSR_INT_COALESCING.
      
      Add some comments regarding periodic interrupt usage.
      Signed-off-by: default avatarBen Cahill <ben.m.cahill@intel.com>
      Signed-off-by: default avatarReinette Chatre <reinette.chatre@intel.com>
      Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
      74ba67ed
  27. 18 Nov, 2009 1 commit
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