1. 03 Apr, 2018 24 commits
    • Palmer Dabbelt's avatar
      RISC-V: Rename CONFIG_CMDLINE_OVERRIDE to CONFIG_CMDLINE_FORCE · f6a11d9f
      Palmer Dabbelt authored
      The device tree code looks for CONFIG_CMDLINE_FORCE, but we were using
      CONFIG_CMDLINE_OVERRIDE.  It looks like this was just a hold over from
      before our device tree conversion -- in fact, we'd already removed the
      support for CONFIG_CMDLINE_OVERRIDE from our arch-specific code so it
      didn't even work any more.
      
      Thanks to Mortiz and Trung for finding the original bug, and for Michael
      for suggeting a better fix.
      
      CC: Trung Tran <trung.tran@ettus.com>
      CC: Michael J Clark <mjc@sifive.com>
      Reviewed-by: default avatarMoritz Fischer <mdf@kernel.org>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      f6a11d9f
    • Palmer Dabbelt's avatar
      RISC-V: Fixes to module loading · 7a8e7da4
      Palmer Dabbelt authored
      This cleans up the module support that was commited earlier to work with
      what's actually emitted from our GCC port as it lands upstream.  Most of
      the work here is adding new relocations to the kernel.
      
      There's some limitations on module loading imposed by the kernel:
      
      * The kernel doesn't support linker relaxation, which is necessary to
        support R_RISCV_ALIGN.  In order to get reliable module building
        you're going to need to a GCC that supports the new '-mno-relax',
        which IIRC isn't going to be out until 8.1.0.  It's somewhat unlikely
        that R_RISCV_ALIGN will appear in a module even without '-mno-relax'
        support, so issues shouldn't be common.
      
      * There is no large code model for RISC-V, which means modules must be
        loaded within a 32-bit signed offset of the kernel.  We don't
        currently have any mechanism for ensuring this memory remains free or
        moving pages around, so issues here might be common.
      
      I fixed a singcle merge conflict in arch/riscv/kernel/Makefile.
      7a8e7da4
    • Palmer Dabbelt's avatar
      RISC-V: Assorted memory model fixes · 2c9046b7
      Palmer Dabbelt authored
      These fixes fall into three categories
      
      * The definiton of __smp_{store_release,load_acquire}, which allow us to
        emit a full fence when unnecessary.
      * Fixes to avoid relying on the behavior of "*.aqrl" atomics, as those
        are specified in the currently released RISC-V memory model draft in
        a way that makes them useless for Linux.  This might change in the
        future, but now the code matches the memory model spec as it's written
        so at least we're getting closer to something sane.  The actual fix is
        to delete the RISC-V specific atomics and drop back to generic
        versions that use the new fences from above.
      * Cleanups to our atomic macros, which are mostly non-functional
        changes.
      
      Unfortunately I haven't given these as thorough of a testing as I
      probably should have, but I've poked through the code and they seem
      generally OK.
      2c9046b7
    • Palmer Dabbelt's avatar
      RISC-V: Add dynamic ftrace support for RISC-V platforms · 1cead2d7
      Palmer Dabbelt authored
      This patch set includes the building blocks of dynamic ftrace features
      for RISC-V machines.  I'm afraid I'm not very familiar with ftrace, but
      the code looks OK to me.  It's been used to track down a performance
      problem in our SPI driver and appears to work acceptably, but we haven't
      given it a whole lot of banging yet so there might still be some bugs
      lurking around somewhere.
      1cead2d7
    • Zong Li's avatar
      RISC-V: Add definition of relocation types · e21d5421
      Zong Li authored
      Signed-off-by: default avatarZong Li <zong@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      e21d5421
    • Zong Li's avatar
      RISC-V: Enable module support in defconfig · 4a632cec
      Zong Li authored
      Signed-off-by: default avatarZong Li <zong@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      4a632cec
    • Zong Li's avatar
      4aad074c
    • Zong Li's avatar
      8e691b16
    • Zong Li's avatar
      RISC-V: Support ALIGN relocation type in kernel module · 29e405cd
      Zong Li authored
      Just fail on align type. Kernel modules loader didn't do relax
      like linker, it is difficult to remove or migrate the code,
      but the remnant nop instructions harm the performaace of module.
      We expect the building module with the no-relax option.
      Signed-off-by: default avatarZong Li <zong@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      29e405cd
    • Zong Li's avatar
    • Zong Li's avatar
      RISC-V: Support HI20/LO12_I/LO12_S relocation type in kernel module · e7456e69
      Zong Li authored
      HI20 and LO12_I/LO12_S relocate the absolute address, the range of
      offset must in 32-bit.
      Signed-off-by: default avatarZong Li <zong@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      e7456e69
    • Zong Li's avatar
      e1910c72
    • Zong Li's avatar
      RISC-V: Support GOT_HI20/CALL_PLT relocation type in kernel module · da975dd4
      Zong Li authored
      For CALL_PLT, emit the plt entry only when offset is more than 32-bit.
      
      For PCREL_LO12, it uses the location of corresponding HI20 to
      get the address of external symbol. It should check the HI20 type
      is the PCREL_HI20 or GOT_HI20, because sometime the location will
      have two or more relocation types.
      For example:
      0:   00000797                auipc   a5,0x0
                           0: R_RISCV_ALIGN        *ABS*
                           0: R_RISCV_GOT_HI20     SYMBOL
      4:   0007b783                ld      a5,0(a5) # 0 <SYMBOL>
                           4: R_RISCV_PCREL_LO12_I .L0
                           4: R_RISCV_RELAX        *ABS*
      Signed-off-by: default avatarZong Li <zong@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      da975dd4
    • Zong Li's avatar
      RISC-V: Add section of GOT.PLT for kernel module · b8bde0ef
      Zong Li authored
      Separate the function symbol address from .plt to .got.plt section.
      
      The original plt entry has trampoline code with symbol address,
      there is a 32-bit padding bwtween jar instruction and symbol address.
      
      Extract the symbol address to .got.plt to reduce the module size.
      Signed-off-by: default avatarZong Li <zong@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      b8bde0ef
    • Zong Li's avatar
      RISC-V: Add sections of PLT and GOT for kernel module · ab1ef68e
      Zong Li authored
      The address of external symbols will locate more than 32-bit offset
      in 64-bit kernel with sv39 or sv48 virtual addressing.
      
      Module loader emits the GOT and PLT entries for data symbols and
      function symbols respectively.
      
      The PLT entry is a trampoline code for jumping to the 64-bit
      real address. The GOT entry is just the data symbol address.
      Signed-off-by: default avatarZong Li <zong@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      ab1ef68e
    • Andrea Parri's avatar
      riscv/atomic: Strengthen implementations with fences · 5ce6c1f3
      Andrea Parri authored
      Atomics present the same issue with locking: release and acquire
      variants need to be strengthened to meet the constraints defined
      by the Linux-kernel memory consistency model [1].
      
      Atomics present a further issue: implementations of atomics such
      as atomic_cmpxchg() and atomic_add_unless() rely on LR/SC pairs,
      which do not give full-ordering with .aqrl; for example, current
      implementations allow the "lr-sc-aqrl-pair-vs-full-barrier" test
      below to end up with the state indicated in the "exists" clause.
      
      In order to "synchronize" LKMM and RISC-V's implementation, this
      commit strengthens the implementations of the atomics operations
      by replacing .rl and .aq with the use of ("lightweigth") fences,
      and by replacing .aqrl LR/SC pairs in sequences such as:
      
        0:      lr.w.aqrl  %0, %addr
                bne        %0, %old, 1f
                ...
                sc.w.aqrl  %1, %new, %addr
                bnez       %1, 0b
        1:
      
      with sequences of the form:
      
        0:      lr.w       %0, %addr
                bne        %0, %old, 1f
                ...
                sc.w.rl    %1, %new, %addr   /* SC-release   */
                bnez       %1, 0b
                fence      rw, rw            /* "full" fence */
        1:
      
      following Daniel's suggestion.
      
      These modifications were validated with simulation of the RISC-V
      memory consistency model.
      
      C lr-sc-aqrl-pair-vs-full-barrier
      
      {}
      
      P0(int *x, int *y, atomic_t *u)
      {
      	int r0;
      	int r1;
      
      	WRITE_ONCE(*x, 1);
      	r0 = atomic_cmpxchg(u, 0, 1);
      	r1 = READ_ONCE(*y);
      }
      
      P1(int *x, int *y, atomic_t *v)
      {
      	int r0;
      	int r1;
      
      	WRITE_ONCE(*y, 1);
      	r0 = atomic_cmpxchg(v, 0, 1);
      	r1 = READ_ONCE(*x);
      }
      
      exists (u=1 /\ v=1 /\ 0:r1=0 /\ 1:r1=0)
      
      [1] https://marc.info/?l=linux-kernel&m=151930201102853&w=2
          https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/hKywNHBkAXM
          https://marc.info/?l=linux-kernel&m=151633436614259&w=2Suggested-by: default avatarDaniel Lustig <dlustig@nvidia.com>
      Signed-off-by: default avatarAndrea Parri <parri.andrea@gmail.com>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Albert Ou <albert@sifive.com>
      Cc: Daniel Lustig <dlustig@nvidia.com>
      Cc: Alan Stern <stern@rowland.harvard.edu>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Boqun Feng <boqun.feng@gmail.com>
      Cc: Nicholas Piggin <npiggin@gmail.com>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Jade Alglave <j.alglave@ucl.ac.uk>
      Cc: Luc Maranget <luc.maranget@inria.fr>
      Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
      Cc: Akira Yokosawa <akiyks@gmail.com>
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: linux-riscv@lists.infradead.org
      Cc: linux-kernel@vger.kernel.org
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      5ce6c1f3
    • Andrea Parri's avatar
      riscv/spinlock: Strengthen implementations with fences · 0123f4d7
      Andrea Parri authored
      Current implementations map locking operations using .rl and .aq
      annotations.  However, this mapping is unsound w.r.t. the kernel
      memory consistency model (LKMM) [1]:
      
      Referring to the "unlock-lock-read-ordering" test reported below,
      Daniel wrote:
      
        "I think an RCpc interpretation of .aq and .rl would in fact
         allow the two normal loads in P1 to be reordered [...]
      
         The intuition would be that the amoswap.w.aq can forward from
         the amoswap.w.rl while that's still in the store buffer, and
         then the lw x3,0(x4) can also perform while the amoswap.w.rl
         is still in the store buffer, all before the l1 x1,0(x2)
         executes.  That's not forbidden unless the amoswaps are RCsc,
         unless I'm missing something.
      
         Likewise even if the unlock()/lock() is between two stores.
         A control dependency might originate from the load part of
         the amoswap.w.aq, but there still would have to be something
         to ensure that this load part in fact performs after the store
         part of the amoswap.w.rl performs globally, and that's not
         automatic under RCpc."
      
      Simulation of the RISC-V memory consistency model confirmed this
      expectation.
      
      In order to "synchronize" LKMM and RISC-V's implementation, this
      commit strengthens the implementations of the locking operations
      by replacing .rl and .aq with the use of ("lightweigth") fences,
      resp., "fence rw,  w" and "fence r , rw".
      
      C unlock-lock-read-ordering
      
      {}
      /* s initially owned by P1 */
      
      P0(int *x, int *y)
      {
              WRITE_ONCE(*x, 1);
              smp_wmb();
              WRITE_ONCE(*y, 1);
      }
      
      P1(int *x, int *y, spinlock_t *s)
      {
              int r0;
              int r1;
      
              r0 = READ_ONCE(*y);
              spin_unlock(s);
              spin_lock(s);
              r1 = READ_ONCE(*x);
      }
      
      exists (1:r0=1 /\ 1:r1=0)
      
      [1] https://marc.info/?l=linux-kernel&m=151930201102853&w=2
          https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/hKywNHBkAXM
          https://marc.info/?l=linux-kernel&m=151633436614259&w=2Signed-off-by: default avatarAndrea Parri <parri.andrea@gmail.com>
      Cc: Palmer Dabbelt <palmer@sifive.com>
      Cc: Albert Ou <albert@sifive.com>
      Cc: Daniel Lustig <dlustig@nvidia.com>
      Cc: Alan Stern <stern@rowland.harvard.edu>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Boqun Feng <boqun.feng@gmail.com>
      Cc: Nicholas Piggin <npiggin@gmail.com>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Jade Alglave <j.alglave@ucl.ac.uk>
      Cc: Luc Maranget <luc.maranget@inria.fr>
      Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
      Cc: Akira Yokosawa <akiyks@gmail.com>
      Cc: Ingo Molnar <mingo@kernel.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: linux-riscv@lists.infradead.org
      Cc: linux-kernel@vger.kernel.org
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      0123f4d7
    • Andrea Parri's avatar
      riscv/barrier: Define __smp_{store_release,load_acquire} · 8d235b17
      Andrea Parri authored
      Introduce __smp_{store_release,load_acquire}, and rely on the generic
      definitions for smp_{store_release,load_acquire}. This avoids the use
      of full ("rw,rw") fences on SMP.
      Signed-off-by: default avatarAndrea Parri <parri.andrea@gmail.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      8d235b17
    • Alan Kao's avatar
      riscv/ftrace: Add HAVE_FUNCTION_GRAPH_RET_ADDR_PTR support · b785ec12
      Alan Kao authored
      In walk_stackframe, the pc now receives the address from calling
      ftrace_graph_ret_addr instead of manual calculation.
      
      Note that the original calculation,
              pc = frame->ra - 4
      is buggy when the instruction at the return address happened to be a
      compressed inst. But since it is not a critical part of ftrace, it is
      ignored for now to ease the review process.
      
      Cc: Greentime Hu <greentime@andestech.com>
      Signed-off-by: default avatarAlan Kao <alankao@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      b785ec12
    • Alan Kao's avatar
      riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support · aea4c671
      Alan Kao authored
      Cc: Greentime Hu <greentime@andestech.com>
      Signed-off-by: default avatarAlan Kao <alankao@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      aea4c671
    • Alan Kao's avatar
      riscv/ftrace: Add ARCH_SUPPORTS_FTRACE_OPS support · 71e736a7
      Alan Kao authored
      Cc: Greentime Hu <greentime@andestech.com>
      Signed-off-by: default avatarAlan Kao <alankao@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      71e736a7
    • Alan Kao's avatar
      riscv/ftrace: Add dynamic function graph tracer support · bc1a4c3a
      Alan Kao authored
      Once the function_graph tracer is enabled, a filtered function has the
      following call sequence:
      
      * ftracer_caller         ==> on/off by ftrace_make_call/ftrace_make_nop
      * ftrace_graph_caller
      * ftrace_graph_call      ==> on/off by ftrace_en/disable_ftrace_graph_caller
      * prepare_ftrace_return
      
      Considering the following DYNAMIC_FTRACE_WITH_REGS feature, it would be
      more extendable to have a ftrace_graph_caller function, instead of
      calling prepare_ftrace_return directly in ftrace_caller.
      
      Cc: Greentime Hu <greentime@andestech.com>
      Signed-off-by: default avatarAlan Kao <alankao@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      bc1a4c3a
    • Alan Kao's avatar
      riscv/ftrace: Add dynamic function tracer support · c15ac4fd
      Alan Kao authored
      We now have dynamic ftrace with the following added items:
      
      * ftrace_make_call, ftrace_make_nop (in kernel/ftrace.c)
        The two functions turn each recorded call site of filtered functions
        into a call to ftrace_caller or nops
      
      * ftracce_update_ftrace_func (in kernel/ftrace.c)
        turns the nops at ftrace_call into a call to a generic entry for
        function tracers.
      
      * ftrace_caller (in kernel/mcount-dyn.S)
        The entry where each _mcount call sites calls to once they are
        filtered to be traced.
      
      Also, this patch fixes the semantic problems in mcount.S, which will be
      treated as only a reference implementation once we have the dynamic
      ftrace.
      
      Cc: Greentime Hu <greentime@andestech.com>
      Signed-off-by: default avatarAlan Kao <alankao@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      c15ac4fd
    • Alan Kao's avatar
      riscv/ftrace: Add RECORD_MCOUNT support · a1d2a6b4
      Alan Kao authored
      Now recordmcount.pl recognizes RISC-V object files. For the mechanism to
      work, we have to disable the linker relaxation.
      
      Cc: Greentime Hu <greentime@andestech.com>
      Signed-off-by: default avatarAlan Kao <alankao@andestech.com>
      Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
      a1d2a6b4
  2. 01 Apr, 2018 1 commit
  3. 31 Mar, 2018 5 commits
    • Linus Torvalds's avatar
      Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 10b84dad
      Linus Torvalds authored
      Pull perf fixes from Ingo Molnar:
       "Two fixlets"
      
      * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        perf/hwbp: Simplify the perf-hwbp code, fix documentation
        perf/x86/intel: Fix linear IP of PEBS real_ip on Haswell and later CPUs
      10b84dad
    • Linus Torvalds's avatar
      Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · ad0500ca
      Linus Torvalds authored
      Pull x86 fixes from Ingo Molnar:
       "Two UV platform fixes, and a kbuild fix"
      
      * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        x86/platform/UV: Fix critical UV MMR address error
        x86/platform/uv/BAU: Add APIC idt entry
        x86/purgatory: Avoid creating stray .<pid>.d files, remove -MD from KBUILD_CFLAGS
      ad0500ca
    • Linus Torvalds's avatar
      Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · 93e04d4a
      Linus Torvalds authored
      Pull x86 PTI fixes from Ingo Molnar:
       "Two fixes: a relatively simple objtool fix that makes Clang built
        kernels work with ORC debug info, plus an alternatives macro fix"
      
      * 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        x86/alternatives: Fixup alternative_call_2
        objtool: Add Clang support
      93e04d4a
    • Linus Torvalds's avatar
      Merge tag 'kbuild-fixes-v4.16-3' of... · b5dbc287
      Linus Torvalds authored
      Merge tag 'kbuild-fixes-v4.16-3' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild
      
      Pull Kbuild fixes from Masahiro Yamada:
      
       - fix missed rebuild of TRIM_UNUSED_KSYMS
      
       - fix rpm-pkg for GNU tar >= 1.29
      
       - include scripts/dtc/include-prefixes/* to kernel header deb-pkg
      
       - add -no-integrated-as option ealier to fix building with Clang
      
       - fix netfilter Makefile for parallel building
      
      * tag 'kbuild-fixes-v4.16-3' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild:
        netfilter: nf_nat_snmp_basic: add correct dependency to Makefile
        kbuild: rpm-pkg: Support GNU tar >= 1.29
        builddeb: Fix header package regarding dtc source links
        kbuild: set no-integrated-as before incl. arch Makefile
        kbuild: make scripts/adjust_autoksyms.sh robust against timestamp races
      b5dbc287
    • Linus Torvalds's avatar
      Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net · a44406ec
      Linus Torvalds authored
      Pull networking fixes from David Miller:
      
       1) Fix RCU locking in xfrm_local_error(), from Taehee Yoo.
      
       2) Fix return value assignments and thus error checking in
          iwl_mvm_start_ap_ibss(), from Johannes Berg.
      
       3) Don't count header length twice in vti4, from Stefano Brivio.
      
       4) Fix deadlock in rt6_age_examine_exception, from Eric Dumazet.
      
       5) Fix out-of-bounds access in nf_sk_lookup_slow{v4,v6}() from Subash
          Abhinov.
      
       6) Check nladdr size in netlink_connect(), from Alexander Potapenko.
      
       7) VF representor SQ numbers are 32 not 16 bits, in mlx5 driver, from
          Or Gerlitz.
      
       8) Out of bounds read in skb_network_protocol(), from Eric Dumazet.
      
       9) r8169 driver sets driver data pointer after register_netdev() which
          is too late. Fix from Heiner Kallweit.
      
      10) Fix memory leak in mlx4 driver, from Moshe Shemesh.
      
      11) The multi-VLAN decap fix added a regression when dealing with device
          that lack a MAC header, such as tun. Fix from Toshiaki Makita.
      
      12) Fix integer overflow in dynamic interrupt coalescing code. From Tal
          Gilboa.
      
      13) Use after free in vrf code, from David Ahern.
      
      14) IPV6 route leak between VRFs fix, also from David Ahern.
      
      * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (81 commits)
        net: mvneta: fix enable of all initialized RXQs
        net/ipv6: Fix route leaking between VRFs
        vrf: Fix use after free and double free in vrf_finish_output
        ipv6: sr: fix seg6 encap performances with TSO enabled
        net/dim: Fix int overflow
        vlan: Fix vlan insertion for packets without ethernet header
        net: Fix untag for vlan packets without ethernet header
        atm: iphase: fix spelling mistake: "Receiverd" -> "Received"
        vhost: validate log when IOTLB is enabled
        qede: Do not drop rx-checksum invalidated packets.
        hv_netvsc: enable multicast if necessary
        ip_tunnel: Resolve ipsec merge conflict properly.
        lan78xx: Crash in lan78xx_writ_reg (Workqueue: events lan78xx_deferred_multicast_write)
        qede: Fix barrier usage after tx doorbell write.
        vhost: correctly remove wait queue during poll failure
        net/mlx4_core: Fix memory leak while delete slave's resources
        net/mlx4_en: Fix mixed PFC and Global pause user control requests
        net/smc: use announced length in sock_recvmsg()
        llc: properly handle dev_queue_xmit() return value
        strparser: Fix sign of err codes
        ...
      a44406ec
  4. 30 Mar, 2018 10 commits