- 03 Apr, 2015 7 commits
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Olof Johansson authored
Merge tag 'imx-soc-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc Merge "ARM: imx: soc changes for 4.1" from Shawn Guo: The i.MX SoC changes for 4.1: - An error handling improvement on imx-weim bus driver - A number of imx6q clock tree update around MIPI support - Add support for i.MX6 GPU/VPU power domain - Enable SMP_ON_UP build for Vybrid - Let MXC_DEBUG_BOARD depend on 3-stack (3DS) boards * tag 'imx-soc-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx: depend MXC debug board on 3DS machines ARM: imx6: gpc: Add PU power domain for GPU/VPU Documentation: Add device tree bindings for Freescale i.MX GPC bus: imx-weim: improve error handling upon child probe-failure ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gate ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gate ARM: imx6q: clk: Change hdmi_isfr clock's parent to be video_27m clock ARM: imx6q: clk: Add the video_27m clock ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition ARM: vf610: use SMP_ON_UP for Vybrid SoC Signed-off-by:
Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Merge tag 'v4.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc Merge "omap soc changes for v4.1" from Tony Lindgren: SoC related changes for omaps. Mostly hwmod related changes via Paul Walmsley <paul@pwsan.com>: OMAP hwmod data changes for AM43xx and DRA7xx for v4.1 Add support for the AM43xx HDQ/1-wire driver and fix the GPTIMER data for DRA7xx. Note that I do not have AM43xx nor DRA7xx boards, and cannot test these patches on those platforms. Basic build, boot, and PM test logs are available at: http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.1/20150324185246/ * tag 'v4.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4 ARM: DRA7: hwmod: Add data for GPTimers 13 through 16 ARM: omap-device: add missed callback for suspend-to-disk ARM: OMAP2: hwmod: AM43XX: Add hwmod support for HDQ-1W Signed-off-by:
Olof Johansson <olof@lixom.net>
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Nicolas Pitre authored
The custom suspend callback is removed for this change. The extra call to exynos_cpu_power_up(() that was present at the end of exynos_suspend() is now relocated to the cpu_is_up callback. Signed-off-by:
Nicolas Pitre <nico@linaro.org> Tested-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Nicolas Pitre authored
Signed-off-by:
Nicolas Pitre <nico@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Nicolas Pitre authored
Currently the cpu argument validity check uses a hardcoded limit of 4. The DCSCB configuration data provides the actual number of CPUs and we already use it elsewhere. Let's improve the cpu argument validity check by using that information instead. Signed-off-by:
Nicolas Pitre <nico@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Nicolas Pitre authored
Signed-off-by:
Nicolas Pitre <nico@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Nicolas Pitre authored
All backends are reimplementing a variation of the same CPU reference count handling. They are also responsible for driving the MCPM special low-level locking. This is needless duplication, involving algorithmic requirements that are not necessarily obvious to the uninitiated. And from past code review experience, those were all initially implemented badly. After 3 years, it is time to refactor as much common code to the core MCPM facility to make the backends as simple as possible. To avoid a flag day, the new scheme is introduced in parallel to the existing backend interface. When all backends are converted over, the compatibility interface could be removed. The new MCPM backend interface implements simpler methods addressing very platform specific tasks performed under lock protection while keeping the algorithmic complexity and race avoidance local to the core code. Signed-off-by:
Nicolas Pitre <nico@linaro.org> Tested-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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- 02 Apr, 2015 1 commit
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Olof Johansson authored
Merge tag 'v4.1-rockchip-soc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/soc Merge "ARM: rockchip: soc code changes for 4.1" from Heiko Stuebner: Some suspend improvements reducing resume time and making sure the watchdog does not reset after 12 hours and a change to constify and staticize some smp parts. * tag 'v4.1-rockchip-soc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: rockchip: disable watchdog during suspend ARM: rockchip: decrease the wait time for resume ARM: rockchip: Constify struct regmap_config and staticize local function Signed-off-by:
Olof Johansson <olof@lixom.net>
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- 27 Mar, 2015 1 commit
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Tony Lindgren authored
Merge tag 'for-v4.1/omap-hwmod-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.1/soc OMAP hwmod data changes for AM43xx and DRA7xx for v4.1 Add support for the AM43xx HDQ/1-wire driver and fix the GPTIMER data for DRA7xx. Note that I do not have AM43xx nor DRA7xx boards, and cannot test these patches on those platforms. Basic build, boot, and PM test logs are available at: http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.1/20150324185246/
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- 24 Mar, 2015 2 commits
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Suman Anna authored
GPTimer 4 is a regular timer and not a secure timer, so fix the hwmod to use the correct hwmod class (even though there are no differences in the class definition itself). Signed-off-by:
Suman Anna <s-anna@ti.com> [paul@pwsan.com: dropped dra7xx_timer_secure_hwmod_class and dra7xx_timer_secure_sysc to avoid compiler warnings] Signed-off-by:
Paul Walmsley <paul@pwsan.com>
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Suman Anna authored
Add the hwmod data for GPTimers 13, 14, 15 and 16. All these timers are present in the L4PER3 clock domain. The corresponding DT nodes are already present but disabled. Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Paul Walmsley <paul@pwsan.com>
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- 16 Mar, 2015 7 commits
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Grygorii Strashko authored
Add missed callback needed for supporting suspend-to-disk (hibernation) mode. Signed-off-by:
Grygorii Strashko <Grygorii.Strashko@linaro.org> Acked-by:
Kevin Hilman <khilman@linaro.org> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Arnd Bergmann authored
Merge tag 'renesas-da9063-da9210-quirk-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Merge "Renesas ARM Based SoC da9063/da9210 Regulator Quirk for v4.1" from Simon Horman: The r8a7790/lager and r8a7791/koelsch development boards have da9063 and da9210 regulators. Both regulators have their interrupt request lines tied to the same interrupt pin (IRQ2) on the SoC. After cold boot or da9063-induced restart, both the da9063 and da9210 seem to assert their interrupt request lines. Hence as soon as one driver requests this irq, it gets stuck in an interrupt storm, as it only manages to deassert its own interrupt request line, and the other driver hasn't installed an interrupt handler yet. To handle this, install a quirk that masks the interrupts in both the da9063 and da9210. This quirk has to run after the i2c master driver has been initialized, but before the i2c slave drivers are initialized. As it depends on i2c, select I2C if one of the affected platforms is enabled in the kernel config. * tag 'renesas-da9063-da9210-quirk-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: lager: Add da9063 PMIC device node for system restart ARM: shmobile: lager dts: Add da9210 regulator interrupt ARM: shmobile: koelsch: Add da9063 PMIC device node for system restart ARM: shmobile: koelsch dts: Add da9210 regulator interrupt ARM: shmobile: R-Car Gen2: Add da9063/da9210 regulator quirk
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Tsahee Zidenberg authored
Add myself as a maintainer for arch/arm/mach-alpine/ Signed-off-by:
Tsahee Zidenberg <tsahee@annapurnalabs.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Tsahee Zidenberg authored
This patch introduces documentation for alpine devicetree bindings. Signed-off-by:
Barak Wasserstrom <barak@annapurnalabs.com> Signed-off-by:
Tsahee Zidenberg <tsahee@annapurnalabs.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Tsahee Zidenberg authored
This patch introduces support for waking up secondary CPU cores on Alpine platform. Signed-off-by:
Barak Wasserstrom <barak@annapurnalabs.com> Signed-off-by:
Tsahee Zidenberg <tsahee@annapurnalabs.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Tsahee Zidenberg authored
Alpine platform includes UART8250 that can be used for early prints. Signed-off-by:
Saeed Bishara <saeed@annapurnalabs.com> Signed-off-by:
Tsahee Zidenberg <tsahee@annapurnalabs.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Tsahee Zidenberg authored
This patch introduces initial architecture and device-tree support. Signed-off-by:
Saeed Bishara <saeed@annapurnalabs.com> Signed-off-by:
Tsahee Zidenberg <tsahee@annapurnalabs.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- 13 Mar, 2015 1 commit
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Stefan Agner authored
Depend the MXC debug board on machines which actually support it. Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- 11 Mar, 2015 11 commits
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git://git.infradead.org/linux-mvebuArnd Bergmann authored
Pull "mvebu soc changes for v4.1 (part #1)" from Gregory CLEMENT: - Add support for a new SoC: Armada 39x * tag 'mvebu-soc-4.1' of git://git.infradead.org/linux-mvebu: Documentation: arm: update supported Marvell EBU processors ARM: mvebu: add core support for Armada 39x devicetree: bindings: add new SMP enable method for Marvell Armada 39x devicetree: bindings: add DT binding for the Marvell Armada 39x SoC family
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Chris Zhong authored
The watchdog clock should be disable in dw_wdt_suspend, but we set a dummy clock to watchdog for rk3288. So the watchdog will continue to work during suspend. And we switch the system clock to 32khz from 24Mhz, during suspend, so the watchdog timer over count will increase to 755 times, about 12.5 hours, the original value is 60 seconds. So watchdog will reset the system over a night, but voltage are all incorrect, then it hang on reset. Signed-off-by:
Chris Zhong <zyw@rock-chips.com> Signed-off-by:
Daniel Kurtz <djkurtz@google.com> Reviewed-by:
Doug Anderson <dianders@chromium.org> Tested-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Chris Zhong authored
The register-default delay time for wait the 24MHz OSC stabilization as well as PMU stabilization is 750ms, let's decrease them to a still safe 30ms. Signed-off-by:
Chris Zhong <zyw@rock-chips.com> Reviewed-by:
Doug Anderson <dianders@chromium.org> Tested-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Krzysztof Kozlowski authored
The regmap_config struct may be const because it is not modified by the driver and regmap_init() accepts pointer to const. Make function rockchip_get_core_reset() static because it is not used outside of the platsmp.c file. Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Philipp Zabel authored
When generic pm domain support is enabled, the PGC can be used to completely gate power to the PU power domain containing GPU3D, GPU2D, and VPU cores. This code triggers the PGC powerdown sequence to disable the GPU/VPU isolation cells and gate power and then disables the PU regulator. To reenable, the reverse powerup sequence is triggered after the PU regulator is enabled again. The GPU and VPU devices in the PU power domain temporarily need to be clocked during powerup, so that the reset machinery can work. [Avoid explicit regulator enabling in probe, unless !PM] Signed-off-by:
Markus Pargmann <mpa@pengutronix.de> Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Philipp Zabel authored
The i.MX6 contains a power controller that controls power gating and sequencing for the SoC's power domains. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Geert Uytterhoeven authored
Add a device node for the da9063 PMIC, with subnodes for rtc and wdt. Regulator support is not yet included. This allows the system to be restarted when the watchdog timer times out, or when a system restart is requested. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
The da9210 regulator is connected to IRQ2. Reflect this in its device node, so the driver can use it when it gains interrupt support. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add a device node for the da9063 PMIC, with subnodes for rtc and wdt. Regulator support is not yet included. This allows the system to be restarted when the watchdog timer times out, or when a system restart is requested. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
The da9210 regulator is connected to IRQ2. Reflect this in its device node, so the driver can use it when it gains interrupt support. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
The r8a7790/lager and r8a7791/koelsch development boards have da9063 and da9210 regulators. Both regulators have their interrupt request lines tied to the same interrupt pin (IRQ2) on the SoC. After cold boot or da9063-induced restart, both the da9063 and da9210 seem to assert their interrupt request lines. Hence as soon as one driver requests this irq, it gets stuck in an interrupt storm, as it only manages to deassert its own interrupt request line, and the other driver hasn't installed an interrupt handler yet. To handle this, install a quirk that masks the interrupts in both the da9063 and da9210. This quirk has to run after the i2c master driver has been initialized, but before the i2c slave drivers are initialized. As it depends on i2c, select I2C if one of the affected platforms is enabled in the kernel config. On koelsch, the following happens: - Cold boot or reboot using the da9063 restart handler: IRQ2 is asserted, installing da9063/da9210 regulator quirk ... i2c i2c-6: regulator_quirk_notify: 1, IRQC_MONITOR = 0x3fb i2c 6-0058: regulator_quirk_notify: 1, IRQC_MONITOR = 0x3fb i2c 6-0058: Detected da9063 i2c 6-0058: Masking da9063 interrupt sources i2c 6-0068: regulator_quirk_notify: 1, IRQC_MONITOR = 0x3fb i2c 6-0068: Detected da9210 i2c 6-0068: Masking da9210 interrupt sources i2c 6-0068: IRQ2 is not asserted, removing quirk - Warm boot (reset button): rcar_gen2_regulator_quirk: IRQ2 is not asserted, not installing quirk Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Tested-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Mark Brown <broonie@kernel.org> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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- 04 Mar, 2015 6 commits
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https://github.com/carlocaione/linux-mesonArnd Bergmann authored
Pull "meson SoC changes" from Carlo Caione: - Add some forgotten documentation - Kconfig changes to enable PINCTRL * tag 'for-v4.0-rc/meson-soc' of https://github.com/carlocaione/linux-meson: of: Define board compatible for MINIX NEO-X8 of: Add vendor prefix for MINIX ARM: meson: select PINCTRL_MESON and ARCH_REQUIRE_GPIOLIB
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Arnd Bergmann authored
Merge tag 'renesas-soc-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Renesas ARM Based SoC Updates for v4.1" from Simon Horman: * Do not make CMA reservation for R-Car Gen2 when HIGHMEM=n * tag 'renesas-soc-for-v4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: No R-Car Gen2 CMA reservation when HIGHMEM=n
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Thomas Petazzoni authored
Now that we support Armada 39x, let's add this family of SoC to the Marvell documentation, and a reference to a link with more details about those processors. Unfortunately, no datasheet is publicly available at this time. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
This commit adds the core support for Armada 39x, which is quite simple: - a new Kconfig option which selects the appropriate clock and pinctrl drivers as well as other common features (GIC, L2 cache, SMP, etc.) - a new DT_MACHINE_START which references the top-level compatible strings supported for the Marvell Armada 39x. - a new SMP enable-method. The mechanism to enable CPUs for Armada 39x appears to be the same as Armada 38x. However, we do not want to use marvell,armada-380-smp in the Device Tree, in the case of the discovery of a subtle difference in the future, which would require changing the Device Tree. And the enable-method isn't a compatible string: you can't specify several values and expect a fallback on the second string if the first one isn't supported. Therefore, we simply declare the SMP enable method "marvell,armada-390-smp" as doing the same thing as the "marvell,armada-380-smp" one. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
This commit updates the ARM CPUs Device Tree binding to document a new enable method of Marvell Armada 39x processors. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
The Marvell Armada 39x is a family of two SoCs: the Armada 390 and the Armada 398, with a slightly different number of interfaces. This commit introduces the Device Tree binding that documents the top-level compatible strings for Armada 39x based platforms. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- 03 Mar, 2015 3 commits
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Linus Torvalds authored
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Daniel Vetter authored
This is a tricky story of the new atomic state handling and the legacy code fighting over each another. The bug at hand is an underrun of the framebuffer reference with subsequent hilarity caused by the load detect code. Which is peculiar since the the exact same code works fine as the implementation of the legacy setcrtc ioctl. Let's look at the ingredients: - Currently our code is a crazy mix of legacy modeset interfaces to set the parameters and half-baked atomic state tracking underneath. While this transition is going we're using the transitional plane helpers to update the atomic side (drm_plane_helper_disable/update and friends), i.e. plane->state->fb. Since the state structure owns the fb those functions take care of that themselves. The legacy state (specifically crtc->primary->fb) is still managed by the old code (and mostly by the drm core), with the fb reference counting done by callers (core drm for the ioctl or the i915 load detect code). The relevant commit is commit ea2c67bb Author: Matt Roper <matthew.d.roper@intel.com> Date: Tue Dec 23 10:41:52 2014 -0800 drm/i915: Move to atomic plane helpers (v9) - drm_plane_helper_disable has special code to handle multiple calls in a row - it checks plane->crtc == NULL and bails out. This is to match the proper atomic implementation which needs the crtc to get at the implied locking context atomic updates always need. See commit acf24a39 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Tue Jul 29 15:33:05 2014 +0200 drm/plane-helper: transitional atomic plane helpers - The universal plane code split out the implicit primary plane from the CRTC into it's own full-blown drm_plane object. As part of that the setcrtc ioctl (which updated both the crtc mode and primary plane) learned to set crtc->primary->crtc on modeset to make sure the plane->crtc assignments statate up to date in commit e13161af Author: Matt Roper <matthew.d.roper@intel.com> Date: Tue Apr 1 15:22:38 2014 -0700 drm: Add drm_crtc_init_with_planes() (v2) Unfortunately we've forgotten to update the load detect code. Which wasn't a problem since the load detect modeset is temporary and always undone before we drop the locks. - Finally there is a organically grown history (i.e. don't ask) around who sets the legacy plane->fb for the various driver entry points. Originally updating that was the drivers duty, but for almost all places we've moved that (plus updating the refcounts) into the core. Again the exception is the load detect code. Taking all together the following happens: - The load detect code doesn't set crtc->primary->crtc. This is only really an issue on crtcs never before used or when userspace explicitly disabled the primary plane. - The plane helper glue code short-circuits because of that and leaves a non-NULL fb behind in plane->state->fb and plane->fb. The state fb isn't a real problem (it's properly refcounted on its own), it's just the canary. - Load detect code drops the reference for that fb, but doesn't set plane->fb = NULL. This is ok since it's still living in that old world where drivers had to clear the pointer but the core/callers handled the refcounting. - On the next modeset the drm core notices plane->fb and takes care of refcounting it properly by doing another unref. This drops the refcount to zero, leaving state->plane now pointing at freed memory. - intel_plane_duplicate_state still assume it owns a reference to that very state->fb and bad things start to happen. Fix this all by applying the same duct-tape as for the legacy setcrtc ioctl code and set crtc->primary->crtc properly. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Paul Bolle <pebolle@tiscali.nl> Cc: Rob Clark <robdclark@gmail.com> Cc: Paulo Zanoni <przanoni@gmail.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Matt Roper <matthew.d.roper@intel.com> Reported-and-tested-by:
Linus Torvalds <torvalds@linux-foundation.org> Reported-by:
Paul Bolle <pebolle@tiscali.nl> Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Sourav Poddar authored
These adds hwmod data for hdq/1w driver on AM43xx. Signed-off-by:
Vignesh R <vigneshr@ti.com> Signed-off-by:
Paul Walmsley <paul@pwsan.com>
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- 02 Mar, 2015 1 commit
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpioLinus Torvalds authored
Pull GPIO fixes from Linus Walleij: "Two GPIO fixes: - Fix a translation problem in of_get_named_gpiod_flags() - Fix a long standing container_of() mistake in the TPS65912 driver" * tag 'gpio-v4.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: gpio: tps65912: fix wrong container_of arguments gpiolib: of: allow of_gpiochip_find_and_xlate to find more than one chip per node
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