- 18 Dec, 2019 40 commits
-
-
Nirmoy Das authored
This sched array can be passed on to entity creation routine instead of manually creating such sched array on every context creation. v2: squash in missing break fix Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Nirmoy Das authored
drm_sched_entity_init() takes drm gpu scheduler list instead of drm_sched_rq list. This makes conversion of drm_sched_rq list to drm gpu scheduler list unnecessary Signed-off-by:
-
Nirmoy Das authored
Entity currently keeps a copy of run_queue list and modify it in drm_sched_entity_set_priority(). Entities shouldn't modify run_queue list. Use drm_gpu_scheduler list instead of drm_sched_rq list in drm_sched_entity struct. In this way we can select a runqueue based on entity/ctx's priority for a drm scheduler. Signed-off-by:
-
Alex Deucher authored
Increment the usage count in emit fence, and decrement in process fence to make sure the GPU is always considered in use while there are fences outstanding. We always wait for the engines to drain in runtime suspend, but in practice that only covers short lived jobs for gfx. This should cover us for longer lived fences. Reviewed-by:
-
Zhan Liu authored
[Why] SMU watermark table (WMTABLE) validity check is missing on Renoir. This validity check is very useful for checking whether WMTABLE is updated successfully. [How] Add SMU watermark validity check. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
-
zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:318:2-3: Unneeded semicolon Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
zhengbin <zhengbin13@huawei.com> Signed-off-by:
-
zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:1967:2-3: Unneeded semicolon Reported-by:
-
zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:110:3-4: Unneeded semicolon drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:133:2-3: Unneeded semicolon drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:163:2-3: Unneeded semicolon drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:191:2-3: Unneeded semicolon Reported-by:
-
zhengbin authored
Fixes coccicheck warning: drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c:412:90-91: Unneeded semicolon Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reported-by:
-
Alex Deucher authored
We already did this for older generations. Reviewed-by:
-
Alex Deucher authored
We already did this for older generations. Reviewed-by:
-
Nikola Cornij authored
[why] It's required for debug purposes. [how] Add a dsc_bpp_increment_div debug option that overrides DPCD BITS_PER_PIXEL_INCREMENT value. The value dsc_bpp_increment_div should be set to is the one after parsing, i.e. it could be 1, 2, 4, 8 or 16 (meaning 1pix, 1/2pix, ..., 1/16pix). Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
-
Anthony Koo authored
[Why] eDP is internal link and link loss is unexpected. It is typically going to be PSR related errors, which is handled separately. [How] Check for eDP and skip check for link loss Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
-
Samson Tam authored
[Why] Cursor disappears for some SLS displays that are rotated 180 and 270 degrees. This occurs when there is no pipe split being done ( ex. 3 or more displays ). The cursor calculations assume pipe splitting is done so when it calculates the new cursor position in hwss.set_cursor_position(), it is out-of-bounds so it disables the cursor in hubp.set_cursor_position(). [How] In non pipe split cases, calculate cursor using viewport size ( width or height ) instead of viewport size * 2 ( the two because pipe splitting divides the rectangle into two ). Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
-
Sung Lee authored
[Why] Previous formula for calculating DPP CLK DTO was hard to understand. [How] Replace with easier to understand formula that produces same results. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
-
Sung Lee authored
[Why] A corner case currently exists where DPP DTO is lowered before pipes are updated to a higher viewport. This causes underflow as the DPPCLK is too low for the current viewport. [How] Only lower DPP DTO when it is safe to lower, or if the newer clocks are higher than the current ones. Signed-off-by:
-
Jun Lei authored
[why] DAL3 should support SRIOV [how] Add support for the virtual dal flag. This flag should skip most/all of DC construction since the HW isn't accessible, but still construct WindowsDM (almost) normally but with only SW display targets Signed-off-by:
-
Aric Cyr authored
Fix manual trigger source correctly be TRIGA for DCN2 rather than MANUAL_FLOW. Signed-off-by:
-
abdoulaye berthe authored
[Why] DCN21 and DCN2 extended timeout support cap is not set correctly. [How] Set extended timeout support for ASIC families to their right values. Signed-off-by:
abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
-
Sung Lee authored
[Why] Previously update_bw_bounding_box for RN was commented out due to incorrect values causing BSOD on Hybrid Graphics. However, commenting out this function also may cause issues such as underflow in certain cases such as 2x4K displays. [How] Fix dram_speed_mts calculations. Update from proper index of clock_limits[] Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
-
Dale Zhao authored
[Why]: According to eDP spec, max T7 delay should be 50 ms. Current code uses 300 retry counters may not be accurate enough for different panels. [How]: Use absolute time stamp to achive accurate delay. Signed-off-by:
Dale Zhao <dale.zhao@amd.com> Reviewed-by:
-
Aric Cyr authored
Signed-off-by:
-
Samson Tam authored
[Why] When we rotate 270 in mixed SLS mode, the recouts occupy the right side of the display. So all the recout_skip_v values are relative to the left side of the display. This causes adjust_vp_and_init_for_seamless_clip() to incorrectly increase the data->viewport.height for that recout. The rotation looks like the bottom half is duplicated twice. [How] recout.x values are being adjusted based on stream->timing.h_border_left. Instead of using h_border_left, use dst.x to represent the border. Shift dst.x by the amount of stream->timing.h_border_left and set stream->timing.h_border_left to 0. Do all the calculations and then revert stream->timing.h_border_left and stream->dst.x back to their original values. When calculating pipe_ctx->plane_res.scl_data.h_active, make sure to use the original stream->timing.h_border_left value. Signed-off-by:
-
Nicholas Kazlauskas authored
[Why] Firmware state and tracebuffer shouldn't be considered stable API between firmware versions. Driver shouldn't be querying anything from firmware state or tracebuffer outside of debugging. Commands are the stable API for this once we have the outbox. [How] Add metadata struct to the end of the data firmware that describes fw_state_size and some reserved area for future use. Drop the tracebuffer and firmware state headers since they can differ per version. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
-
Noah Abradjian authored
[Why] In certain instances, there was a reliance on pipe indexing being accurate. However, this assumption fails with harvesting of pipes 1 or 2, which can occur in production B6 parts. HW hang would occur as a result. [How] Use hubp index for mpcc, and do mpc_init for all theoretical pipes (including disabled ones). Signed-off-by:
Noah Abradjian <noah.abradjian@amd.com> Reviewed-by:
-
Derek Lai authored
[Why] After read the 3rd Edid blocks, we will reset segment to 0, which causes this VR fail to read Edid successfully. [How] Skip to reset segment to 0 for this VR device. Signed-off-by:
Derek Lai <Derek.Lai@amd.com> Reviewed-by:
-
Paul Hsieh authored
[Why] 1. Set second screen only then unplug external monitor 2. Enter to S4 then plug in external monitor 3. Resume from S4, eDP will not turn off when OS set second screen only Sometimes OS will not set eDP power up cause eDP dpms_off keep true then driver skipp disable stream [How] When drvier try to disable stream, add link status condition Signed-off-by:
Paul Hsieh <paul.hsieh@amd.com> Reviewed-by:
-
Hugo Hu authored
Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
-
Nicholas Kazlauskas authored
[Why] The DMUB is put into reset on suspend and is not running on resume, disabling PSR/ABM features. [How] Move the allocation of the framebuffer to sw_init. Do DMUB hardware init and framebuffer filling only from hw_init. On resume the contents of the framebuffer will be invalid so those should be cleared. Signed-off-by:
Roman Li <Roman.Li@amd.com> Acked-by:
-
Nikola Cornij authored
[why] Up to 4 ODM memory pieces are required per ODM combine and cannot overlap, i.e. each ODM "session" has to use its own memory pieces. The ODM-memory mapping is currently broken for generic case. The maximum number of memory pieces is ASIC-dependent, but it's always big enough to satisfy maximum number of ODM combines. Memory pieces are mapped as a bit-map, i.e. one memory piece corresponds to one bit. The OPTC doing ODM needs to select memory pieces by setting the corresponding bits, making sure there's no overlap with other OPTC instances that might be doing ODM. The current mapping works only for OPTC instance indexes smaller than 3. For instance indexes 3 and up it practically maps no ODM memory, causing black, gray or white screen in display configs that include ODM on OPTC instance 3 or up. [how] Statically map two unique ODM memory pieces for each OPTC instance and piece them together when programming ODM combine mode. Signed-off-by:
-
Charlene Liu authored
Add warmup escape support, for diags, in a way that is possible to choose a new or an existing sequence. For achieving this goal, this commit adds separated MCIF buffer as VCN request. Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
-
Josip Pavic authored
[Why] When the global variable pow_buffer_ptr is set to -1, by definition optimizations should not be used to build the regamma. Since translate_from_linear_space unconditionally increments this global, it inadvertently enables the optimization. [How] Increment pow_buffer_ptr only if it is not -1. Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
-
Aric Cyr authored
Signed-off-by:
-
Aric Cyr authored
Signed-off-by:
-
Aric Cyr authored
[Why] Scaling better handled by upper layers before pipe splitting. [How] Remove DC code for integer scaling and force cursor update if viewport or scaling changes occur to prevent underflow from invalid cursor position. Signed-off-by:
-
Martin Leung authored
[why] dc previously had bugs that interfered with the ability to inherit a timing from a device with multiple streams (without flash/blanking). After this fix there is still a dependency on UEFI support. [how] fixed 3 bugs: loaded MPC state, changed bw_optimize flag to a counter instead of a boolean, and reading dpp/disp clk from HW to ensure we don't raise the clock's when we're not supposed to. Signed-off-by:
-
Roman Li authored
[Why] Some 10bit eDP panels don't lightup after we cap bpc to 8. [How] Set default max_bpc to 16 for edp connector type. Signed-off-by:
-
Noah Abradjian authored
[Why] Currently, pipe resources are assigned to an index that matches the pipe position. However, if pipe 1 or 2 is disabled, there will be a gap in the arrays which causes a crash when iterating based on pipe_count. [How] Fix resource construct to assign resources to minimum available array index. Signed-off-by:
-
Eric Yang authored
[Why] Need previously implemented chroma vp wa to work for rotation cases. [How] Implement rotation specific wa. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
-
Noah Abradjian authored
[Why] There is one opp per pipe. For certain RN parts, the fourth pipe is disabled, so there is no opp for it. res_cap->num_opp is hardcoded to 4, so if we use that to iterate over opps we will crash. [How] Use the pipe_count value instead, which is not hardcoded and so will have the correct number. Signed-off-by:
-
