1. 13 May, 2016 7 commits
  2. 12 May, 2016 28 commits
  3. 11 May, 2016 5 commits
    • David S. Miller's avatar
      Merge branch 'mlx5-next' · 6a47a570
      David S. Miller authored
      Saeed Mahameed says:
      
      ====================
      Mellanox 100G mlx5 CQE compression
      
      Introducing ConnectX-4 CQE (Completion Queue Entry) compression feature
      for mlx5 etherent driver.
      
      CQE Compressing reduces PCI overhead by coalescing and compressing multiple CQEs into a
      single merged CQE.  Successful compressing improves message rate especially for small packet
      traffic.
      
      CQE Compressing in details:
      
      Instead of writing full CQEs to memory, multiple almost identical CQEs are merged and compressed.
      Information that is shared between the CQEs is written once, regardless of the number of
      compressed CQEs.  In addition, only the unique information (small amount of bytes compared to
      full CQE size) is written per CQE.
      
      CQE Compression Block:
      
      This block contains multiple compressed CQEs.  CQE Compression Block contains a single copy
      of CQEs properties which are shared between all the compressed CQEs (called Title, see below)
      and multiple mini CQEs (CQEs in compressed form).
      
      Title:
      
      The Title holds information which is shared between all the compressed CQEs in the CQE Compression
      Block.  In each Compression Block there is only a single Title regardless of the number
      of compressed CQEs.
      
      Mini CQE:
      
      A CQE in compressed form that holds some data needed to extract a single full CQE, for example
      8 Bytes instead of 64 Bytes.
      The shared information between all compressed CQEs, which belong to the same CQE Compression
      Block called Title, is written once, and only the unique information in each compressed
      CQE, for example 8 bytes, is written per compressed CQE, called mini CQE.
      
      Since CQE Compression can add overhead to the software (CPU),
      it will be only enabled on "weak/slow" PCI slots, where it can actually help.
      
      Applied on top: c047c3b1 ('netfilter: conntrack: remove uninitialized shadow variable')
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6a47a570
    • Saeed Mahameed's avatar
      net/mlx5e: Enable CQE compression when PCI is slower than link · b797a684
      Saeed Mahameed authored
      We turn the feature ON, only for servers with PCI BW < MAX LINK BW, as it
      helps reducing PCI pressure on weak PCI slots, but it adds some software
      overhead.
      Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
      Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b797a684
    • Tariq Toukan's avatar
      net/mlx5e: Expand WQE stride when CQE compression is enabled · d9d9f156
      Tariq Toukan authored
      Make the MPWQE/Striding RQ default configuration dynamic and not
      statically set at compile time.  Now at driver load we set
      stride size and num strides dynamically.
      
      By default we use same values as before, but when CQE compression
      is enabled, we set larger stride size to benefit from CQE
      compression for larger packets.
      Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
      Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      d9d9f156
    • Tariq Toukan's avatar
      net/mlx5e: CQE compression · 7219ab34
      Tariq Toukan authored
      CQE compression feature is meant to save PCIe bandwidth by
      compressing few CQEs into smaller amount of bytes on PCIe.
      CQE compression can be selectively enabled per CQ.  By default
      is disabled for now and will be enabled later on.
      Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
      Signed-off-by: default avatarEugenia Emantayev <eugenia@mellanox.com>
      Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      7219ab34
    • David S. Miller's avatar
      Merge branch 'more-dsa-probing' · c1869d58
      David S. Miller authored
      Andrew Lunn says:
      
      ====================
      More enabler patches for DSA probing
      
      The complete set of patches for the reworked DSA probing is too big to
      post as once. These subset contains some enablers which are easy to
      review.
      
      Eventually, the Marvell driver will instantiate its own internal MDIO
      bus, rather than have the framework do it, thus allows devices on the
      bus to be listed in the device tree. Initialize the main mutex as soon
      as it is created, to avoid lifetime issues with the mdio bus.
      
      A previous patch renamed all the DSA probe functions to make room for
      a true device probe. However the recent merging of all the Marvell
      switch drivers resulted in mv88e6xxx going back to the old probe
      name. Rename it again, so we can have a driver probe function.
      
      Add minimum support for the Marvell switch driver to probe as an MDIO
      device, as well as an DSA driver. Later patches will then register
      this device with the new DSA core framework.
      
      Move the GPIO reset code out of the DSA code. Different drivers may
      need different reset mechanisms, e.g. via a reset controller for
      memory mapped devices. Don't clutter up the core with this. Let each
      driver implement what it needs.
      
      master_dev is no longer needed in the switch drivers, since they have
      access to a device pointer from the probe function. Remove it.
      
      Let the switch parse the eeprom length from its one device tree
      node. This is required with the new binding when the central DSA
      platform device no longer exists.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      c1869d58