1. 29 Jun, 2017 40 commits
    • David S. Miller's avatar
      Merge branch 'mlx4-dynamic-tc-tx-queues' · fcce2fdb
      David S. Miller authored
      Tariq Toukan says:
      
      ====================
      mlx4_en dynamic TC tx queues
      
      This patchset from Inbar aligns the number of TX queues
      to the actual need, according to the TC configuration.
      
      Series generated against net-next commit:
      2ee87db3 Merge branch 'nfp-get_phys_port_name-for-representors-and-SR-IOV-reorder'
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      fcce2fdb
    • Inbar Karmy's avatar
      net/mlx4_en: Do not allocate redundant TX queues when TC is disabled · ec327f7a
      Inbar Karmy authored
      Currently the number of TX queues that are allocated doesn't depend
      on the number of TCs, the module always loads with max num of UP
      per channel.
      In order to prevent the allocation of unnecessary memory, the
      module will load with minimum number of UPs per channel, and the
      user will be able to control the number of TX queues per channel
      by changing the number of TC to 8 using the tc command.
      The variable num_up will hold the information about the current
      number of UPs.
      Due to the change, needed to remove the lines that set the value of
      UP to be different than zero in the func "mlx4_en_select_queue",
      since now the num of TX queues that are allocated is only one per channel
      in default.
      In order not to force the UP to be zero in case of only one TC, added
      a condition before forcing it in the func "mlx4_en_fill_qp_context".
      
      Tested:
      After the module is loaded with minimum number of UP per channel, to
      increase num of TCs to 8, use:
      tc qdisc add dev ens8 root mqprio num_tc 8
      In order to decrease the number of TCs to minimum number of UP per channel,
      use:
      tc qdisc del dev ens8 root
      Signed-off-by: default avatarInbar Karmy <inbark@mellanox.com>
      Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
      Cc: Tarick Bedeir <tarick@google.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ec327f7a
    • Inbar Karmy's avatar
      net/mlx4_en: Add dynamic variable to hold the number of user priorities (UP) · f21ad614
      Inbar Karmy authored
      Until this patch, the number of UPs was hard coded for eight.
      Replace this with a variable in struct "mlx4_en_port_profile".
      Currently, the variable will hold the maximum number of UP,
      as before.
      The patch creates an infrastructure to add an option for dynamic
      change of the actual number of TCs.
      Signed-off-by: default avatarInbar Karmy <inbark@mellanox.com>
      Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
      Cc: Tarick Bedeir <tarick@google.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f21ad614
    • Arvind Yadav's avatar
      net: bridge: constify attribute_group structures. · cddbb79f
      Arvind Yadav authored
      attribute_groups are not supposed to change at runtime. All functions
      working with attribute_groups provided by <linux/sysfs.h> work with const
      attribute_group. So mark the non-const structs as const.
      
      File size before:
         text	   data	    bss	    dec	    hex	filename
         2645	    896	      0	   3541	    dd5	net/bridge/br_sysfs_br.o
      
      File size After adding 'const':
         text	   data	    bss	    dec	    hex	filename
         2701	    832	      0	   3533	    dcd	net/bridge/br_sysfs_br.o
      Signed-off-by: default avatarArvind Yadav <arvind.yadav.cs@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      cddbb79f
    • Arvind Yadav's avatar
      net: constify attribute_group structures. · 38ef00cc
      Arvind Yadav authored
      attribute_groups are not supposed to change at runtime. All functions
      working with attribute_groups provided by <linux/device.h> work with const
      attribute_group. So mark the non-const structs as const.
      
      File size before:
         text	   data	    bss	    dec	    hex	filename
         9968	   3168	     16	  13152	   3360	net/core/net-sysfs.o
      
      File size After adding 'const':
         text	   data	    bss	    dec	    hex	filename
        10160	   2976	     16	  13152	   3360	net/core/net-sysfs.o
      Signed-off-by: default avatarArvind Yadav <arvind.yadav.cs@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      38ef00cc
    • Arvind Yadav's avatar
      net: freescale: gianfar : constify dev_pm_ops structures. · ee27244b
      Arvind Yadav authored
      dev_pm_ops are not supposed to change at runtime. All functions
      working with dev_pm_ops provided by <linux/device.h> work with const
      dev_pm_ops. So mark the non-const structs as const.
      
      File size before:
         text	   data	    bss	    dec	    hex	filename
        19057	    392	      0	  19449	   4bf9	drivers/net/ethernet/freescale/gianfar.o
      
      File size After adding 'const':
         text	   data	    bss	    dec	    hex	filename
        19249	    192	      0	  19441	   4bf1	drivers/net/ethernet/freescale/gianfar.o
      Signed-off-by: default avatarArvind Yadav <arvind.yadav.cs@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ee27244b
    • Arvind Yadav's avatar
      net: smc91x: constify dev_pm_ops structures. · d19724ec
      Arvind Yadav authored
      dev_pm_ops are not supposed to change at runtime. All functions
      working with dev_pm_ops provided by <linux/device.h> work with const
      dev_pm_ops. So mark the non-const structs as const.
      
      File size before:
         text	   data	    bss	    dec	    hex	filename
        18709	    401	      0	  19110	   4aa6	drivers/net/ethernet/smsc/smc91x.o
      
      File size After adding 'const':
         text	   data	    bss	    dec	    hex	filename
        18901	    201	      0	  19102	   4a9e	drivers/net/ethernet/smsc/smc91x.o
      Signed-off-by: default avatarArvind Yadav <arvind.yadav.cs@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      d19724ec
    • Arvind Yadav's avatar
      net: ibm: ibmveth: constify dev_pm_ops structures. · eb60a73d
      Arvind Yadav authored
      dev_pm_ops are not supposed to change at runtime. All functions
      working with dev_pm_ops provided by <linux/device.h> work with const
      dev_pm_ops. So mark the non-const structs as const.
      
      File size before:
         text	   data	    bss	    dec	    hex	filename
        15426	   1256	      0	  16682	   412a	drivers/net/ethernet/ibm/ibmveth.o
      
      File size After adding 'const':
         text	   data	    bss	    dec	    hex	filename
        15618	   1064	      0	  16682	   412a	drivers/net/ethernet/ibm/ibmveth.o
      Signed-off-by: default avatarArvind Yadav <arvind.yadav.cs@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      eb60a73d
    • Thomas Falcon's avatar
      ibmvnic: Fix assignment of RX/TX IRQ's · 5df969c3
      Thomas Falcon authored
      The driver currently creates RX/TX queues during device probe, but
      assigns IRQ's to them during device open. On reset, however,
      IRQ's are assigned when resetting the queues. If there is a reset
      while the device is closed and the device is later opened, the driver will
      request IRQ's twice, causing the open to fail. This patch assigns
      the IRQ's in the ibmvnic_init function after the queues are reset or
      initialized, ensuring IRQ's are only requested once.
      Signed-off-by: default avatarThomas Falcon <tlfalcon@linux.vnet.ibm.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5df969c3
    • Donald Sharp's avatar
      net: ipmr: Add ipmr_rtm_getroute · 4f75ba69
      Donald Sharp authored
      Add to RTNL_FAMILY_IPMR, RTM_GETROUTE the ability
      to retrieve one S,G mroute from a specified table.
      
      *,G will return mroute information for just that
      particular mroute if it exists.  This is because
      it is entirely possible to have more S's then
      can fit in one skb to return to the requesting
      process.
      Signed-off-by: default avatarDonald Sharp <sharpd@cumulusnetworks.com>
      Signed-off-by: default avatarNikolay Aleksandrov <nikolay@cumulusnetworks.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      4f75ba69
    • Martin KaFai Lau's avatar
      bpf: Fix out-of-bound access on interpreters[] · 8007e40a
      Martin KaFai Lau authored
      The index is off-by-one when fp->aux->stack_depth
      has already been rounded up to 32.  In particular,
      if stack_depth is 512, the index will be 16.
      
      The fix is to round_up and then takes -1 instead of round_down.
      
      [   22.318680] ==================================================================
      [   22.319745] BUG: KASAN: global-out-of-bounds in bpf_prog_select_runtime+0x48a/0x670
      [   22.320737] Read of size 8 at addr ffffffff82aadae0 by task sockex3/1946
      [   22.321646]
      [   22.321858] CPU: 1 PID: 1946 Comm: sockex3 Tainted: G        W       4.12.0-rc6-01680-g2ee87db3 #22
      [   22.323061] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.9.3-1.el7.centos 04/01/2014
      [   22.324260] Call Trace:
      [   22.324612]  dump_stack+0x67/0x99
      [   22.325081]  print_address_description+0x1e8/0x290
      [   22.325734]  ? bpf_prog_select_runtime+0x48a/0x670
      [   22.326360]  kasan_report+0x265/0x350
      [   22.326860]  __asan_report_load8_noabort+0x19/0x20
      [   22.327484]  bpf_prog_select_runtime+0x48a/0x670
      [   22.328109]  bpf_prog_load+0x626/0xd40
      [   22.328637]  ? __bpf_prog_charge+0xc0/0xc0
      [   22.329222]  ? check_nnp_nosuid.isra.61+0x100/0x100
      [   22.329890]  ? __might_fault+0xf6/0x1b0
      [   22.330446]  ? lock_acquire+0x360/0x360
      [   22.331013]  SyS_bpf+0x67c/0x24d0
      [   22.331491]  ? trace_hardirqs_on+0xd/0x10
      [   22.332049]  ? __getnstimeofday64+0xaf/0x1c0
      [   22.332635]  ? bpf_prog_get+0x20/0x20
      [   22.333135]  ? __audit_syscall_entry+0x300/0x600
      [   22.333770]  ? syscall_trace_enter+0x540/0xdd0
      [   22.334339]  ? exit_to_usermode_loop+0xe0/0xe0
      [   22.334950]  ? do_syscall_64+0x48/0x410
      [   22.335446]  ? bpf_prog_get+0x20/0x20
      [   22.335954]  do_syscall_64+0x181/0x410
      [   22.336454]  entry_SYSCALL64_slow_path+0x25/0x25
      [   22.337121] RIP: 0033:0x7f263fe81f19
      [   22.337618] RSP: 002b:00007ffd9a3440c8 EFLAGS: 00000202 ORIG_RAX: 0000000000000141
      [   22.338619] RAX: ffffffffffffffda RBX: 0000000000aac5fb RCX: 00007f263fe81f19
      [   22.339600] RDX: 0000000000000030 RSI: 00007ffd9a3440d0 RDI: 0000000000000005
      [   22.340470] RBP: 0000000000a9a1e0 R08: 0000000000a9a1e0 R09: 0000009d00000001
      [   22.341430] R10: 0000000000000000 R11: 0000000000000202 R12: 0000000000010000
      [   22.342411] R13: 0000000000a9a023 R14: 0000000000000001 R15: 0000000000000003
      [   22.343369]
      [   22.343593] The buggy address belongs to the variable:
      [   22.344241]  interpreters+0x80/0x980
      [   22.344708]
      [   22.344908] Memory state around the buggy address:
      [   22.345556]  ffffffff82aad980: 00 00 00 04 fa fa fa fa 04 fa fa fa fa fa fa fa
      [   22.346449]  ffffffff82aada00: 00 00 00 00 00 fa fa fa fa fa fa fa 00 00 00 00
      [   22.347361] >ffffffff82aada80: 00 00 00 00 00 00 00 00 00 00 00 00 fa fa fa fa
      [   22.348301]                                                        ^
      [   22.349142]  ffffffff82aadb00: 00 01 fa fa fa fa fa fa 00 00 00 00 00 00 00 00
      [   22.350058]  ffffffff82aadb80: 00 00 07 fa fa fa fa fa 00 00 05 fa fa fa fa fa
      [   22.350984] ==================================================================
      
      Fixes: b870aa90 ("bpf: use different interpreter depending on required stack size")
      Signed-off-by: default avatarMartin KaFai Lau <kafai@fb.com>
      Acked-by: default avatarAlexei Starovoitov <ast@fb.com>
      Acked-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8007e40a
    • Colin Ian King's avatar
      amd-xgbe: fix spelling mistake: "avialable" -> "available" · beef8516
      Colin Ian King authored
      Trivial fix to spelling mistake in netdev_err message
      Signed-off-by: default avatarColin Ian King <colin.king@canonical.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      beef8516
    • David S. Miller's avatar
      Merge branch 'arcnet-features' · 8ac6e2a3
      David S. Miller authored
      Michael Grzeschik says:
      
      ====================
      arcnet: Collection of latest features
      
      Here we sum up the latest features to improve the arcnet framework. One
      patch is used to get feedback from the transfer queue about failed xfers
      by adding the err_skb message queue. Beside that we improve the
      backplane status that can be read by the PCI-based cards and offer that
      status via an extra sysfs attribute. In the last patch we add another
      card type PCIFB2.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8ac6e2a3
    • Michael Grzeschik's avatar
      arcnet: com20020-pci: add support for PCIFB2 card · a356ab1c
      Michael Grzeschik authored
      We add support for the PCIFB2 card from EAE.
      
      Beside other cards, this card has the backplane mode enabled by default.
      Signed-off-by: default avatarMichael Grzeschik <m.grzeschik@pengutronix.de>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      a356ab1c
    • Michael Grzeschik's avatar
      arcnet: com20020-pci: handle backplane mode depending on card type · 52ab12e4
      Michael Grzeschik authored
      We read the backplane mode of each subcard from bits 2 and 3 of the misc
      register.
      Signed-off-by: default avatarMichael Grzeschik <m.grzeschik@pengutronix.de>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      52ab12e4
    • Michael Grzeschik's avatar
      arcnet: com20020-pci: add attribute to readback backplane status · ede07a1f
      Michael Grzeschik authored
      We add the sysfs interface the read back the backplane
      status of the interface.
      Signed-off-by: default avatarMichael Grzeschik <m.grzeschik@pengutronix.de>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ede07a1f
    • Michael Grzeschik's avatar
      arcnet: add err_skb package for package status feedback · 05fcd31c
      Michael Grzeschik authored
      We need to track the status of our queued packages. This way the driving
      process knows if failed packages need to be retransmitted. For this
      purpose we queue the transferred/failed packages back into the err_skb
      message queue added with some status information.
      Signed-off-by: default avatarMichael Grzeschik <m.grzeschik@pengutronix.de>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      05fcd31c
    • David S. Miller's avatar
      Merge branch 'amd-xgbe-updates' · 65344ba9
      David S. Miller authored
      Tom Lendacky says:
      
      ====================
      amd-xgbe: AMD XGBE driver updates 2016-06-28
      
      The following updates and fixes are included in this driver update series:
      
      - Simplify mailbox interface code
      - Fix SFP supported and advertising settings
      - Fix PTP initialization register usage
      - Insure there is timestamp skb present before using it
      - Add a timeout to timestamp register updates
      - Handle return code from software reset function
      - Some fixes for handling 2.5Gbps rates
      - Limit I2C error messages
      - Fix non-DMA interrupt handling through tasklet usage
      - Add NUMA affinity support for memory allocations
      - Add NUMA affinity support for interrupts
      - Prepare for more fine-grained cache coherency controls
      - Simplify setting the DMA burst length programming
      - Performance improvements
      
      This patch series is based on net-next.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      65344ba9
    • Lendacky, Thomas's avatar
      amd-xgbe: Adjust register settings to improve performance · 6f595959
      Lendacky, Thomas authored
      Add support to change some general performance settings and to provide
      some performance settings based on the device that is probed.
      
      This includes:
      
      - Setting the maximum read/write outstanding request limit
      - Reducing the AXI interface burst length size
      - Selectively setting the Tx and Rx descriptor pre-fetch threshold
      - Selectively setting additional cache coherency controls
      
      Tested and verified on all versions of the hardware.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6f595959
    • Lendacky, Thomas's avatar
      amd-xgbe: Simplify the burst length settings · 7e1e6b86
      Lendacky, Thomas authored
      Currently the driver hardcodes the PBLx8 setting.  Remove the need for
      specifying the PBLx8 setting and automatically calculate based on the
      specified PBL value. Since the PBLx8 setting applies to both Tx and Rx
      use the same PBL value for both of them.
      
      Also, the driver currently uses a bit field to set the AXI master burst
      len setting. Change to the full bit field range and set the burst length
      based on the specified value.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      7e1e6b86
    • Lendacky, Thomas's avatar
      amd-xgbe: Prepare for more fine grained cache coherency controls · 9916716a
      Lendacky, Thomas authored
      In prep for setting fine grained read and write DMA cache coherency
      controls, allow specific values to be used to set the cache coherency
      registers.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9916716a
    • Lendacky, Thomas's avatar
      amd-xgbe: Add NUMA affinity support for IRQ hints · f00ba49d
      Lendacky, Thomas authored
      For IRQ affinity, set the affinity hints for the IRQs to be (initially) on
      the processors corresponding to the NUMA node of the device.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f00ba49d
    • Lendacky, Thomas's avatar
      amd-xgbe: Add NUMA affinity support for memory allocations · 18f9f0ac
      Lendacky, Thomas authored
      Add support to perform memory allocations on the node of the device. The
      original allocation or the ring structure and Tx/Rx queues allocated all
      of the memory at once and then carved it up for each channel and queue.
      To best ensure that we get as much memory from the NUMA node as we can,
      break the channel and ring allocations into individual allocations.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      18f9f0ac
    • Lendacky, Thomas's avatar
      amd-xgbe: Re-issue interrupt if interrupt status not cleared · 85b85c85
      Lendacky, Thomas authored
      Some of the device interrupts should function as level interrupts. For
      some hardware configurations this requires setting some control bits
      so that if the interrupt status has not been cleared the interrupt
      should be reissued.
      
      Additionally, when using MSI or MSI-X interrupts, run the interrupt
      service routine as a tasklet so that the re-issuance of the interrupt
      is handled properly.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      85b85c85
    • Lendacky, Thomas's avatar
      amd-xgbe: Limit the I2C error messages that are output · 45a2005e
      Lendacky, Thomas authored
      When I2C communication fails, it tends to always fail. Rather than
      continuously issue an error message (once per second in most cases),
      change the message to be issued just once.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      45a2005e
    • Lendacky, Thomas's avatar
      amd-xgbe: Fixes for working with PHYs that support 2.5GbE · ed3333fa
      Lendacky, Thomas authored
      The driver has some missing functionality when operating in the mode that
      supports 2.5GbE.  Fix the driver to fully recognize and support this speed.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ed3333fa
    • Lendacky, Thomas's avatar
      amd-xgbe: Handle return code from software reset function · 42d452dc
      Lendacky, Thomas authored
      Currently the function that performs a software reset of the hardware
      provides a return code.  During driver probe check this return code and
      exit with an error if the software reset fails.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      42d452dc
    • Lendacky, Thomas's avatar
      amd-xgbe: Prevent looping forever if timestamp update fails · 9018ff53
      Lendacky, Thomas authored
      Just to be on the safe side, should the update of the timestamp registers
      not complete, issue a warning rather than looping forever waiting for the
      update to complete.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9018ff53
    • Lendacky, Thomas's avatar
      amd-xgbe: Add a check for an skb in the timestamp path · 93845d5f
      Lendacky, Thomas authored
      Spurious Tx timestamp interrupts can cause an oops in the Tx timestamp
      processing function if a Tx timestamp skb is NULL. Add a check to insure
      a Tx timestamp skb is present before attempting to use it.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      93845d5f
    • Lendacky, Thomas's avatar
      amd-xgbe: Use the proper register during PTP initialization · 3abc7cff
      Lendacky, Thomas authored
      During PTP initialization, the Timestamp Control register should be
      cleared and not the Tx Configuration register.  While this typo causes
      the wrong register to be cleared, the default value of each register and
      and the fact that the Tx Configuration register is programmed afterwards
      doesn't result in a bug, hence only fixing in net-next.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      3abc7cff
    • Lendacky, Thomas's avatar
      amd-xgbe: Fix SFP PHY supported/advertised settings · 56503d55
      Lendacky, Thomas authored
      When using SFPs, the supported and advertised settings should be initially
      based on the SFP that has been detected.  The code currently indicates the
      overall support of the device as opposed to what the SFP is capable of.
      Update the code to change the supported link modes, auto-negotiation, etc.
      to be based on the installed SFP.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      56503d55
    • Lendacky, Thomas's avatar
      amd-xgbe: Simplify mailbox interface rate change code · 549b32af
      Lendacky, Thomas authored
      Simplify and centralize the mailbox command rate change interface by
      having a single function perform the writes to the mailbox registers
      to issue the request.
      Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      549b32af
    • David S. Miller's avatar
      Merge branch 'bpf-Add-syscall-lookup-support-for-fd-array-and-htab' · e3ef6983
      David S. Miller authored
      Martin KaFai Lau says:
      
      ====================
      bpf: Add syscall lookup support for fd array and htab
      
      This patchset adds BPF_MAP_LOOKUP_ELEM syscall support for
      BPF_MAP_TYPE_PROG_ARRAY,
      BPF_MAP_TYPE_ARRAY_OF_MAPS and
      BPF_MAP_TYPE_HASH_OF_MAPS
      ====================
      Reviewed-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e3ef6983
    • Martin KaFai Lau's avatar
      bpf: Add test for syscall on fd array/htab lookup · a8744f25
      Martin KaFai Lau authored
      Checks are added to the existing sockex3 and test_map_in_map test.
      Signed-off-by: default avatarMartin KaFai Lau <kafai@fb.com>
      Acked-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      a8744f25
    • Martin KaFai Lau's avatar
      bpf: Add syscall lookup support for fd array and htab · 14dc6f04
      Martin KaFai Lau authored
      This patch allows userspace to do BPF_MAP_LOOKUP_ELEM on
      BPF_MAP_TYPE_PROG_ARRAY,
      BPF_MAP_TYPE_ARRAY_OF_MAPS and
      BPF_MAP_TYPE_HASH_OF_MAPS.
      
      The lookup returns a prog-id or map-id to the userspace.
      The userspace can then use the BPF_PROG_GET_FD_BY_ID
      or BPF_MAP_GET_FD_BY_ID to get a fd.
      Signed-off-by: default avatarMartin KaFai Lau <kafai@fb.com>
      Acked-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      14dc6f04
    • Thor Thayer's avatar
      net: stmmac: Add additional registers for dwmac1000_dma ethtool · 77b0d361
      Thor Thayer authored
      Version 3.70a of the Designware has additional DMA registers so
      add those to the ethtool DMA Register dump.
      Offset 9  - Receive Interrupt Watchdog Timer Register
      Offset 10 - AXI Bus Mode Register
      Offset 11 - AHB or AXI Status Register
      Offset 22 - HW Feature Register
      Signed-off-by: default avatarThor Thayer <thor.thayer@linux.intel.com>
      Acked-by: default avatarGiuseppe Cavallaro <peppe.cavallaro@st.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      77b0d361
    • David S. Miller's avatar
      Merge tag 'mlx5-updates-2017-06-27' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux · 5185ad61
      David S. Miller authored
      Saeed Mahameed says:
      
      ====================
      mlx5-updates-2017-06-27 (Innova IPsec offload support)
      
      This patchset adds support for Innova IPSec network interface card.
      
      About Innova device:
      --------------------
      Innova is a network card with a ConnectX chip and an FPGA chip as a
       bump-on-the-wire.
      
                     Internal
      +----------+   Link       +-----------------+
      |          +--------------+      FPGA       |  +------+
      | ConnectX |              |  Shell          +--+ QSFP |
      |          +--------------+    +-------+    |  | Port |
      +----------+      I2C     |    |  SBU  |    |  +------+
                                |    +-------+    |
                                +--+----------+---+
                                   |          |
                                +--+--+   +---+---+
                                | DDR |   | Flash |
                                +-----+   +-------+
      
      The FPGA synthesized logic is loaded from dedicated flash storage and has
       access to its own dedicated DDR RAM.
      The ConnectX chip firmware programs the FPGA by accessing its configuration
      space over either the slow internal I2C link or the high-speed internal link.
      
      The FPGA logic is divided into a "Shell" and a "Sandbox Unit" (SBU).
      mlx5_core driver (with CONFIG_MLX5_FPGA) handles all shell functionality,
      while other components may handle the various SBU functionalities.
      
      The driver opens high-speed reliable communication channels with the shell and
      the SBU over the internal link.
      These channels may be used for high-bandwidth configuration or for SBU-specific
      out-of-band data paths.
      
      About Innova IPSec device:
      --------------------------
      Innova IPSec is a network card that allows offloading IPSec cryptography operations
      from the host CPU to the NIC. It is an Innova card with an IPSec SBU.
      The hardware keeps the database of IPSec Security Associations (SADB) in the FPGA's
      DDR memory.
      
                     Internal
      +----------+   Link       +-----------------+
      |          +--------------+      FPGA       |  +------+
      | ConnectX |              |  Shell          +--+ QSFP |
      |          +--------------+    +-------+    |  | Port |
      +----------+ Internal I2C |    | IPSec |    |  +------+
                                |    |  SBU  |    |
                                |    +-------+    |
                                +--+----------+---+
                                   |          |
                                +--+--+   +---+---+
                                | DDR |   |       |
                                |     |   | Flash |
                                |SADB |   |       |
                                +-----+   +-------+
      
      Modes and ciphers:
      Currently the following modes and ciphers are supported:
      IPv4 and IPv6
      ESP tunnel and transport modes
      AES 128 and 256 bit encryption, with GCM authentication (RFC4106)
      
      IV is generated using seqiv, in sync with Linux's geniv.
      
      More modes and ciphers may be added later.
      
      Notes:
      In the future similar functionality will be included in a single-chip NIC.
      
      About the driver:
      -----------------
      Patches 1-4 prepare some existing driver code for the new feature:
        * Add support for reserved GIDs in the hardware GID table
        * Allow multiple modules to enable hardware RoCE support independently
      Patches 5-6 define structs and helper functions for QP work-queues.
      Patches 7-11 add various FPGA-related features required for Innova.
      IPSec.
      Patch 12 adds abstraction layer for Mellanox IPSec-offload capable devices.
      atches 13-16 add IPSec offload support to the mlx5 netdevice.
      
      This driver services the new IPSec offload API introduced in commit
      d77e38e6 ("xfrm: Add an IPsec hardware offloading API")
      
      Configuration Path:
      If Innova IPSec device is detected, the mlx5e netdevice gets the new
      NETIF_F_HW_ESP feature and the xdo callbacks, indicating ESP offload
      capabilities, and also the matching TX checksum and GSO features.
      
      The driver configures offloaded Security Associations (SAs) by sending
      an ADD_SA or DEL_SA message to the IPSec SBU, which updates the SADB in DDR.
      These messages and their responses are sent over a high-speed channel.
      Counters for ethtool are retrieved by the driver from the SBU.
      
      Data path:
      On receive path, the SBU decrypts ESP packets which match the offloaded SADB,
      but keeps them encapsulated.
      The SBU injects metadata (Mellanox owned ethertype) indicating that crypto-offload
      has taken place, the SA with which it was done, and the authentication result.
      
      The ConnectX chip performs RX checksum offload on the packet, and RSS using the
      ESP SPI value.  The driver detects the special ethertype, and attaches a struct
      secpath to the RX SKB, including flags to indicate that crypto offload took place,
      the authentication result, and which xfrm_state was used for decryption, in the
      olen and ovec members. The RX SKB may have useful CHECKSUM_COMPLETE. A separate
      patchset will add support for that in the xfrm stack.
      
      On transmit path, the stack encapsulates the packet but does not encrypt it, and
      indicates in the SKB's secpath that crypto offload is to be performed and the SA
      to use to do so.
      The driver avoids performing crypto-offload for ESP fragments, and packets with
      IP options, as the SBU cannot currently do that.  For eligible packets, the driver
      prepends a special ethertype with metadata instructing the hardware to perform crypto offload.
      The stack builds regular (non-GSO) SKBs so that they contain a placeholder for the ESP trailer.
      The driver trims it off, because the SBU automatically appends the trailer for offloaded packets.
      The ConnectX chip performs TX checksum offload on inner UDP or TCP packets,
      and GSO for TCP packets (duplicating the prepended metadata).
      The segmented packets then undergo encryption in the SBU before going on the wire.
      
      Performance:
      We measure single stream of TCP on Intel(R) Xeon(R) CPU E5-2643 v2 @3.50GHz
      Using AES-NI with ESP GSO we get constant 4.1 Gbps.
      Using crypto offload we get constant 18 Gbps.
      
      Note that these numbers require CHECKSUM_COMPLETE support in XFRM, which we submit separately.
      
      -  Ilan Tayari
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5185ad61
    • David S. Miller's avatar
      Merge branch 'net-fix-sw-timestamping' · 869684a7
      David S. Miller authored
      Ivan Khoronzhuk says:
      
      ====================
      net: fix sw timestamping for non PTP packets
      
      This series contains several corrections connected with timestamping
      for cpsw and netcp drivers based on same cpts module.
      
      Based on net/next
      ====================
      Reviewed-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      869684a7
    • Ivan Khoronzhuk's avatar
      net: ethernet: ti: netcp_ethss: use cpts to check if packet needs timestamping · 0ccf59ba
      Ivan Khoronzhuk authored
      There is cpts function to check if packet can be timstamped with cpts.
      Seems that ptp_classify_raw cover all cases listed with "case".
      Signed-off-by: default avatarIvan Khoronzhuk <ivan.khoronzhuk@linaro.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      0ccf59ba
    • Ivan Khoronzhuk's avatar
      net: ethernet: ti: cpsw: fix sw timestamping for non PTP packets · f44f8417
      Ivan Khoronzhuk authored
      The cpts can timestmap only ptp packets at this moment, so driver
      cannot mark every packet as though it's going to be timestamped,
      only because h/w timestamping for given skb is enabled with
      SKBTX_HW_TSTAMP. It doesn't allow to use sw timestamping, as result
      outgoing packet is not timestamped at all if it's not PTP and h/w
      timestamping is enabled. So, fix it by setting SKBTX_IN_PROGRESS
      only for PTP packets.
      Signed-off-by: default avatarIvan Khoronzhuk <ivan.khoronzhuk@linaro.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f44f8417