1. 05 May, 2020 26 commits
  2. 04 May, 2020 14 commits
    • David S. Miller's avatar
      Merge branch 'net-reduce-dynamic-lockdep-keys' · 354d8614
      David S. Miller authored
      Cong Wang says:
      
      ====================
      net: reduce dynamic lockdep keys
      
      syzbot has been complaining about low MAX_LOCKDEP_KEYS for a
      long time, it is mostly because we register 4 dynamic keys per
      network device.
      
      This patchset reduces the number of dynamic lockdep keys from
      4 to 1 per netdev, by reverting to the previous static keys,
      except for addr_list_lock which still has to be dynamic.
      The second patch removes a bonding-specific key by the way.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      354d8614
    • Cong Wang's avatar
      bonding: remove useless stats_lock_key · e7511f56
      Cong Wang authored
      After commit b3e80d44
      ("bonding: fix lockdep warning in bond_get_stats()") the dynamic
      key is no longer necessary, as we compute nest level at run-time.
      So, we can just remove it to save some lockdep key entries.
      
      Test commands:
       ip link add bond0 type bond
       ip link add bond1 type bond
       ip link set bond0 master bond1
       ip link set bond0 nomaster
       ip link set bond1 master bond0
      
      Reported-and-tested-by: syzbot+aaa6fa4949cc5d9b7b25@syzkaller.appspotmail.com
      Cc: Dmitry Vyukov <dvyukov@google.com>
      Acked-by: default avatarTaehee Yoo <ap420073@gmail.com>
      Signed-off-by: default avatarCong Wang <xiyou.wangcong@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      e7511f56
    • Cong Wang's avatar
      net: partially revert dynamic lockdep key changes · 1a33e10e
      Cong Wang authored
      This patch reverts the folowing commits:
      
      commit 064ff66e
      "bonding: add missing netdev_update_lockdep_key()"
      
      commit 53d37497
      "net: avoid updating qdisc_xmit_lock_key in netdev_update_lockdep_key()"
      
      commit 1f26c0d3
      "net: fix kernel-doc warning in <linux/netdevice.h>"
      
      commit ab92d68f
      "net: core: add generic lockdep keys"
      
      but keeps the addr_list_lock_key because we still lock
      addr_list_lock nestedly on stack devices, unlikely xmit_lock
      this is safe because we don't take addr_list_lock on any fast
      path.
      
      Reported-and-tested-by: syzbot+aaa6fa4949cc5d9b7b25@syzkaller.appspotmail.com
      Cc: Dmitry Vyukov <dvyukov@google.com>
      Cc: Taehee Yoo <ap420073@gmail.com>
      Signed-off-by: default avatarCong Wang <xiyou.wangcong@gmail.com>
      Acked-by: default avatarTaehee Yoo <ap420073@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      1a33e10e
    • David S. Miller's avatar
      Merge branch 'net-ethernet-ti-k3-introduce-common-platform-time-sync-driver-cpts' · ea84c842
      David S. Miller authored
      Grygorii Strashko says:
      
      ====================
      net: ethernet: ti: k3: introduce common platform time sync driver - cpts
      
      This series introduced support for significantly upgraded TI A65x/J721E Common
      platform time sync (CPTS) modules which are part of AM65xx Time Synchronization
      Architecture [1].
      The TI A65x/J721E now contain more than one CPTS instance:
      - MCU CPSW CPTS (IEEE 1588 compliant)
      - Main NAVSS CPTS (central)
      - PCIe CPTS(s) (PTM  compliant)
      - J721E: Main CPSW9g CPTS (IEEE 1588 compliant)
      which can work as separately as interact to each other through Time Sync Router
      (TSR) and Compare Event Router (CER). In addition there are also ICSS-G IEP
      blocks which can perform similar timsync functions, but require FW support.
      More info also available in TRM [2][3]. Not all above modules are available
      to the Linux by as of now as some of them are reserved for RTOS/FW purposes.
      
      The scope of this submission is TI A65x/J721E CPSW CPTS and Main NAVSS CPTS,
      and TSR was used for testing purposes.
                                                                             +---------------------------+
                                                                             | MCU CPSW                  |
      +-------------------+           +------------------------+             |                TS         |
      | Main Navss CPTS   |           | Time Sync Router (TSR) |             |          +-------------+  |
      |                   |           |                        |             |          |             |  |
      |            HW1_TS +<----------+                        |             | +--------v-----+    +--+--+
      |                   |           |                        |             | |        CPTS  |    |Port |
      |              ...  |           |                        |           X+-->HW1_TS        |    |     |
      |            HW8_TS <------------<---------+             |           X|-->HW2_TS        |    +--^--+
      |                   |           |          |             +--------------->HW3_TS        |       |  |
      |                   |           |          |             +--------------->HW4_TS        |       |  |
      |                   |           |          |             |             | |              |       |  |
      |                   |           |          |             |             | |              |       |  |
      |            Genf0  +----------->          (A)---------+ +<--------------+Genf0         |       |  |
      |                   |           |          |             |             | |              |       |  |
      |              ...  |           |          +-----------> <---------------+Genf1     ESTf+-------+  |
      |                   |           |                        |             | |              |          |
      |                   |           |                        |             | +--------------+          |
      |            Genf8  +---------->+                        |             |                           |
      |                   |           |    SYNC0 ...    SYNC3  |             |                           |
      +-------------------+           +------+------------+----+             +---------------------------+
                                             +            +
                                             X            X
      (A) shows possible routing path for MCU CPSW CPTS Genf0 signal as an example.
      
      Main features of the new TI A65x/J721E CPTS modules are:
      - 64-bit timestamp/counter mode support in ns by using add_val
      - implemented in HW PPM and nudge adjustment.
      - control of time sync events via interrupt or polling
      - selection of multiple external reference clock sources
      - hardware timestamp of ext. inputs events (HWx_TS_PUSH)
      - periodic generator function outputs (TS_GENFx)
      - (CPSW only) Ethernet Enhanced Scheduled Traffic Operations (CPTS_ESTFn),
        which drives TSN schedule
      - timestamping of all RX packets bypassing CPTS FIFO
      
      Patch 1 - DT bindings
      Patch 2 - the AM65x/J721E driver
      Patch 3 - enables packet timestamping support in TI AM65x/J721E MCU CPSW driver.
      Patches 4-7 - DT updates.
      
      === PTP Testing:
      
      phc2sys -s CLOCK_REALTIME -c eth0 -m -O 0 -u30
      phc2sys[627.331]: eth0 rms 409912446712787392 max 1587584079521858304 freq  -6665 +/- 35040 delay   832 +/-  27
      phc2sys[657.335]: eth0 rms   33 max   66 freq     -0 +/-  28 delay   820 +/-  30
      phc2sys[687.339]: eth0 rms   37 max   70 freq     -1 +/-  32 delay   830 +/-  29
      phc2sys[717.343]: eth0 rms   33 max   71 freq     -0 +/-  29 delay   828 +/-  23
      phc2sys[747.346]: eth0 rms   35 max   75 freq     -0 +/-  31 delay   829 +/-  26
      phc2sys[777.350]: eth0 rms   37 max   68 freq     -1 +/-  32 delay   825 +/-  25
      phc2sys[807.354]: eth0 rms   28 max   57 freq     -1 +/-  25 delay   824 +/-  21
      phc2sys[837.358]: eth0 rms   43 max   81 freq     -1 +/-  37 delay   836 +/-  23
      phc2sys[867.361]: eth0 rms   33 max   74 freq     +0 +/-  29 delay   828 +/-  24
      phc2sys[897.365]: eth0 rms   35 max   77 freq     -2 +/-  30 delay   824 +/-  25
      phc2sys[927.369]: eth0 rms   28 max   50 freq     +0 +/-  25 delay   825 +/-  25
      
      ptp4l -P -2 -H -i eth0 -l 6 -m -q -p /dev/ptp1 -f ptp.cfg -s
      ptp4l[22095.754]: port 1: MASTER to UNCALIBRATED on RS_SLAVE
      ptp4l[22097.754]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
      ptp4l[22159.757]: rms  317 max 1418 freq    +79 +/- 186 delay   410 +/-   1
      ptp4l[22223.760]: rms    9 max   24 freq    +42 +/-  12 delay   409 +/-   1
      ptp4l[22287.763]: rms   10 max   28 freq    +41 +/-  11 delay   410 +/-   1
      ptp4l[22351.767]: rms   10 max   26 freq    +34 +/-  12 delay   410 +/-   1
      ptp4l[22415.770]: rms   10 max   26 freq    +49 +/-  14 delay   410 +/-   1
      
      === Ext. HW_TS and Genf testing:
      
      For testing purposes Time Sync Router (TSR) can be modeled in DT as pin controller
      +       timesync_router: timesync_router@A40000 {
      +               compatible = "pinctrl-single";
      +               reg = <0x0 0xA40000 0x0 0x800>;
      +               #address-cells = <1>;
      +               #size-cells = <0>;
      +               #pinctrl-cells = <1>;
      +               pinctrl-single,register-width = <32>;
      +               pinctrl-single,function-mask = <0x800007ff>;
      +       };
      
      then signals routing can be done in board file, for example:
      +#define TS_OFFSET(pa, val)     (0x4+(pa)*4) (0x80000000 | val)
      +
      +&timesync_router {
      +       pinctrl-names = "default";
      +       pinctrl-0 = <&mcu_cpts>;
      +
      +       /* Example of the timesync routing */
      +       mcu_cpts: mcu_cpts {
      +               pinctrl-single,pins = <
      +                       /* [cpts genf1] in13 -> out25 [cpts hw4_push] */
      +                       TS_OFFSET(25, 13)
      +                       /* [cpts genf1] in13 -> out0 [main cpts hw1_push] */
      +                       TS_OFFSET(0, 13)
      +                       /* [main cpts genf0] in4 -> out1 [main cpts hw2_push] */
      +                       TS_OFFSET(1, 4)
      +                       /* [main cpts genf0] in4 -> out24 [cpts hw3_push] */
      +                       TS_OFFSET(24, 4)
      +               >;
      +       };
      +};
      
      will create link:
          cpsw cpts Genf1 -> main cpts hw1_push
                          -> cpsw cpts hw4_push
      
          main cpts Genf0 -> main cpts hw2_push
                          -> cpsw cpts hw3_push
      
       testptp -d /dev/ptp0 -i 0 -p 1000000000
       periodic output request okay
       testptp -d /dev/ptp0 -i 1 -e 5
       external time stamp request okay
       event index 1 at 22583.000000025
       event index 1 at 22584.000000025
       event index 1 at 22585.000000025
       event index 1 at 22586.000000025
       event index 1 at 22587.000000025
       testptp -d /dev/ptp1 -i 2 -e 5
       external time stamp request okay
       event index 2 at 1587606764.249304554
       event index 2 at 1587606765.249304467
       event index 2 at 1587606766.249304380
       event index 2 at 1587606767.249304293
       event index 2 at 1587606768.249304206
      
      [1] https://www.ti.com/lit/pdf/spracp7
      [2] https://www.ti.com/lit/pdf/sprz452
      [3] https://www.ti.com/lit/pdf/spruil1
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ea84c842
    • Grygorii Strashko's avatar
      arm64: dts: ti: j721e-main: add main navss cpts node · 461d6d05
      Grygorii Strashko authored
      Add DT node for Main NAVSS CPTS module.
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      461d6d05
    • Grygorii Strashko's avatar
      arm64: dts: ti: k3-j721e-mcu: add mcu cpsw cpts node · 29390928
      Grygorii Strashko authored
      Add DT node for The TI J721E MCU CPSW CPTS which is part of MCU CPSW NUSS.
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      29390928
    • Grygorii Strashko's avatar
      arm64: dts: ti: k3-am65-main: add main navss cpts node · b3f7e95f
      Grygorii Strashko authored
      Add DT node for Main NAVSS CPTS module.
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b3f7e95f
    • Grygorii Strashko's avatar
      arm64: dts: ti: k3-am65-mcu: add cpsw cpts node · 885a26ba
      Grygorii Strashko authored
      Add DT node for the TI AM65x SoC Common Platform Time Sync (CPTS).
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      885a26ba
    • Grygorii Strashko's avatar
      net: ethernet: ti: am65-cpsw-nuss: enable packet timestamping support · b1f66a5b
      Grygorii Strashko authored
      The MCU CPSW Common Platform Time Sync (CPTS) provides possibility to
      timestamp TX PTP packets and all RX packets.
      
      This enables corresponding support in TI AM65x/J721E MCU CPSW driver.
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b1f66a5b
    • Grygorii Strashko's avatar
      net: ethernet: ti: introduce am654 common platform time sync driver · f6bd5952
      Grygorii Strashko authored
      The CPTS module is used to facilitate host control of time sync operations.
      Main features of CPTS module are:
      - selection of multiple external clock sources
      - control of time sync events via interrupt or polling
      - 64-bit timestamp mode in ns with HW PPM and nudge adjustment.
      - hardware timestamp ext. inputs (HWx_TS_PUSH)
      - timestamp Generator function outputs (TS_GENFx)
      Depending on integration it enables compliance with the IEEE 1588-2008
      standard for a precision clock synchronization protocol, Ethernet Enhanced
      Scheduled Traffic Operations (CPTS_ESTFn) and PCIe Subsystem Precision Time
      Measurement (PTM).
      
      Introduced driver provides Linux PTP hardware clock for each CPTS device
      and network packets timestamping where applicable. CPTS PTP hardware clock
      supports following operations:
          - Set time
          - Get time
          - Shift the clock by a given offset atomically
          - Adjust clock frequency
          - Time stamp external events
          - Periodic output signals
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f6bd5952
    • Grygorii Strashko's avatar
      dt-binding: ti: am65x: document common platform time sync cpts module · 6e87ac74
      Grygorii Strashko authored
      Document device tree bindings for TI AM654/J721E SoC The Common Platform
      Time Sync (CPTS) module. The CPTS module is used to facilitate host control
      of time sync operations. Main features of CPTS module are:
        - selection of multiple external clock sources
        - 64-bit timestamp mode in ns with ppm and nudge adjustment.
        - control of time sync events via interrupt or polling
        - hardware timestamp of ext. events (HWx_TS_PUSH)
        - periodic generator function outputs (TS_GENFx)
        - PPS in combination with timesync router
        - Depending on integration it enables compliance with the IEEE 1588-2008
      standard for a precision clock synchronization protocol, Ethernet Enhanced
      Scheduled Traffic Operations (CPTS_ESTFn) and PCIe Subsystem Precision Time
      Measurement (PTM).
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6e87ac74
    • David S. Miller's avatar
      Merge branch 'devlink-kernel-region-snapshot-id-allocation' · 1248dc00
      David S. Miller authored
      Jakub Kicinski says:
      
      ====================
      devlink: kernel region snapshot id allocation
      
      currently users have to find a free snapshot id to pass
      to the kernel when they are requesting a snapshot to be
      taken.
      
      This set extends the kernel so it can allocate the id
      on its own and send it back to user space in a response.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      1248dc00
    • Jakub Kicinski's avatar
      docs: devlink: clarify the scope of snapshot id · aebbd7df
      Jakub Kicinski authored
      In past discussions Jiri explained snapshot ids are cross-region.
      Explain this in the docs.
      
      v3: new patch
      Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      Reviewed-by: default avatarJiri Pirko <jiri@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      aebbd7df
    • Jakub Kicinski's avatar
      devlink: let kernel allocate region snapshot id · 043b3e22
      Jakub Kicinski authored
      Currently users have to choose a free snapshot id before
      calling DEVLINK_CMD_REGION_NEW. This is potentially racy
      and inconvenient.
      
      Make the DEVLINK_ATTR_REGION_SNAPSHOT_ID optional and try
      to allocate id automatically. Send a message back to the
      caller with the snapshot info.
      
      Example use:
      $ devlink region new netdevsim/netdevsim1/dummy
      netdevsim/netdevsim1/dummy: snapshot 1
      
      $ id=$(devlink -j region new netdevsim/netdevsim1/dummy | \
             jq '.[][][][]')
      $ devlink region dump netdevsim/netdevsim1/dummy snapshot $id
      [...]
      $ devlink region del netdevsim/netdevsim1/dummy snapshot $id
      
      v4:
       - inline the notification code
      v3:
       - send the notification only once snapshot creation completed.
      v2:
       - don't wrap the line containing extack;
       - add a few sentences to the docs.
      Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      Reviewed-by: default avatarJacob Keller <jacob.e.keller@intel.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      043b3e22