OrsPa10W

OrsPa10W/OrsPa10W.PrjPcbStructure

+Record=TopLevelDocument|FileName=OrsPa10W_Top.SchDoc
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsPa10W_Top.SchDoc|Designator= |SchDesignator= |FileName=OrsPa10W_PA.SchDoc|SymbolType=Normal|RawFileName=OrsPa10W_PA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsPa10W_Top.SchDoc|Designator= |SchDesignator= |FileName=OrsPa10W_Supply2.SchDoc|SymbolType=Normal|RawFileName=OrsPa10W_Supply2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsPa10W_Top.SchDoc|Designator= |SchDesignator= |FileName=OrsPa10W_Supply1.SchDoc|SymbolType=Normal|RawFileName=OrsPa10W_Supply1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsPa10W_PA.SchDoc|Designator=VC|SchDesignator=VC|FileName=OrsPa10W_CmdVGS.SchDoc|SymbolType=Normal|RawFileName=OrsPa10W_CmdVGS.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsPa10W_PA.SchDoc|Designator=VD|SchDesignator=VD|FileName=OrsPa10W_CmdVGS.SchDoc|SymbolType=Normal|RawFileName=OrsPa10W_CmdVGS.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 
+Record=SheetSymbol|Record=SheetSymbol|SourceDocument=OrsPa10W_PA.SchDoc|Designator=VP|SchDesignator=VP|FileName=OrsPa10W_CmdVGS.SchDoc|SymbolType=Normal|RawFileName=OrsPa10W_CmdVGS.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 

OrsPa10W/Project Outputs for OrsPa10W/Design Rule Check - OrsPa10W.drc

+Protel Design System Design Rule Check
+PCB File : Z:\RfPowerBoard\RfPowerBoard\hard\OrsPa10W.PcbDoc
+Date     : 8/3/2023
+Time     : 12:10:26 PM
+
+Processing Rule : Clearance Constraint (Gap=0.35mm) (InNamedPolygon('GND_L3')OR  InNamedPolygon('L4-+12V')),(All)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.35mm) (InNet('48/40V')),(All)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.5mm) (InNamedPolygon('L5_NoNet') OR InNamedPolygon('L6_NoNet') OR InNamedPolygon('L4_NoNet') OR InNamedPolygon('L7_NoNet')OR InNamedPolygon('L3_NoNet')),(All)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.2mm) (InNamedPolygon('L4-+12V-2')OR  InNamedPolygon('L4-+12V')OR InNamedPolygon('BOTTOM+12V')OR InNamedPolygon('BOTTOM+12V-1')OR InNamedPolygon('L6_NoNet2') OR InNamedPolygon('L6_NoNet')),(All)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.165mm) (InNetClass('50OhmsToptoL2')),(InPolygon)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.225mm) (InNetClass('50OhmsToptoL3')),(All)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.12mm) (All),(IsVia)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.21mm) (InPolygon),(All)
+Rule Violations :0
+
+Processing Rule : Clearance Constraint (Gap=0.1mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.254mm) (All)
+Rule Violations :0
+
+Processing Rule : Matched Net Lengths(Tolerance=0.3mm) (InNetClass('POENetClass1'))
+Rule Violations :0
+
+Processing Rule : Matched Net Lengths(Tolerance=0.5mm) (InNetClass('POENetClass2'))
+Rule Violations :0
+
+Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
+Rule Violations :0
+
+Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
+Rule Violations :0
+
+Processing Rule : Un-Routed Net Constraint ( (All) )
+Rule Violations :0
+
+Processing Rule : Hole Size Constraint (Min=0.02mm) (Max=3.5mm) (All)
+Rule Violations :0
+
+Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
+Rule Violations :0
+
+Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Minimum Solder Mask Sliver (Gap=0.05mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Silk To Solder Mask (Clearance=0.2mm) (Disabled)(IsPad),(All)
+Rule Violations :0
+
+Processing Rule : Silk to Silk (Clearance=0.2mm) (Disabled)(All),(All)
+Rule Violations :0
+
+Processing Rule : Net Antennae (Tolerance=0mm) (Disabled)(All)
+Rule Violations :0
+
+Processing Rule : Silk primitive without silk layer
+Rule Violations :0
+
+Processing Rule : Rule
+Rule Violations :0
+
+
+Violations Detected : 0
+Time Elapsed        : 00:00:01
\ No newline at end of file

OrsPa10W/Project Outputs for OrsPa10W/Gerber/Gerber Files.EXTREP

+------------------------------------------------------------------------------------------
+Gerber File Extension Report For: Gerber Files.GBR   8/3/2023  11:48:09 AM
+------------------------------------------------------------------------------------------
+
+
+------------------------------------------------------------------------------------------
+Layer Extension     Layer Description                      
+------------------------------------------------------------------------------------------
+.GTL                Top Layer                               
+.G1                 Signal Layer 2                          
+.G2                 Signal Layer 3                          
+.GBL                Bottom Layer                            
+.GTO                Top Overlay                             
+.GTP                Top Paste                               
+.GTS                Top Solder                              
+.GM1                Mechanical 1                            
+.GM3                Mechanical 3                            
+.GM13               Dimension                               
+------------------------------------------------------------------------------------------