software/ors-amarisoft: Add high UL TDD config

Follow https://tech-academy.amarisoft.com/NR_TDD_Pattern.html#Test_4

software/ors-amarisoft/buildout.hash.cfg

@@ -112,7 +112,7 @@ md5sum = 3b901e8733e6afff8940c6c318da4493
 
 [enb.jinja2.cfg]
 filename = config/enb.jinja2.cfg
-md5sum = e1c40827e30d6ddcd98be35ec8569af2
+md5sum = 1b8dc68206485299c08ab0e1544773f6
 
 [drb_lte.jinja2.cfg]
 filename = config/drb_lte.jinja2.cfg

software/ors-amarisoft/cell/nr/input-schema.json

@@ -24,7 +24,8 @@
       "enum": [
         "5ms 2UL 7DL 4/6 (default)",
         "2.5ms 1UL 3DL 2/10",
-        "5ms 8UL 1DL 2/10 (maximum uplink)"
+        "5ms 8UL 1DL 2/10 (EXPERIMENTAL maximum uplink)",
+        "5ms 6UL 3DL 10/2 (high uplink)"
       ],
       "default": "5ms 2UL 7DL 4/6 (default)",
       "options": {

software/ors-amarisoft/config/enb.jinja2.cfg

@@ -537,9 +537,10 @@
 
 {%-     set tdd = (cell.rf_mode == 'tdd') %}
 {%-     set tdd_config =
-            {'5ms 2UL 7DL 4/6 (default)':         1,
-             '2.5ms 1UL 3DL 2/10':                2,
-             '5ms 8UL 1DL 2/10 (maximum uplink)': 3}
+            {'5ms 2UL 7DL 4/6 (default)':                      1,
+             '2.5ms 1UL 3DL 2/10':                             2,
+             '5ms 8UL 1DL 2/10 (EXPERIMENTAL maximum uplink)': 3,
+             '5ms 6UL 3DL 10/2 (high uplink)':                 4}
             [cell.tdd_ul_dl_config]
             if tdd  else None  %}
 {%      if tdd_config == 1 %}
@@ -572,6 +573,16 @@
               ul_symbols: 2,
            },
          },
+{%      elif tdd_config == 4 %}
+         tdd_ul_dl_config: {
+           pattern1: {
+              period: 5, /* in ms */
+              dl_slots: 3,
+              dl_symbols: 2,
+              ul_slots: 6,
+              ul_symbols: 10,
+           },
+         },
 {%      endif %}
 
         prach: {

software/ors-amarisoft/slapos-render-config.py

@@ -409,7 +409,7 @@ def ORS_gnb(ienb):
         'root_sequence_index':  1,
         'pci':          500,
         'cell_id':      '0x01',
-        "tdd_ul_dl_config": "5ms 8UL 1DL 2/10 (maximum uplink)",
+        "tdd_ul_dl_config": "5ms 8UL 1DL 2/10 (EXPERIMENTAL maximum uplink)",
         'inactivity_timer': 10000,
         'ru': {
             'ru_type': 'ru_ref',

software/ors-amarisoft/test/test_ors.py

@@ -123,7 +123,7 @@ gnb_param_dict2 = {
         '0x171717': {'sd': '0x171717', 'sst': 10},
         '0x181818': {'sd': '0x181818', 'sst': 20},
     },
-    'tdd_ul_dl_config': '2.5ms 1UL 3DL 2/10',
+    'tdd_ul_dl_config': '5ms 6UL 3DL 10/2 (high uplink)',
 }
 enb_param_dict.update(param_dict)
 gnb_param_dict1.update(param_dict)
@@ -217,6 +217,13 @@ def test_gnb_conf2(self):
     self.assertEqual(sd, gnb_param_dict2['nssai'][sd]['sd'], 16)
     self.assertEqual(p['sst'], gnb_param_dict2['nssai'][sd]['sst'])
 
+  tdd_config = conf['nr_cell_list'][0]['tdd_ul_dl_config']['pattern1']
+  self.assertEqual(float(tdd_config['period']), 5)
+  self.assertEqual(int(tdd_config['dl_slots']), 3)
+  self.assertEqual(int(tdd_config['dl_symbols']), 2)
+  self.assertEqual(int(tdd_config['ul_slots']), 6)
+  self.assertEqual(int(tdd_config['ul_symbols']), 10)
+
 def test_mme_conf(self):
 
   conf_file = glob.glob(os.path.join(