- 25 May, 2022 1 commit
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Josua Mayer authored
Disable high-speed modes in Linux to ensure the microSD operates in the same mode as it does during rcw and u-boot. This is a work-around for when the system gets stuck after reset failing to read from the microSD card. Signed-off-by: Josua Mayer <josua@solid-run.com>
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- 11 May, 2022 1 commit
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 09 May, 2022 2 commits
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Josua Mayer authored
Directly connect the sfp drivers's (sfp.c) link up and down events to an LED node in device-tree. This solution is a workaround to the shortcomings of the generic led triggers framework in combination with multiple dynamic network interfaces, hot-pluggable phys (inside sfp modules) and the dpaa2 driver in particular. Signed-off-by: Josua Mayer <josua@solid-run.com>
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Rabeeh Khoury authored
The issue is that dpmac.16 to dpmac.18 links up, but unable to communicate thru those ports. This patch series does - 1. Fix dpmac.17 phy-handle type since by default the dpmac is RGMII, and in half-twins case it is thru SGMII. 2. Add to the build script the usage of MC firmware 10.28.100; which is based on 10.28.1 that fixes the tx/rx thru dpmac.16, dpmac.17 and dpmac.18. This firmware is only for LSDK-21.08 and will be fixed in later LSDK releases with newer MC firmwares. 3. Limit recycle queues in the half twins DPC to 1G; this makes it possible for dpmac.18 to be able to transmit Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 01 May, 2022 3 commits
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Rabeeh Khoury authored
1. Half twins is 8xSFP+ and 8xSFP with OCPv3 NIC support board 2. Using SD1=8S (PLLF=100MHz, PLLS=161.132825MHz) runtime downgrade from 10G to 1G, according to SFP module inserted is not supported 3. Reverted default DDR speed to 3200 Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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Rabeeh Khoury authored
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Josua Mayer authored
Signed-off-by: Josua Mayer <josua@solid-run.com>
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- 28 Apr, 2022 1 commit
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Josua Mayer authored
Also fix buildroot compile error when running as root, and allow using a local mirror. Signed-off-by: Josua Mayer <josua@solid-run.com>
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- 04 Apr, 2022 2 commits
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Yazan Shhady authored
lx2160acex7: add support for SERDES1 mode 21, wich support 6x 25GB [Lanes 1-4 & Lane 7-8]. Signed-off-by: Yazan Shhady <yazan.shhady@solid-run.com>
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Josua Mayer authored
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- 28 Mar, 2022 1 commit
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Josua Mayer authored
- can work with podman - added required packages - allow using an apt proxy Signed-off-by: Josua Mayer <josua@solid-run.com>
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- 21 Mar, 2022 1 commit
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Rabeeh Khoury authored
- Enabled CONFIG_SFP in the kernel build - Pulled SFP device tree patch from mainline - this enables dpmac7,8,9,10 that are the 4 SFP+ connectors on HoneyComb / ClearFog-CX - Pulled AR8035 phy device tree patch - Remove RTC interrupt from device tree - Added power button support to device tree Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 20 Mar, 2022 2 commits
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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Rabeeh Khoury authored
This patch debootstraps debian bullseye under arm64 emulated buildroot To build debian; run - DISTRO=debian ./runme.sh Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 30 Nov, 2021 1 commit
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 15 Jun, 2021 1 commit
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 17 Feb, 2021 2 commits
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Rabeeh Khoury authored
runme: check DDR speed before doing build
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Marcin Juszkiewicz authored
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- 24 Jan, 2021 1 commit
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Rabeeh Khoury authored
This patch adds most of the fixes to enable secure boot on the LX2160A COM express - 1. The atf patches fixes the efuse fip fuse loading, and setting of ppwm register and then gpio handling 2. The u-boot patches adds the secureboot defconfig, and then SVR_WO_E mask fix 3. Patches for runme.sh script; for building the secure image run with 'SECURE=true ./runme.sh' The missing piece is u-boot esbc validate code that completes the chain of trust boot (COT). Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 18 Jan, 2021 1 commit
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 17 Jan, 2021 1 commit
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Rabeeh Khoury authored
1. Added support for LSDK-20.12 2. Added initial support for secure boot; there are few atf patches that will be added later 3. Fixed documentation in README.md withregards SPI flashing to use cmp.b instead of cmp (the size is given in bytes) 4. Added ATF debug/release build environment variable Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 10 Jan, 2021 1 commit
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Russell King authored
Add support for mode 4, which allows connectivity with 1000base-X and SGMII to be used with the SFP and QSFP slots in conjunction with the kernel's PCS support. Signed-off-by: Russell King <rmk@armlinux.org.uk>
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- 04 Jan, 2021 1 commit
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 30 Dec, 2020 2 commits
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Rabeeh Khoury authored
ClearFog CX boards rev 1.3 and newer contains on carrier board retimers to support 100Gbps DAC cables. When configuring the SERDEses to 10Gbps the retimer configuration needs to be changed to lock on 10.3125Gbps rate on both the ingress (i2c address 0x23) and egress (i2c address 0x22) retimers. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 20 Dec, 2020 1 commit
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 17 Dec, 2020 2 commits
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Rabeeh Khoury authored
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Rabeeh Khoury authored
For machines that doesn't have sys_eeprom initialized, this can be done in u-boot by - sys_eeprom set 0x24 00:11:22:44:11:44 sys_eeprom set 0x2a 0x10 sys_eeprom write The first command will set the base MAC, the second will define a range of 16 MAC addresses (LX2 COM can actually go up to 17 MACs). The third command will save the TLV data. After that reset is required for the MAC addresses to get effective Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 13 Dec, 2020 1 commit
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yazan shhady authored
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- 08 Dec, 2020 2 commits
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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Rabeeh Khoury authored
1. Rename DWC3 SS patch from .patc to .patch 2. Add power button support to LX2 COM PWRBTN# GPIO input 3. Set pinmuxing to correctly read SD card CD# signal when booting from SPI / eMMC. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 08 Nov, 2020 2 commits
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Rabeeh Khoury authored
issue found when working with 12c variant and CAN-FD is disabled (bit12) Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 03 Nov, 2020 2 commits
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 01 Nov, 2020 1 commit
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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- 28 Oct, 2020 4 commits
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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Rabeeh Khoury authored
1. Added TI based retimer initialization on 25Gbp SERDES configuration. Note that those retimers are available on ClearFog CX revision 1.3 and newer 2. Restructure SERDES configuration files Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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Rabeeh Khoury authored
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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Rabeeh Khoury authored
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