dce110_resource.c 34.7 KB
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dm_services.h"

#include "link_encoder.h"
#include "stream_encoder.h"

#include "resource.h"
#include "dce110/dce110_resource.h"

#include "include/irq_service_interface.h"
#include "dce/dce_audio.h"
#include "dce110/dce110_timing_generator.h"
#include "irq/dce110/irq_service_dce110.h"
#include "dce110/dce110_timing_generator_v.h"
#include "dce/dce_link_encoder.h"
#include "dce/dce_stream_encoder.h"
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#include "dce/dce_mem_input.h"
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#include "dce110/dce110_mem_input_v.h"
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#include "dce/dce_ipp.h"
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#include "dce/dce_transform.h"
#include "dce110/dce110_transform_v.h"
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#include "dce/dce_opp.h"
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#include "dce110/dce110_opp_v.h"
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#include "dce/dce_clocks.h"
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#include "dce/dce_clock_source.h"
#include "dce/dce_hwseq.h"
#include "dce110/dce110_hw_sequencer.h"
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#include "dce/dce_abm.h"
#include "dce/dce_dmcu.h"
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#ifdef ENABLE_FBC
#include "dce110/dce110_compressor.h"
#endif

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#include "reg_helper.h"

#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_sh_mask.h"

#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
#include "gmc/gmc_8_2_d.h"
#include "gmc/gmc_8_2_sh_mask.h"
#endif

#ifndef mmDP_DPHY_INTERNAL_CTRL
	#define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
	#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
	#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
	#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
	#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
	#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
	#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
	#define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
	#define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
	#define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
#endif

#ifndef mmBIOS_SCRATCH_2
	#define mmBIOS_SCRATCH_2 0x05CB
	#define mmBIOS_SCRATCH_6 0x05CF
#endif

#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
	#define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
	#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
	#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
	#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
	#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
	#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
	#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
	#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
#endif

#ifndef mmDP_DPHY_FAST_TRAINING
	#define mmDP_DPHY_FAST_TRAINING                         0x4ABC
	#define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
	#define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
	#define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
	#define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
	#define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
	#define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
	#define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
#endif

#ifndef DPHY_RX_FAST_TRAINING_CAPABLE
	#define DPHY_RX_FAST_TRAINING_CAPABLE 0x1
#endif

static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
	{
		.crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
		.dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
	},
	{
		.crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
	},
	{
		.crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
	},
	{
		.crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
		.dcp =  (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
	},
	{
		.crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
	},
	{
		.crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
	}
};

/* set register offset */
#define SR(reg_name)\
	.reg_name = mm ## reg_name

/* set register offset with instance */
#define SRI(reg_name, block, id)\
	.reg_name = mm ## block ## id ## _ ## reg_name

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static const struct dce_disp_clk_registers disp_clk_regs = {
		CLK_COMMON_REG_LIST_DCE_BASE()
};

static const struct dce_disp_clk_shift disp_clk_shift = {
		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
};

static const struct dce_disp_clk_mask disp_clk_mask = {
		CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
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static const struct dce_dmcu_registers dmcu_regs = {
		DMCU_DCE110_COMMON_REG_LIST()
};

static const struct dce_dmcu_shift dmcu_shift = {
		DMCU_MASK_SH_LIST_DCE110(__SHIFT)
};

static const struct dce_dmcu_mask dmcu_mask = {
		DMCU_MASK_SH_LIST_DCE110(_MASK)
};

static const struct dce_abm_registers abm_regs = {
		ABM_DCE110_COMMON_REG_LIST()
};

static const struct dce_abm_shift abm_shift = {
		ABM_MASK_SH_LIST_DCE110(__SHIFT)
};

static const struct dce_abm_mask abm_mask = {
		ABM_MASK_SH_LIST_DCE110(_MASK)
};

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#define ipp_regs(id)\
[id] = {\
		IPP_DCE110_REG_LIST_DCE_BASE(id)\
}

static const struct dce_ipp_registers ipp_regs[] = {
		ipp_regs(0),
		ipp_regs(1),
		ipp_regs(2)
};

static const struct dce_ipp_shift ipp_shift = {
		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
};

static const struct dce_ipp_mask ipp_mask = {
		IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};

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#define transform_regs(id)\
[id] = {\
		XFM_COMMON_REG_LIST_DCE110(id)\
}

static const struct dce_transform_registers xfm_regs[] = {
		transform_regs(0),
		transform_regs(1),
		transform_regs(2)
};

static const struct dce_transform_shift xfm_shift = {
		XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
};

static const struct dce_transform_mask xfm_mask = {
		XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
};

#define aux_regs(id)\
[id] = {\
	AUX_REG_LIST(id)\
}

static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
		aux_regs(0),
		aux_regs(1),
		aux_regs(2),
		aux_regs(3),
		aux_regs(4),
		aux_regs(5)
};

#define hpd_regs(id)\
[id] = {\
	HPD_REG_LIST(id)\
}

static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
		hpd_regs(0),
		hpd_regs(1),
		hpd_regs(2),
		hpd_regs(3),
		hpd_regs(4),
		hpd_regs(5)
};


#define link_regs(id)\
[id] = {\
	LE_DCE110_REG_LIST(id)\
}

static const struct dce110_link_enc_registers link_enc_regs[] = {
	link_regs(0),
	link_regs(1),
	link_regs(2),
	link_regs(3),
	link_regs(4),
	link_regs(5),
	link_regs(6),
};

#define stream_enc_regs(id)\
[id] = {\
	SE_COMMON_REG_LIST(id),\
	.TMDS_CNTL = 0,\
}

static const struct dce110_stream_enc_registers stream_enc_regs[] = {
	stream_enc_regs(0),
	stream_enc_regs(1),
	stream_enc_regs(2)
};

static const struct dce_stream_encoder_shift se_shift = {
		SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
};

static const struct dce_stream_encoder_mask se_mask = {
		SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
};

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#define opp_regs(id)\
[id] = {\
	OPP_DCE_110_REG_LIST(id),\
}

static const struct dce_opp_registers opp_regs[] = {
	opp_regs(0),
	opp_regs(1),
	opp_regs(2),
	opp_regs(3),
	opp_regs(4),
	opp_regs(5)
};

static const struct dce_opp_shift opp_shift = {
	OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT)
};

static const struct dce_opp_mask opp_mask = {
	OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK)
};

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#define audio_regs(id)\
[id] = {\
	AUD_COMMON_REG_LIST(id)\
}

static const struct dce_audio_registers audio_regs[] = {
	audio_regs(0),
	audio_regs(1),
	audio_regs(2),
	audio_regs(3),
	audio_regs(4),
	audio_regs(5),
	audio_regs(6),
};

static const struct dce_audio_shift audio_shift = {
		AUD_COMMON_MASK_SH_LIST(__SHIFT)
};

static const struct dce_aduio_mask audio_mask = {
		AUD_COMMON_MASK_SH_LIST(_MASK)
};

/* AG TBD Needs to be reduced back to 3 pipes once dce10 hw sequencer implemented. */
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#define clk_src_regs(id)\
[id] = {\
	CS_COMMON_REG_LIST_DCE_100_110(id),\
}

static const struct dce110_clk_src_regs clk_src_regs[] = {
	clk_src_regs(0),
	clk_src_regs(1),
	clk_src_regs(2)
};

static const struct dce110_clk_src_shift cs_shift = {
		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
};

static const struct dce110_clk_src_mask cs_mask = {
		CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};

static const struct bios_registers bios_regs = {
	.BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
};

static const struct resource_caps carrizo_resource_cap = {
		.num_timing_generator = 3,
		.num_video_plane = 1,
		.num_audio = 3,
		.num_stream_encoder = 3,
		.num_pll = 2,
};

static const struct resource_caps stoney_resource_cap = {
		.num_timing_generator = 2,
		.num_video_plane = 1,
		.num_audio = 3,
		.num_stream_encoder = 3,
		.num_pll = 2,
};

#define CTX  ctx
#define REG(reg) mm ## reg

#ifndef mmCC_DC_HDMI_STRAPS
#define mmCC_DC_HDMI_STRAPS 0x4819
#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
#endif

static void read_dce_straps(
	struct dc_context *ctx,
	struct resource_straps *straps)
{
	REG_GET_2(CC_DC_HDMI_STRAPS,
			HDMI_DISABLE, &straps->hdmi_disable,
			AUDIO_STREAM_NUMBER, &straps->audio_stream_number);

	REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
}

static struct audio *create_audio(
		struct dc_context *ctx, unsigned int inst)
{
	return dce_audio_create(ctx, inst,
			&audio_regs[inst], &audio_shift, &audio_mask);
}

static struct timing_generator *dce110_timing_generator_create(
		struct dc_context *ctx,
		uint32_t instance,
		const struct dce110_timing_generator_offsets *offsets)
{
	struct dce110_timing_generator *tg110 =
		dm_alloc(sizeof(struct dce110_timing_generator));

	if (!tg110)
		return NULL;

	if (dce110_timing_generator_construct(tg110, ctx, instance, offsets))
		return &tg110->base;

	BREAK_TO_DEBUGGER();
	dm_free(tg110);
	return NULL;
}

static struct stream_encoder *dce110_stream_encoder_create(
	enum engine_id eng_id,
	struct dc_context *ctx)
{
	struct dce110_stream_encoder *enc110 =
		dm_alloc(sizeof(struct dce110_stream_encoder));

	if (!enc110)
		return NULL;

	if (dce110_stream_encoder_construct(
			enc110, ctx, ctx->dc_bios, eng_id,
			&stream_enc_regs[eng_id], &se_shift, &se_mask))
		return &enc110->base;

	BREAK_TO_DEBUGGER();
	dm_free(enc110);
	return NULL;
}

#define SRII(reg_name, block, id)\
	.reg_name[id] = mm ## block ## id ## _ ## reg_name

static const struct dce_hwseq_registers hwseq_stoney_reg = {
		HWSEQ_ST_REG_LIST()
};

static const struct dce_hwseq_registers hwseq_cz_reg = {
		HWSEQ_CZ_REG_LIST()
};

static const struct dce_hwseq_shift hwseq_shift = {
		HWSEQ_DCE11_MASK_SH_LIST(__SHIFT),
};

static const struct dce_hwseq_mask hwseq_mask = {
		HWSEQ_DCE11_MASK_SH_LIST(_MASK),
};

static struct dce_hwseq *dce110_hwseq_create(
	struct dc_context *ctx)
{
	struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq));

	if (hws) {
		hws->ctx = ctx;
		hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ?
				&hwseq_stoney_reg : &hwseq_cz_reg;
		hws->shifts = &hwseq_shift;
		hws->masks = &hwseq_mask;
		hws->wa.blnd_crtc_trigger = true;
	}
	return hws;
}

static const struct resource_create_funcs res_create_funcs = {
	.read_dce_straps = read_dce_straps,
	.create_audio = create_audio,
	.create_stream_encoder = dce110_stream_encoder_create,
	.create_hwseq = dce110_hwseq_create,
};

#define mi_inst_regs(id) { \
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	MI_DCE11_REG_LIST(id), \
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	.MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
}
static const struct dce_mem_input_registers mi_regs[] = {
		mi_inst_regs(0),
		mi_inst_regs(1),
		mi_inst_regs(2),
};

static const struct dce_mem_input_shift mi_shifts = {
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		MI_DCE11_MASK_SH_LIST(__SHIFT),
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		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
};

static const struct dce_mem_input_mask mi_masks = {
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		MI_DCE11_MASK_SH_LIST(_MASK),
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		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
};

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static struct mem_input *dce110_mem_input_create(
	struct dc_context *ctx,
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	uint32_t inst)
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{
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	struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input));
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	if (!dce_mi) {
		BREAK_TO_DEBUGGER();
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		return NULL;
	}

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	dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
	dce_mi->wa.single_head_rdreq_dmif_limit = 3;
	return &dce_mi->base;
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}

static void dce110_transform_destroy(struct transform **xfm)
{
	dm_free(TO_DCE_TRANSFORM(*xfm));
	*xfm = NULL;
}

static struct transform *dce110_transform_create(
	struct dc_context *ctx,
	uint32_t inst)
{
	struct dce_transform *transform =
		dm_alloc(sizeof(struct dce_transform));

	if (!transform)
		return NULL;

	if (dce_transform_construct(transform, ctx, inst,
			&xfm_regs[inst], &xfm_shift, &xfm_mask))
		return &transform->base;

	BREAK_TO_DEBUGGER();
	dm_free(transform);
	return NULL;
}

static struct input_pixel_processor *dce110_ipp_create(
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	struct dc_context *ctx, uint32_t inst)
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{
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	struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp));
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	if (!ipp) {
		BREAK_TO_DEBUGGER();
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		return NULL;
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	}
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	dce_ipp_construct(ipp, ctx, inst,
			&ipp_regs[inst], &ipp_shift, &ipp_mask);
	return &ipp->base;
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}

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static const struct encoder_feature_support link_enc_feature = {
		.max_hdmi_deep_color = COLOR_DEPTH_121212,
		.max_hdmi_pixel_clock = 594000,
		.flags.bits.IS_HBR2_CAPABLE = true,
		.flags.bits.IS_TPS3_CAPABLE = true,
		.flags.bits.IS_YCBCR_CAPABLE = true
};

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static struct link_encoder *dce110_link_encoder_create(
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	const struct encoder_init_data *enc_init_data)
{
	struct dce110_link_encoder *enc110 =
		dm_alloc(sizeof(struct dce110_link_encoder));

	if (!enc110)
		return NULL;

	if (dce110_link_encoder_construct(
			enc110,
			enc_init_data,
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			&link_enc_feature,
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			&link_enc_regs[enc_init_data->transmitter],
			&link_enc_aux_regs[enc_init_data->channel - 1],
			&link_enc_hpd_regs[enc_init_data->hpd_source])) {

		return &enc110->base;
	}

	BREAK_TO_DEBUGGER();
	dm_free(enc110);
	return NULL;
}

static struct output_pixel_processor *dce110_opp_create(
	struct dc_context *ctx,
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	uint32_t inst)
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{
	struct dce110_opp *opp =
		dm_alloc(sizeof(struct dce110_opp));

	if (!opp)
		return NULL;

	if (dce110_opp_construct(opp,
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				ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask))
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		return &opp->base;

	BREAK_TO_DEBUGGER();
	dm_free(opp);
	return NULL;
}

struct clock_source *dce110_clock_source_create(
	struct dc_context *ctx,
	struct dc_bios *bios,
	enum clock_source_id id,
	const struct dce110_clk_src_regs *regs,
	bool dp_clk_src)
{
	struct dce110_clk_src *clk_src =
		dm_alloc(sizeof(struct dce110_clk_src));

	if (!clk_src)
		return NULL;

	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
			regs, &cs_shift, &cs_mask)) {
		clk_src->base.dp_clk_src = dp_clk_src;
		return &clk_src->base;
	}

	BREAK_TO_DEBUGGER();
	return NULL;
}

void dce110_clock_source_destroy(struct clock_source **clk_src)
{
	struct dce110_clk_src *dce110_clk_src;

	if (!clk_src)
		return;

	dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src);

	if (dce110_clk_src->dp_ss_params)
		dm_free(dce110_clk_src->dp_ss_params);

	if (dce110_clk_src->hdmi_ss_params)
		dm_free(dce110_clk_src->hdmi_ss_params);

	if (dce110_clk_src->dvi_ss_params)
		dm_free(dce110_clk_src->dvi_ss_params);

	dm_free(dce110_clk_src);
	*clk_src = NULL;
}

static void destruct(struct dce110_resource_pool *pool)
{
	unsigned int i;

	for (i = 0; i < pool->base.pipe_count; i++) {
		if (pool->base.opps[i] != NULL)
			dce110_opp_destroy(&pool->base.opps[i]);

		if (pool->base.transforms[i] != NULL)
			dce110_transform_destroy(&pool->base.transforms[i]);

		if (pool->base.ipps[i] != NULL)
669
			dce_ipp_destroy(&pool->base.ipps[i]);
670 671

		if (pool->base.mis[i] != NULL) {
672
			dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i]));
673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701
			pool->base.mis[i] = NULL;
		}

		if (pool->base.timing_generators[i] != NULL)	{
			dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
			pool->base.timing_generators[i] = NULL;
		}
	}

	for (i = 0; i < pool->base.stream_enc_count; i++) {
		if (pool->base.stream_enc[i] != NULL)
			dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
	}

	for (i = 0; i < pool->base.clk_src_count; i++) {
		if (pool->base.clock_sources[i] != NULL) {
			dce110_clock_source_destroy(&pool->base.clock_sources[i]);
		}
	}

	if (pool->base.dp_clock_source != NULL)
		dce110_clock_source_destroy(&pool->base.dp_clock_source);

	for (i = 0; i < pool->base.audio_count; i++)	{
		if (pool->base.audios[i] != NULL) {
			dce_aud_destroy(&pool->base.audios[i]);
		}
	}

702 703 704 705 706 707
	if (pool->base.abm != NULL)
		dce_abm_destroy(&pool->base.abm);

	if (pool->base.dmcu != NULL)
		dce_dmcu_destroy(&pool->base.dmcu);

708 709
	if (pool->base.display_clock != NULL)
		dce_disp_clk_destroy(&pool->base.display_clock);
710 711 712 713 714 715 716 717 718 719 720

	if (pool->base.irqs != NULL) {
		dal_irq_service_destroy(&pool->base.irqs);
	}
}


static void get_pixel_clock_parameters(
	const struct pipe_ctx *pipe_ctx,
	struct pixel_clk_params *pixel_clk_params)
{
721
	const struct dc_stream_state *stream = pipe_ctx->stream;
722 723 724 725 726

	/*TODO: is this halved for YCbCr 420? in that case we might want to move
	 * the pixel clock normalization for hdmi up to here instead of doing it
	 * in pll_adjust_pix_clk
	 */
727
	pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
728 729 730 731 732 733 734 735
	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
	pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
	/* TODO: un-hardcode*/
	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
						LINK_RATE_REF_FREQ_IN_KHZ;
	pixel_clk_params->flags.ENABLE_SS = 0;
	pixel_clk_params->color_depth =
736
		stream->timing.display_color_depth;
737
	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
738
	pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
739
			PIXEL_ENCODING_YCBCR420);
740 741
	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
742 743
		pixel_clk_params->color_depth = COLOR_DEPTH_888;
	}
744
	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
745 746
		pixel_clk_params->requested_pix_clk  = pixel_clk_params->requested_pix_clk / 2;
	}
747 748 749 750
}

enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
{
751
	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
752 753
	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
		pipe_ctx->clock_source,
754
		&pipe_ctx->stream_res.pix_clk_params,
755
		&pipe_ctx->pll_settings);
756
	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
757
			&pipe_ctx->stream->bit_depth_params);
758
	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
759 760 761 762 763 764 765 766

	return DC_OK;
}

static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigned int underlay_idx)
{
	if (pipe_ctx->pipe_idx != underlay_idx)
		return true;
767
	if (!pipe_ctx->plane_state)
768
		return false;
769
	if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
770 771 772 773
		return false;
	return true;
}

774
static enum dc_status build_mapped_resource(
775
		const struct dc *dc,
776
		struct validate_context *context,
777
		struct dc_stream_state *stream)
778 779
{
	enum dc_status status = DC_OK;
780
	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
781

782 783
	if (!pipe_ctx)
		return DC_ERROR_UNEXPECTED;
784

785 786 787
	if (!is_surface_pixel_format_supported(pipe_ctx,
			dc->res_pool->underlay_pipe_index))
		return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED;
788

789
	status = dce110_resource_build_pipe_hw_param(pipe_ctx);
790

791 792
	if (status != DC_OK)
		return status;
793

794
	/* TODO: validate audio ASIC caps, encoder */
795

796
	resource_build_info_frame(pipe_ctx);
797 798 799 800

	return DC_OK;
}

801
static bool dce110_validate_bandwidth(
802
	struct dc *dc,
803 804
	struct validate_context *context)
{
805
	bool result = false;
806 807 808 809 810 811

	dm_logger_write(
		dc->ctx->logger, LOG_BANDWIDTH_CALCS,
		"%s: start",
		__func__);

812
	if (bw_calcs(
813
			dc->ctx,
814 815
			dc->bw_dceip,
			dc->bw_vbios,
816
			context->res_ctx.pipe_ctx,
817
			dc->res_pool->pipe_count,
818
			&context->bw.dce))
819
		result =  true;
820

821
	if (!result)
822 823 824
		dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
			"%s: %dx%d@%d Bandwidth validation failed!\n",
			__func__,
825 826 827
			context->streams[0]->timing.h_addressable,
			context->streams[0]->timing.v_addressable,
			context->streams[0]->timing.pix_clk_khz);
828

829 830
	if (memcmp(&dc->current_context->bw.dce,
			&context->bw.dce, sizeof(context->bw.dce))) {
831 832 833 834 835 836 837 838 839
		struct log_entry log_entry;
		dm_logger_open(
			dc->ctx->logger,
			&log_entry,
			LOG_BANDWIDTH_CALCS);
		dm_logger_append(&log_entry, "%s: finish,\n"
			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
			"stutMark_b: %d stutMark_a: %d\n",
			__func__,
840 841 842 843 844 845
			context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
			context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
			context->bw.dce.urgent_wm_ns[0].b_mark,
			context->bw.dce.urgent_wm_ns[0].a_mark,
			context->bw.dce.stutter_exit_wm_ns[0].b_mark,
			context->bw.dce.stutter_exit_wm_ns[0].a_mark);
846 847 848
		dm_logger_append(&log_entry,
			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
			"stutMark_b: %d stutMark_a: %d\n",
849 850 851 852 853 854
			context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
			context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
			context->bw.dce.urgent_wm_ns[1].b_mark,
			context->bw.dce.urgent_wm_ns[1].a_mark,
			context->bw.dce.stutter_exit_wm_ns[1].b_mark,
			context->bw.dce.stutter_exit_wm_ns[1].a_mark);
855 856 857
		dm_logger_append(&log_entry,
			"nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
			"stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n",
858 859 860 861 862 863 864
			context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
			context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
			context->bw.dce.urgent_wm_ns[2].b_mark,
			context->bw.dce.urgent_wm_ns[2].a_mark,
			context->bw.dce.stutter_exit_wm_ns[2].b_mark,
			context->bw.dce.stutter_exit_wm_ns[2].a_mark,
			context->bw.dce.stutter_mode_enable);
865 866 867
		dm_logger_append(&log_entry,
			"cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
			"sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n",
868 869 870 871 872 873 874 875 876
			context->bw.dce.cpuc_state_change_enable,
			context->bw.dce.cpup_state_change_enable,
			context->bw.dce.nbp_state_change_enable,
			context->bw.dce.all_displays_in_sync,
			context->bw.dce.dispclk_khz,
			context->bw.dce.sclk_khz,
			context->bw.dce.sclk_deep_sleep_khz,
			context->bw.dce.yclk_khz,
			context->bw.dce.blackout_recovery_time_us);
877 878 879 880 881 882 883 884 885 886 887 888
		dm_logger_close(&log_entry);
	}
	return result;
}

static bool dce110_validate_surface_sets(
		const struct dc_validation_set set[],
		int set_count)
{
	int i;

	for (i = 0; i < set_count; i++) {
889
		if (set[i].plane_count == 0)
890 891
			continue;

892
		if (set[i].plane_count > 2)
893 894
			return false;

895
		if (set[i].plane_states[0]->format
896 897 898
				>= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
			return false;

899 900
		if (set[i].plane_count == 2) {
			if (set[i].plane_states[1]->format
901 902
					< SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
				return false;
903 904
			if (set[i].plane_states[1]->src_rect.width > 1920
					|| set[i].plane_states[1]->src_rect.height > 1080)
905 906
				return false;

907
			if (set[i].stream->timing.pixel_encoding != PIXEL_ENCODING_RGB)
908 909 910 911 912 913 914
				return false;
		}
	}

	return true;
}

915
enum dc_status dce110_validate_global(
916
		struct dc *dc,
917 918
		const struct dc_validation_set set[],
		int set_count,
919 920
		struct validate_context *old_context,
		struct validate_context *context)
921 922 923 924
{
	if (!dce110_validate_surface_sets(set, set_count))
		return DC_FAIL_SURFACE_VALIDATE;

925
	return DC_OK;
926 927
}

928
static enum dc_status dce110_validate_guaranteed(
929
		struct dc *dc,
930
		struct dc_stream_state *dc_stream,
931 932 933 934
		struct validate_context *context)
{
	enum dc_status result = DC_ERROR_UNEXPECTED;

935 936
	context->streams[0] = dc_stream;
	dc_stream_retain(context->streams[0]);
937
	context->stream_count++;
938

939
	result = resource_map_pool_resources(dc, context, dc_stream);
940 941

	if (result == DC_OK)
942
		result = resource_map_clock_resources(dc, context, dc_stream);
943 944

	if (result == DC_OK)
945
		result = build_mapped_resource(dc, context, dc_stream);
946 947

	if (result == DC_OK) {
948
		validate_guaranteed_copy_streams(
949
				context, dc->caps.max_streams);
950 951 952 953
		result = resource_build_scaling_params_for_context(dc, context);
	}

	if (result == DC_OK)
954 955
		if (!dce110_validate_bandwidth(dc, context))
			result = DC_FAIL_BANDWIDTH_VALIDATE;
956 957 958 959

	return result;
}

960 961
static struct pipe_ctx *dce110_acquire_underlay(
		struct validate_context *context,
962
		const struct resource_pool *pool,
963
		struct dc_stream_state *stream)
964
{
965
	struct dc *dc = stream->ctx->dc;
966
	struct resource_context *res_ctx = &context->res_ctx;
967
	unsigned int underlay_idx = pool->underlay_pipe_index;
968 969
	struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[underlay_idx];

970
	if (res_ctx->pipe_ctx[underlay_idx].stream)
971 972
		return NULL;

973
	pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
974 975 976
	pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
	/*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
	pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
977
	pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
978
	pipe_ctx->dis_clk = pool->display_clock;
979 980 981 982
	pipe_ctx->pipe_idx = underlay_idx;

	pipe_ctx->stream = stream;

983 984 985 986 987 988 989 990 991 992 993 994 995 996
	if (!dc->current_context->res_ctx.pipe_ctx[underlay_idx].stream) {
		struct tg_color black_color = {0};
		struct dc_bios *dcb = dc->ctx->dc_bios;

		dc->hwss.enable_display_power_gating(
				dc,
				pipe_ctx->pipe_idx,
				dcb, PIPE_GATING_CONTROL_DISABLE);

		/*
		 * This is for powering on underlay, so crtc does not
		 * need to be enabled
		 */

997
		pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
998
				&stream->timing,
999 1000
				false);

1001 1002
		pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
				pipe_ctx->stream_res.tg,
1003
				true,
1004
				&stream->timing);
1005

1006
		pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
1007 1008 1009
				stream->timing.h_total,
				stream->timing.v_total,
				stream->timing.pix_clk_khz,
1010 1011 1012 1013
				context->stream_count);

		color_space_to_black_color(dc,
				COLOR_SPACE_YCBCR601, &black_color);
1014 1015
		pipe_ctx->stream_res.tg->funcs->set_blank_color(
				pipe_ctx->stream_res.tg,
1016 1017
				&black_color);
	}
1018

1019
	return pipe_ctx;
1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036
}

static void dce110_destroy_resource_pool(struct resource_pool **pool)
{
	struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);

	destruct(dce110_pool);
	dm_free(dce110_pool);
	*pool = NULL;
}


static const struct resource_funcs dce110_res_pool_funcs = {
	.destroy = dce110_destroy_resource_pool,
	.link_enc_create = dce110_link_encoder_create,
	.validate_guaranteed = dce110_validate_guaranteed,
	.validate_bandwidth = dce110_validate_bandwidth,
1037
	.acquire_idle_pipe_for_layer = dce110_acquire_underlay,
1038
	.validate_global = dce110_validate_global
1039 1040
};

1041
static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
1042 1043 1044
{
	struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv));
	struct dce_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv));
1045
	struct dce_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv));
1046 1047
	struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv));

1048 1049 1050 1051 1052 1053 1054 1055 1056
	if ((dce110_tgv == NULL) ||
		(dce110_xfmv == NULL) ||
		(dce110_miv == NULL) ||
		(dce110_oppv == NULL))
			return false;

	if (!dce110_opp_v_construct(dce110_oppv, ctx))
		return false;

1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069
	dce110_timing_generator_v_construct(dce110_tgv, ctx);
	dce110_mem_input_v_construct(dce110_miv, ctx);
	dce110_transform_v_construct(dce110_xfmv, ctx);

	pool->opps[pool->pipe_count] = &dce110_oppv->base;
	pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
	pool->mis[pool->pipe_count] = &dce110_miv->base;
	pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
	pool->pipe_count++;

	/* update the public caps to indicate an underlay is available */
	ctx->dc->caps.max_slave_planes = 1;
	ctx->dc->caps.max_slave_planes = 1;
1070 1071

	return true;
1072 1073
}

1074
static void bw_calcs_data_update_from_pplib(struct dc *dc)
1075 1076 1077 1078 1079 1080 1081 1082 1083
{
	struct dm_pp_clock_levels clks = {0};

	/*do system clock*/
	dm_pp_get_clock_levels_by_type(
			dc->ctx,
			DM_PP_CLOCK_TYPE_ENGINE_CLK,
			&clks);
	/* convert all the clock fro kHz to fix point mHz */
1084
	dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1085
			clks.clocks_in_khz[clks.num_levels-1], 1000);
1086
	dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1087
			clks.clocks_in_khz[clks.num_levels/8], 1000);
1088
	dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1089
			clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1090
	dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1091
			clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1092
	dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1093
			clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1094
	dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1095
			clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1096
	dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1097
			clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1098
	dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1099 1100 1101 1102 1103 1104 1105 1106
			clks.clocks_in_khz[0], 1000);
	dc->sclk_lvls = clks;

	/*do display clock*/
	dm_pp_get_clock_levels_by_type(
			dc->ctx,
			DM_PP_CLOCK_TYPE_DISPLAY_CLK,
			&clks);
1107
	dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(
1108
			clks.clocks_in_khz[clks.num_levels-1], 1000);
1109
	dc->bw_vbios->mid_voltage_max_dispclk  = bw_frc_to_fixed(
1110
			clks.clocks_in_khz[clks.num_levels>>1], 1000);
1111
	dc->bw_vbios->low_voltage_max_dispclk  = bw_frc_to_fixed(
1112 1113 1114 1115 1116 1117 1118 1119
			clks.clocks_in_khz[0], 1000);

	/*do memory clock*/
	dm_pp_get_clock_levels_by_type(
			dc->ctx,
			DM_PP_CLOCK_TYPE_MEMORY_CLK,
			&clks);

1120
	dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1121
		clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
1122
	dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1123 1124
		clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
		1000);
1125
	dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140
		clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
		1000);
}

const struct resource_caps *dce110_resource_cap(
	struct hw_asic_id *asic_id)
{
	if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
		return &stoney_resource_cap;
	else
		return &carrizo_resource_cap;
}

static bool construct(
	uint8_t num_virtual_links,
1141
	struct dc *dc,
1142 1143 1144 1145 1146
	struct dce110_resource_pool *pool,
	struct hw_asic_id asic_id)
{
	unsigned int i;
	struct dc_context *ctx = dc->ctx;
1147
	struct dc_firmware_info info;
1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162
	struct dc_bios *bp;
	struct dm_pp_static_clock_info static_clk_info = {0};

	ctx->dc_bios->regs = &bios_regs;

	pool->base.res_cap = dce110_resource_cap(&ctx->asic_id);
	pool->base.funcs = &dce110_res_pool_funcs;

	/*************************************************
	 *  Resource + asic cap harcoding                *
	 *************************************************/

	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
	pool->base.underlay_pipe_index = pool->base.pipe_count;

1163 1164 1165
	dc->caps.max_downscale_ratio = 150;
	dc->caps.i2c_speed_in_khz = 100;
	dc->caps.max_cursor_size = 128;
1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203

	/*************************************************
	 *  Create resources                             *
	 *************************************************/

	bp = ctx->dc_bios;

	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
		info.external_clock_source_frequency_for_dp != 0) {
		pool->base.dp_clock_source =
				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);

		pool->base.clock_sources[0] =
				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0,
						&clk_src_regs[0], false);
		pool->base.clock_sources[1] =
				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1,
						&clk_src_regs[1], false);

		pool->base.clk_src_count = 2;

		/* TODO: find out if CZ support 3 PLLs */
	}

	if (pool->base.dp_clock_source == NULL) {
		dm_error("DC: failed to create dp clock source!\n");
		BREAK_TO_DEBUGGER();
		goto res_create_fail;
	}

	for (i = 0; i < pool->base.clk_src_count; i++) {
		if (pool->base.clock_sources[i] == NULL) {
			dm_error("DC: failed to create clock sources!\n");
			BREAK_TO_DEBUGGER();
			goto res_create_fail;
		}
	}

1204 1205 1206 1207
	pool->base.display_clock = dce110_disp_clk_create(ctx,
			&disp_clk_regs,
			&disp_clk_shift,
			&disp_clk_mask);
1208 1209 1210 1211 1212 1213
	if (pool->base.display_clock == NULL) {
		dm_error("DC: failed to create display clock!\n");
		BREAK_TO_DEBUGGER();
		goto res_create_fail;
	}

1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233
	pool->base.dmcu = dce_dmcu_create(ctx,
			&dmcu_regs,
			&dmcu_shift,
			&dmcu_mask);
	if (pool->base.dmcu == NULL) {
		dm_error("DC: failed to create dmcu!\n");
		BREAK_TO_DEBUGGER();
		goto res_create_fail;
	}

	pool->base.abm = dce_abm_create(ctx,
			&abm_regs,
			&abm_shift,
			&abm_mask);
	if (pool->base.abm == NULL) {
		dm_error("DC: failed to create abm!\n");
		BREAK_TO_DEBUGGER();
		goto res_create_fail;
	}

1234 1235 1236
	/* get static clock information for PPLIB or firmware, save
	 * max_clock_state
	 */
1237 1238
	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
		pool->base.display_clock->max_clks_state =
1239
				static_clk_info.max_clocks_state;
1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257

	{
		struct irq_service_init_data init_data;
		init_data.ctx = dc->ctx;
		pool->base.irqs = dal_irq_service_dce110_create(&init_data);
		if (!pool->base.irqs)
			goto res_create_fail;
	}

	for (i = 0; i < pool->base.pipe_count; i++) {
		pool->base.timing_generators[i] = dce110_timing_generator_create(
				ctx, i, &dce110_tg_offsets[i]);
		if (pool->base.timing_generators[i] == NULL) {
			BREAK_TO_DEBUGGER();
			dm_error("DC: failed to create tg!\n");
			goto res_create_fail;
		}

1258
		pool->base.mis[i] = dce110_mem_input_create(ctx, i);
1259 1260 1261 1262 1263 1264 1265
		if (pool->base.mis[i] == NULL) {
			BREAK_TO_DEBUGGER();
			dm_error(
				"DC: failed to create memory input!\n");
			goto res_create_fail;
		}

1266
		pool->base.ipps[i] = dce110_ipp_create(ctx, i);
1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281
		if (pool->base.ipps[i] == NULL) {
			BREAK_TO_DEBUGGER();
			dm_error(
				"DC: failed to create input pixel processor!\n");
			goto res_create_fail;
		}

		pool->base.transforms[i] = dce110_transform_create(ctx, i);
		if (pool->base.transforms[i] == NULL) {
			BREAK_TO_DEBUGGER();
			dm_error(
				"DC: failed to create transform!\n");
			goto res_create_fail;
		}

1282
		pool->base.opps[i] = dce110_opp_create(ctx, i);
1283 1284 1285 1286 1287 1288 1289 1290
		if (pool->base.opps[i] == NULL) {
			BREAK_TO_DEBUGGER();
			dm_error(
				"DC: failed to create output pixel processor!\n");
			goto res_create_fail;
		}
	}

1291 1292 1293 1294 1295 1296
#ifdef ENABLE_FBC
	dc->fbc_compressor = dce110_compressor_create(ctx);



#endif
1297 1298
	if (!underlay_create(ctx, &pool->base))
		goto res_create_fail;
1299 1300 1301 1302 1303 1304 1305 1306 1307

	if (!resource_construct(num_virtual_links, dc, &pool->base,
			&res_create_funcs))
		goto res_create_fail;

	/* Create hardware sequencer */
	if (!dce110_hw_sequencer_construct(dc))
		goto res_create_fail;

1308
	dc->caps.max_planes =  pool->base.pipe_count;
1309

1310
	bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322

	bw_calcs_data_update_from_pplib(dc);

	return true;

res_create_fail:
	destruct(pool);
	return false;
}

struct resource_pool *dce110_create_resource_pool(
	uint8_t num_virtual_links,
1323
	struct dc *dc,
1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337
	struct hw_asic_id asic_id)
{
	struct dce110_resource_pool *pool =
		dm_alloc(sizeof(struct dce110_resource_pool));

	if (!pool)
		return NULL;

	if (construct(num_virtual_links, dc, pool, asic_id))
		return &pool->base;

	BREAK_TO_DEBUGGER();
	return NULL;
}