spi-s3c64xx.c 37.4 KB
Newer Older
Grant Likely's avatar
Grant Likely committed
1
/*
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
 * Copyright (C) 2009 Samsung Electronics Ltd.
 *	Jaswinder Singh <jassi.brar@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/init.h>
#include <linux/module.h>
18
#include <linux/interrupt.h>
19 20 21
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/dma-mapping.h>
22
#include <linux/dmaengine.h>
23
#include <linux/platform_device.h>
24
#include <linux/pm_runtime.h>
25
#include <linux/spi/spi.h>
26
#include <linux/gpio.h>
27 28
#include <linux/of.h>
#include <linux/of_gpio.h>
29

30
#include <linux/platform_data/spi-s3c64xx.h>
31

32
#define MAX_SPI_PORTS		6
33
#define S3C64XX_SPI_QUIRK_POLL		(1 << 0)
34
#define S3C64XX_SPI_QUIRK_CS_AUTO	(1 << 1)
35
#define AUTOSUSPEND_TIMEOUT	2000
36

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
/* Registers and bit-fields */

#define S3C64XX_SPI_CH_CFG		0x00
#define S3C64XX_SPI_CLK_CFG		0x04
#define S3C64XX_SPI_MODE_CFG	0x08
#define S3C64XX_SPI_SLAVE_SEL	0x0C
#define S3C64XX_SPI_INT_EN		0x10
#define S3C64XX_SPI_STATUS		0x14
#define S3C64XX_SPI_TX_DATA		0x18
#define S3C64XX_SPI_RX_DATA		0x1C
#define S3C64XX_SPI_PACKET_CNT	0x20
#define S3C64XX_SPI_PENDING_CLR	0x24
#define S3C64XX_SPI_SWAP_CFG	0x28
#define S3C64XX_SPI_FB_CLK		0x2C

#define S3C64XX_SPI_CH_HS_EN		(1<<6)	/* High Speed Enable */
#define S3C64XX_SPI_CH_SW_RST		(1<<5)
#define S3C64XX_SPI_CH_SLAVE		(1<<4)
#define S3C64XX_SPI_CPOL_L		(1<<3)
#define S3C64XX_SPI_CPHA_B		(1<<2)
#define S3C64XX_SPI_CH_RXCH_ON		(1<<1)
#define S3C64XX_SPI_CH_TXCH_ON		(1<<0)

#define S3C64XX_SPI_CLKSEL_SRCMSK	(3<<9)
#define S3C64XX_SPI_CLKSEL_SRCSHFT	9
#define S3C64XX_SPI_ENCLK_ENABLE	(1<<8)
63
#define S3C64XX_SPI_PSR_MASK		0xff
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

#define S3C64XX_SPI_MODE_CH_TSZ_BYTE		(0<<29)
#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD	(1<<29)
#define S3C64XX_SPI_MODE_CH_TSZ_WORD		(2<<29)
#define S3C64XX_SPI_MODE_CH_TSZ_MASK		(3<<29)
#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE		(0<<17)
#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD	(1<<17)
#define S3C64XX_SPI_MODE_BUS_TSZ_WORD		(2<<17)
#define S3C64XX_SPI_MODE_BUS_TSZ_MASK		(3<<17)
#define S3C64XX_SPI_MODE_RXDMA_ON		(1<<2)
#define S3C64XX_SPI_MODE_TXDMA_ON		(1<<1)
#define S3C64XX_SPI_MODE_4BURST			(1<<0)

#define S3C64XX_SPI_SLAVE_AUTO			(1<<1)
#define S3C64XX_SPI_SLAVE_SIG_INACT		(1<<0)
79
#define S3C64XX_SPI_SLAVE_NSC_CNT_2		(2<<4)
80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114

#define S3C64XX_SPI_INT_TRAILING_EN		(1<<6)
#define S3C64XX_SPI_INT_RX_OVERRUN_EN		(1<<5)
#define S3C64XX_SPI_INT_RX_UNDERRUN_EN		(1<<4)
#define S3C64XX_SPI_INT_TX_OVERRUN_EN		(1<<3)
#define S3C64XX_SPI_INT_TX_UNDERRUN_EN		(1<<2)
#define S3C64XX_SPI_INT_RX_FIFORDY_EN		(1<<1)
#define S3C64XX_SPI_INT_TX_FIFORDY_EN		(1<<0)

#define S3C64XX_SPI_ST_RX_OVERRUN_ERR		(1<<5)
#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR	(1<<4)
#define S3C64XX_SPI_ST_TX_OVERRUN_ERR		(1<<3)
#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR	(1<<2)
#define S3C64XX_SPI_ST_RX_FIFORDY		(1<<1)
#define S3C64XX_SPI_ST_TX_FIFORDY		(1<<0)

#define S3C64XX_SPI_PACKET_CNT_EN		(1<<16)

#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR		(1<<4)
#define S3C64XX_SPI_PND_TX_OVERRUN_CLR		(1<<3)
#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR		(1<<2)
#define S3C64XX_SPI_PND_RX_OVERRUN_CLR		(1<<1)
#define S3C64XX_SPI_PND_TRAILING_CLR		(1<<0)

#define S3C64XX_SPI_SWAP_RX_HALF_WORD		(1<<7)
#define S3C64XX_SPI_SWAP_RX_BYTE		(1<<6)
#define S3C64XX_SPI_SWAP_RX_BIT			(1<<5)
#define S3C64XX_SPI_SWAP_RX_EN			(1<<4)
#define S3C64XX_SPI_SWAP_TX_HALF_WORD		(1<<3)
#define S3C64XX_SPI_SWAP_TX_BYTE		(1<<2)
#define S3C64XX_SPI_SWAP_TX_BIT			(1<<1)
#define S3C64XX_SPI_SWAP_TX_EN			(1<<0)

#define S3C64XX_SPI_FBCLK_MSK		(3<<0)

115 116 117 118 119 120
#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
				(1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
					FIFO_LVL_MASK(i))
121 122 123 124 125 126 127

#define S3C64XX_SPI_MAX_TRAILCNT	0x3ff
#define S3C64XX_SPI_TRAILCNT_OFF	19

#define S3C64XX_SPI_TRAILCNT		S3C64XX_SPI_MAX_TRAILCNT

#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
128
#define is_polling(x)	(x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
129 130 131 132

#define RXBUSY    (1<<2)
#define TXBUSY    (1<<3)

133
struct s3c64xx_spi_dma_data {
134
	struct dma_chan *ch;
135
	enum dma_transfer_direction direction;
136 137
};

138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155
/**
 * struct s3c64xx_spi_info - SPI Controller hardware info
 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 * @clk_from_cmu: True, if the controller does not include a clock mux and
 *	prescaler unit.
 *
 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 * differ in some aspects such as the size of the fifo and spi bus clock
 * setup. Such differences are specified to the driver using this structure
 * which is provided as driver data to the driver.
 */
struct s3c64xx_spi_port_config {
	int	fifo_lvl_mask[MAX_SPI_PORTS];
	int	rx_lvl_offset;
	int	tx_st_done;
156
	int	quirks;
157 158 159 160
	bool	high_speed;
	bool	clk_from_cmu;
};

161 162 163
/**
 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 * @clk: Pointer to the spi clock.
164
 * @src_clk: Pointer to the clock used to generate SPI signals.
165 166 167 168 169 170 171 172 173
 * @master: Pointer to the SPI Protocol master.
 * @cntrlr_info: Platform specific data for the controller this driver manages.
 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 * @lock: Controller specific lock.
 * @state: Set of FLAGS to indicate status.
 * @rx_dmach: Controller's DMA channel for Rx.
 * @tx_dmach: Controller's DMA channel for Tx.
 * @sfr_start: BUS address of SPI controller regs.
 * @regs: Pointer to ioremap'ed controller registers.
174
 * @irq: interrupt
175 176 177 178 179 180 181 182
 * @xfer_completion: To indicate completion of xfer task.
 * @cur_mode: Stores the active configuration of the controller.
 * @cur_bpw: Stores the active bits per word settings.
 * @cur_speed: Stores the active xfer clock speed.
 */
struct s3c64xx_spi_driver_data {
	void __iomem                    *regs;
	struct clk                      *clk;
183
	struct clk                      *src_clk;
184 185
	struct platform_device          *pdev;
	struct spi_master               *master;
186
	struct s3c64xx_spi_info  *cntrlr_info;
187 188 189 190 191 192 193
	struct spi_device               *tgl_spi;
	spinlock_t                      lock;
	unsigned long                   sfr_start;
	struct completion               xfer_completion;
	unsigned                        state;
	unsigned                        cur_mode, cur_bpw;
	unsigned                        cur_speed;
194 195
	struct s3c64xx_spi_dma_data	rx_dma;
	struct s3c64xx_spi_dma_data	tx_dma;
196 197
	struct s3c64xx_spi_port_config	*port_conf;
	unsigned int			port_id;
198 199 200 201 202 203 204 205 206 207
};

static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
{
	void __iomem *regs = sdd->regs;
	unsigned long loops;
	u32 val;

	writel(0, regs + S3C64XX_SPI_PACKET_CNT);

208 209 210 211
	val = readl(regs + S3C64XX_SPI_CH_CFG);
	val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
	writel(val, regs + S3C64XX_SPI_CH_CFG);

212 213 214 215 216 217 218 219 220
	val = readl(regs + S3C64XX_SPI_CH_CFG);
	val |= S3C64XX_SPI_CH_SW_RST;
	val &= ~S3C64XX_SPI_CH_HS_EN;
	writel(val, regs + S3C64XX_SPI_CH_CFG);

	/* Flush TxFIFO*/
	loops = msecs_to_loops(1);
	do {
		val = readl(regs + S3C64XX_SPI_STATUS);
221
	} while (TX_FIFO_LVL(val, sdd) && loops--);
222

223 224 225
	if (loops == 0)
		dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");

226 227 228 229
	/* Flush RxFIFO*/
	loops = msecs_to_loops(1);
	do {
		val = readl(regs + S3C64XX_SPI_STATUS);
230
		if (RX_FIFO_LVL(val, sdd))
231 232 233 234 235
			readl(regs + S3C64XX_SPI_RX_DATA);
		else
			break;
	} while (loops--);

236 237 238
	if (loops == 0)
		dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");

239 240 241 242 243 244 245 246 247
	val = readl(regs + S3C64XX_SPI_CH_CFG);
	val &= ~S3C64XX_SPI_CH_SW_RST;
	writel(val, regs + S3C64XX_SPI_CH_CFG);

	val = readl(regs + S3C64XX_SPI_MODE_CFG);
	val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
	writel(val, regs + S3C64XX_SPI_MODE_CFG);
}

248
static void s3c64xx_spi_dmacb(void *data)
249
{
250 251
	struct s3c64xx_spi_driver_data *sdd;
	struct s3c64xx_spi_dma_data *dma = data;
252 253
	unsigned long flags;

254
	if (dma->direction == DMA_DEV_TO_MEM)
255 256 257 258 259 260
		sdd = container_of(data,
			struct s3c64xx_spi_driver_data, rx_dma);
	else
		sdd = container_of(data,
			struct s3c64xx_spi_driver_data, tx_dma);

261 262
	spin_lock_irqsave(&sdd->lock, flags);

263
	if (dma->direction == DMA_DEV_TO_MEM) {
264 265 266 267 268 269 270 271
		sdd->state &= ~RXBUSY;
		if (!(sdd->state & TXBUSY))
			complete(&sdd->xfer_completion);
	} else {
		sdd->state &= ~TXBUSY;
		if (!(sdd->state & RXBUSY))
			complete(&sdd->xfer_completion);
	}
272 273 274 275

	spin_unlock_irqrestore(&sdd->lock, flags);
}

276
static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
277
			struct sg_table *sgt)
278 279 280 281 282
{
	struct s3c64xx_spi_driver_data *sdd;
	struct dma_slave_config config;
	struct dma_async_tx_descriptor *desc;

283 284
	memset(&config, 0, sizeof(config));

285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302
	if (dma->direction == DMA_DEV_TO_MEM) {
		sdd = container_of((void *)dma,
			struct s3c64xx_spi_driver_data, rx_dma);
		config.direction = dma->direction;
		config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
		config.src_addr_width = sdd->cur_bpw / 8;
		config.src_maxburst = 1;
		dmaengine_slave_config(dma->ch, &config);
	} else {
		sdd = container_of((void *)dma,
			struct s3c64xx_spi_driver_data, tx_dma);
		config.direction = dma->direction;
		config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
		config.dst_addr_width = sdd->cur_bpw / 8;
		config.dst_maxburst = 1;
		dmaengine_slave_config(dma->ch, &config);
	}

303 304
	desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
				       dma->direction, DMA_PREP_INTERRUPT);
305 306 307 308 309 310 311 312

	desc->callback = s3c64xx_spi_dmacb;
	desc->callback_param = dma;

	dmaengine_submit(desc);
	dma_async_issue_pending(dma->ch);
}

313 314 315 316 317
static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
{
	struct s3c64xx_spi_driver_data *sdd =
					spi_master_get_devdata(spi->master);

318 319 320
	if (sdd->cntrlr_info->no_cs)
		return;

321 322 323 324 325 326 327 328 329 330 331 332
	if (enable) {
		if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
			writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
		} else {
			u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);

			ssel |= (S3C64XX_SPI_SLAVE_AUTO |
						S3C64XX_SPI_SLAVE_NSC_CNT_2);
			writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
		}
	} else {
		if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
333 334
			writel(S3C64XX_SPI_SLAVE_SIG_INACT,
			       sdd->regs + S3C64XX_SPI_SLAVE_SEL);
335 336 337
	}
}

338 339 340 341 342 343 344
static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
{
	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
	dma_filter_fn filter = sdd->cntrlr_info->filter;
	struct device *dev = &sdd->pdev->dev;
	dma_cap_mask_t mask;

345 346 347 348 349 350 351 352 353 354 355 356
	if (is_polling(sdd))
		return 0;

	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

	/* Acquire DMA channels */
	sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
			   sdd->cntrlr_info->dma_rx, dev, "rx");
	if (!sdd->rx_dma.ch) {
		dev_err(dev, "Failed to get RX DMA channel\n");
		return -EBUSY;
357
	}
358
	spi->dma_rx = sdd->rx_dma.ch;
359

360 361 362 363 364 365 366 367
	sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
			   sdd->cntrlr_info->dma_tx, dev, "tx");
	if (!sdd->tx_dma.ch) {
		dev_err(dev, "Failed to get TX DMA channel\n");
		dma_release_channel(sdd->rx_dma.ch);
		return -EBUSY;
	}
	spi->dma_tx = sdd->tx_dma.ch;
368

369
	return 0;
370 371 372 373 374 375 376
}

static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
{
	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);

	/* Free DMA channels */
377 378 379 380
	if (!is_polling(sdd)) {
		dma_release_channel(sdd->rx_dma.ch);
		dma_release_channel(sdd->tx_dma.ch);
	}
381 382 383 384

	return 0;
}

385 386 387 388 389 390 391 392 393
static bool s3c64xx_spi_can_dma(struct spi_master *master,
				struct spi_device *spi,
				struct spi_transfer *xfer)
{
	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);

	return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
}

394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424
static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
				struct spi_device *spi,
				struct spi_transfer *xfer, int dma_mode)
{
	void __iomem *regs = sdd->regs;
	u32 modecfg, chcfg;

	modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
	modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);

	chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
	chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;

	if (dma_mode) {
		chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
	} else {
		/* Always shift in data in FIFO, even if xfer is Tx only,
		 * this helps setting PCKT_CNT value for generating clocks
		 * as exactly needed.
		 */
		chcfg |= S3C64XX_SPI_CH_RXCH_ON;
		writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
					| S3C64XX_SPI_PACKET_CNT_EN,
					regs + S3C64XX_SPI_PACKET_CNT);
	}

	if (xfer->tx_buf != NULL) {
		sdd->state |= TXBUSY;
		chcfg |= S3C64XX_SPI_CH_TXCH_ON;
		if (dma_mode) {
			modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
425
			prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
426
		} else {
427 428 429 430 431 432 433 434 435 436 437 438 439 440
			switch (sdd->cur_bpw) {
			case 32:
				iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
					xfer->tx_buf, xfer->len / 4);
				break;
			case 16:
				iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
					xfer->tx_buf, xfer->len / 2);
				break;
			default:
				iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
					xfer->tx_buf, xfer->len);
				break;
			}
441 442 443 444 445 446
		}
	}

	if (xfer->rx_buf != NULL) {
		sdd->state |= RXBUSY;

447
		if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
448 449 450 451 452 453 454 455 456
					&& !(sdd->cur_mode & SPI_CPHA))
			chcfg |= S3C64XX_SPI_CH_HS_EN;

		if (dma_mode) {
			modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
			chcfg |= S3C64XX_SPI_CH_RXCH_ON;
			writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
					| S3C64XX_SPI_PACKET_CNT_EN,
					regs + S3C64XX_SPI_PACKET_CNT);
457
			prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
458 459 460 461 462 463 464
		}
	}

	writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
	writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
}

465
static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483
					int timeout_ms)
{
	void __iomem *regs = sdd->regs;
	unsigned long val = 1;
	u32 status;

	/* max fifo depth available */
	u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;

	if (timeout_ms)
		val = msecs_to_loops(timeout_ms);

	do {
		status = readl(regs + S3C64XX_SPI_STATUS);
	} while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);

	/* return the actual received data length */
	return RX_FIFO_LVL(status, sdd);
484 485
}

486 487
static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
			struct spi_transfer *xfer)
488 489 490
{
	void __iomem *regs = sdd->regs;
	unsigned long val;
491
	u32 status;
492 493 494 495
	int ms;

	/* millisecs to xfer 'len' bytes @ 'cur_speed' */
	ms = xfer->len * 8 * 1000 / sdd->cur_speed;
496
	ms += 10; /* some tolerance */
497

498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516
	val = msecs_to_jiffies(ms) + 10;
	val = wait_for_completion_timeout(&sdd->xfer_completion, val);

	/*
	 * If the previous xfer was completed within timeout, then
	 * proceed further else return -EIO.
	 * DmaTx returns after simply writing data in the FIFO,
	 * w/o waiting for real transmission on the bus to finish.
	 * DmaRx returns only after Dma read data from FIFO which
	 * needs bus transmission to finish, so we don't worry if
	 * Xfer involved Rx(with or without Tx).
	 */
	if (val && !xfer->rx_buf) {
		val = msecs_to_loops(10);
		status = readl(regs + S3C64XX_SPI_STATUS);
		while ((TX_FIFO_LVL(status, sdd)
			|| !S3C64XX_SPI_ST_TX_DONE(status, sdd))
		       && --val) {
			cpu_relax();
517
			status = readl(regs + S3C64XX_SPI_STATUS);
518 519
		}

520 521
	}

522 523 524
	/* If timed out while checking rx/tx status return error */
	if (!val)
		return -EIO;
525

526 527
	return 0;
}
528

529 530 531 532 533 534 535 536 537 538
static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
			struct spi_transfer *xfer)
{
	void __iomem *regs = sdd->regs;
	unsigned long val;
	u32 status;
	int loops;
	u32 cpy_len;
	u8 *buf;
	int ms;
539

540 541 542
	/* millisecs to xfer 'len' bytes @ 'cur_speed' */
	ms = xfer->len * 8 * 1000 / sdd->cur_speed;
	ms += 10; /* some tolerance */
543

544 545 546 547
	val = msecs_to_loops(ms);
	do {
		status = readl(regs + S3C64XX_SPI_STATUS);
	} while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
548

549 550 551 552 553

	/* If it was only Tx */
	if (!xfer->rx_buf) {
		sdd->state &= ~TXBUSY;
		return 0;
554 555
	}

556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589
	/*
	 * If the receive length is bigger than the controller fifo
	 * size, calculate the loops and read the fifo as many times.
	 * loops = length / max fifo size (calculated by using the
	 * fifo mask).
	 * For any size less than the fifo size the below code is
	 * executed atleast once.
	 */
	loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
	buf = xfer->rx_buf;
	do {
		/* wait for data to be received in the fifo */
		cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
						       (loops ? ms : 0));

		switch (sdd->cur_bpw) {
		case 32:
			ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
				     buf, cpy_len / 4);
			break;
		case 16:
			ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
				     buf, cpy_len / 2);
			break;
		default:
			ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
				    buf, cpy_len);
			break;
		}

		buf = buf + cpy_len;
	} while (loops--);
	sdd->state &= ~RXBUSY;

590 591 592 593 594 595 596 597 598
	return 0;
}

static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
{
	void __iomem *regs = sdd->regs;
	u32 val;

	/* Disable Clock */
599
	if (sdd->port_conf->clk_from_cmu) {
600
		clk_disable_unprepare(sdd->src_clk);
601 602 603 604 605
	} else {
		val = readl(regs + S3C64XX_SPI_CLK_CFG);
		val &= ~S3C64XX_SPI_ENCLK_ENABLE;
		writel(val, regs + S3C64XX_SPI_CLK_CFG);
	}
606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628

	/* Set Polarity and Phase */
	val = readl(regs + S3C64XX_SPI_CH_CFG);
	val &= ~(S3C64XX_SPI_CH_SLAVE |
			S3C64XX_SPI_CPOL_L |
			S3C64XX_SPI_CPHA_B);

	if (sdd->cur_mode & SPI_CPOL)
		val |= S3C64XX_SPI_CPOL_L;

	if (sdd->cur_mode & SPI_CPHA)
		val |= S3C64XX_SPI_CPHA_B;

	writel(val, regs + S3C64XX_SPI_CH_CFG);

	/* Set Channel & DMA Mode */
	val = readl(regs + S3C64XX_SPI_MODE_CFG);
	val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
			| S3C64XX_SPI_MODE_CH_TSZ_MASK);

	switch (sdd->cur_bpw) {
	case 32:
		val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
629
		val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
630 631 632
		break;
	case 16:
		val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
633
		val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
634 635 636
		break;
	default:
		val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
637
		val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
638 639 640 641 642
		break;
	}

	writel(val, regs + S3C64XX_SPI_MODE_CFG);

643
	if (sdd->port_conf->clk_from_cmu) {
644 645 646 647
		/* Configure Clock */
		/* There is half-multiplier before the SPI */
		clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
		/* Enable Clock */
648
		clk_prepare_enable(sdd->src_clk);
649 650 651 652 653 654 655 656 657 658 659 660 661
	} else {
		/* Configure Clock */
		val = readl(regs + S3C64XX_SPI_CLK_CFG);
		val &= ~S3C64XX_SPI_PSR_MASK;
		val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
				& S3C64XX_SPI_PSR_MASK);
		writel(val, regs + S3C64XX_SPI_CLK_CFG);

		/* Enable Clock */
		val = readl(regs + S3C64XX_SPI_CLK_CFG);
		val |= S3C64XX_SPI_ENCLK_ENABLE;
		writel(val, regs + S3C64XX_SPI_CLK_CFG);
	}
662 663 664 665
}

#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)

666 667
static int s3c64xx_spi_prepare_message(struct spi_master *master,
				       struct spi_message *msg)
668
{
669
	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
670 671 672 673 674 675
	struct spi_device *spi = msg->spi;
	struct s3c64xx_spi_csinfo *cs = spi->controller_data;

	/* Configure feedback delay */
	writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);

676 677
	return 0;
}
678

679 680 681
static int s3c64xx_spi_transfer_one(struct spi_master *master,
				    struct spi_device *spi,
				    struct spi_transfer *xfer)
682 683
{
	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
684
	int status;
685 686
	u32 speed;
	u8 bpw;
687 688
	unsigned long flags;
	int use_dma;
689

690
	reinit_completion(&sdd->xfer_completion);
691

692 693
	/* Only BPW and Speed may change across transfers */
	bpw = xfer->bits_per_word;
694
	speed = xfer->speed_hz;
695

696 697 698
	if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
		sdd->cur_bpw = bpw;
		sdd->cur_speed = speed;
699
		sdd->cur_mode = spi->mode;
700 701
		s3c64xx_spi_config(sdd);
	}
702

703 704 705 706 707 708
	/* Polling method for xfers not bigger than FIFO capacity */
	use_dma = 0;
	if (!is_polling(sdd) &&
	    (sdd->rx_dma.ch && sdd->tx_dma.ch &&
	     (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
		use_dma = 1;
709

710
	spin_lock_irqsave(&sdd->lock, flags);
711

712 713 714
	/* Pending only which is to be done */
	sdd->state &= ~RXBUSY;
	sdd->state &= ~TXBUSY;
715

716
	enable_datapath(sdd, spi, xfer, use_dma);
717

718
	/* Start the signals */
719
	s3c64xx_spi_set_cs(spi, true);
720

721
	spin_unlock_irqrestore(&sdd->lock, flags);
722

723 724 725 726
	if (use_dma)
		status = wait_for_dma(sdd, xfer);
	else
		status = wait_for_pio(sdd, xfer);
727 728 729 730 731 732 733 734 735 736 737

	if (status) {
		dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
			xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
			(sdd->state & RXBUSY) ? 'f' : 'p',
			(sdd->state & TXBUSY) ? 'f' : 'p',
			xfer->len);

		if (use_dma) {
			if (xfer->tx_buf != NULL
			    && (sdd->state & TXBUSY))
738
				dmaengine_terminate_all(sdd->tx_dma.ch);
739 740
			if (xfer->rx_buf != NULL
			    && (sdd->state & RXBUSY))
741
				dmaengine_terminate_all(sdd->rx_dma.ch);
742
		}
743
	} else {
744 745 746
		flush_fifo(sdd);
	}

747
	return status;
748 749
}

750 751 752 753
static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
				struct spi_device *spi)
{
	struct s3c64xx_spi_csinfo *cs;
754
	struct device_node *slave_np, *data_np = NULL;
755 756 757 758 759 760 761 762
	u32 fb_delay = 0;

	slave_np = spi->dev.of_node;
	if (!slave_np) {
		dev_err(&spi->dev, "device node not found\n");
		return ERR_PTR(-EINVAL);
	}

763
	data_np = of_get_child_by_name(slave_np, "controller-data");
764 765 766 767 768 769 770
	if (!data_np) {
		dev_err(&spi->dev, "child node 'controller-data' not found\n");
		return ERR_PTR(-EINVAL);
	}

	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
	if (!cs) {
771
		of_node_put(data_np);
772 773 774 775 776
		return ERR_PTR(-ENOMEM);
	}

	of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
	cs->fb_delay = fb_delay;
777
	of_node_put(data_np);
778 779 780
	return cs;
}

781 782 783 784 785 786 787 788 789 790
/*
 * Here we only check the validity of requested configuration
 * and save the configuration in a local data-structure.
 * The controller is actually configured only just before we
 * get a message to transfer.
 */
static int s3c64xx_spi_setup(struct spi_device *spi)
{
	struct s3c64xx_spi_csinfo *cs = spi->controller_data;
	struct s3c64xx_spi_driver_data *sdd;
791
	struct s3c64xx_spi_info *sci;
792
	int err;
793

794
	sdd = spi_master_get_devdata(spi->master);
795
	if (spi->dev.of_node) {
796
		cs = s3c64xx_get_slave_ctrldata(spi);
797
		spi->controller_data = cs;
798 799 800 801 802 803 804
	} else if (cs) {
		/* On non-DT platforms the SPI core will set spi->cs_gpio
		 * to -ENOENT. The GPIO pin used to drive the chip select
		 * is defined by using platform data so spi->cs_gpio value
		 * has to be override to have the proper GPIO pin number.
		 */
		spi->cs_gpio = cs->line;
805 806 807
	}

	if (IS_ERR_OR_NULL(cs)) {
808 809 810 811
		dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
		return -ENODEV;
	}

812
	if (!spi_get_ctldata(spi)) {
813 814 815 816 817 818 819 820 821
		if (gpio_is_valid(spi->cs_gpio)) {
			err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
					       dev_name(&spi->dev));
			if (err) {
				dev_err(&spi->dev,
					"Failed to get /CS gpio [%d]: %d\n",
					spi->cs_gpio, err);
				goto err_gpio_req;
			}
822 823
		}

824
		spi_set_ctldata(spi, cs);
825 826 827 828
	}

	sci = sdd->cntrlr_info;

829 830
	pm_runtime_get_sync(&sdd->pdev->dev);

831
	/* Check if we can provide the requested rate */
832
	if (!sdd->port_conf->clk_from_cmu) {
833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854
		u32 psr, speed;

		/* Max possible */
		speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);

		if (spi->max_speed_hz > speed)
			spi->max_speed_hz = speed;

		psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
		psr &= S3C64XX_SPI_PSR_MASK;
		if (psr == S3C64XX_SPI_PSR_MASK)
			psr--;

		speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
		if (spi->max_speed_hz < speed) {
			if (psr+1 < S3C64XX_SPI_PSR_MASK) {
				psr++;
			} else {
				err = -EINVAL;
				goto setup_exit;
			}
		}
855

856
		speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
857
		if (spi->max_speed_hz >= speed) {
858
			spi->max_speed_hz = speed;
859
		} else {
860 861
			dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
				spi->max_speed_hz);
862
			err = -EINVAL;
863 864
			goto setup_exit;
		}
865 866
	}

867 868
	pm_runtime_mark_last_busy(&sdd->pdev->dev);
	pm_runtime_put_autosuspend(&sdd->pdev->dev);
869 870
	s3c64xx_spi_set_cs(spi, false);

871
	return 0;
872

873
setup_exit:
874 875
	pm_runtime_mark_last_busy(&sdd->pdev->dev);
	pm_runtime_put_autosuspend(&sdd->pdev->dev);
876
	/* setup() returns with device de-selected */
877
	s3c64xx_spi_set_cs(spi, false);
878

879 880
	if (gpio_is_valid(spi->cs_gpio))
		gpio_free(spi->cs_gpio);
881 882 883
	spi_set_ctldata(spi, NULL);

err_gpio_req:
884 885
	if (spi->dev.of_node)
		kfree(cs);
886

887 888 889
	return err;
}

890 891 892 893
static void s3c64xx_spi_cleanup(struct spi_device *spi)
{
	struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);

894
	if (gpio_is_valid(spi->cs_gpio)) {
895
		gpio_free(spi->cs_gpio);
896 897
		if (spi->dev.of_node)
			kfree(cs);
898 899 900 901 902 903 904 905
		else {
			/* On non-DT platforms, the SPI core sets
			 * spi->cs_gpio to -ENOENT and .setup()
			 * overrides it with the GPIO pin value
			 * passed using platform data.
			 */
			spi->cs_gpio = -ENOENT;
		}
906
	}
907

908 909 910
	spi_set_ctldata(spi, NULL);
}

911 912 913 914
static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
{
	struct s3c64xx_spi_driver_data *sdd = data;
	struct spi_master *spi = sdd->master;
915
	unsigned int val, clr = 0;
916

917
	val = readl(sdd->regs + S3C64XX_SPI_STATUS);
918

919 920
	if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
		clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
921
		dev_err(&spi->dev, "RX overrun\n");
922 923 924
	}
	if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
		clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
925
		dev_err(&spi->dev, "RX underrun\n");
926 927 928
	}
	if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
		clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
929
		dev_err(&spi->dev, "TX overrun\n");
930 931 932
	}
	if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
		clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
933
		dev_err(&spi->dev, "TX underrun\n");
934 935 936 937 938
	}

	/* Clear the pending irq by setting and then clearing it */
	writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
	writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
939 940 941 942

	return IRQ_HANDLED;
}

943 944
static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
{
945
	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
946 947 948 949 950
	void __iomem *regs = sdd->regs;
	unsigned int val;

	sdd->cur_speed = 0;

951 952 953
	if (sci->no_cs)
		writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
	else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
954
		writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
955 956 957 958

	/* Disable Interrupts - we use Polling if not DMA mode */
	writel(0, regs + S3C64XX_SPI_INT_EN);

959
	if (!sdd->port_conf->clk_from_cmu)
960
		writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
961 962 963 964
				regs + S3C64XX_SPI_CLK_CFG);
	writel(0, regs + S3C64XX_SPI_MODE_CFG);
	writel(0, regs + S3C64XX_SPI_PACKET_CNT);

965 966 967 968 969 970 971
	/* Clear any irq pending bits, should set and clear the bits */
	val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
		S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
		S3C64XX_SPI_PND_TX_OVERRUN_CLR |
		S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
	writel(val, regs + S3C64XX_SPI_PENDING_CLR);
	writel(0, regs + S3C64XX_SPI_PENDING_CLR);
972 973 974 975 976 977 978 979 980 981 982 983

	writel(0, regs + S3C64XX_SPI_SWAP_CFG);

	val = readl(regs + S3C64XX_SPI_MODE_CFG);
	val &= ~S3C64XX_SPI_MODE_4BURST;
	val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
	val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
	writel(val, regs + S3C64XX_SPI_MODE_CFG);

	flush_fifo(sdd);
}

984
#ifdef CONFIG_OF
985
static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
986 987 988 989 990
{
	struct s3c64xx_spi_info *sci;
	u32 temp;

	sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
991
	if (!sci)
992 993 994
		return ERR_PTR(-ENOMEM);

	if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
995
		dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
996 997 998 999 1000 1001
		sci->src_clk_nr = 0;
	} else {
		sci->src_clk_nr = temp;
	}

	if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1002
		dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1003 1004 1005 1006 1007
		sci->num_cs = 1;
	} else {
		sci->num_cs = temp;
	}

1008 1009
	sci->no_cs = of_property_read_bool(dev->of_node, "broken-cs");

1010 1011 1012 1013 1014
	return sci;
}
#else
static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
{
Jingoo Han's avatar
Jingoo Han committed
1015
	return dev_get_platdata(dev);
1016 1017 1018 1019 1020
}
#endif

static const struct of_device_id s3c64xx_spi_dt_match[];

1021 1022 1023
static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
						struct platform_device *pdev)
{
1024 1025 1026 1027 1028 1029 1030
#ifdef CONFIG_OF
	if (pdev->dev.of_node) {
		const struct of_device_id *match;
		match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
		return (struct s3c64xx_spi_port_config *)match->data;
	}
#endif
1031 1032 1033 1034
	return (struct s3c64xx_spi_port_config *)
			 platform_get_device_id(pdev)->driver_data;
}

1035
static int s3c64xx_spi_probe(struct platform_device *pdev)
1036
{
1037
	struct resource	*mem_res;
1038
	struct s3c64xx_spi_driver_data *sdd;
Jingoo Han's avatar
Jingoo Han committed
1039
	struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1040
	struct spi_master *master;
1041
	int ret, irq;
1042
	char clk_name[16];
1043

1044 1045 1046 1047
	if (!sci && pdev->dev.of_node) {
		sci = s3c64xx_spi_parse_dt(&pdev->dev);
		if (IS_ERR(sci))
			return PTR_ERR(sci);
1048 1049
	}

1050
	if (!sci) {
1051 1052 1053 1054 1055 1056 1057 1058 1059 1060
		dev_err(&pdev->dev, "platform_data missing!\n");
		return -ENODEV;
	}

	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (mem_res == NULL) {
		dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
		return -ENXIO;
	}

1061 1062 1063 1064 1065 1066
	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
		return irq;
	}

1067 1068 1069 1070 1071 1072 1073 1074 1075 1076
	master = spi_alloc_master(&pdev->dev,
				sizeof(struct s3c64xx_spi_driver_data));
	if (master == NULL) {
		dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
		return -ENOMEM;
	}

	platform_set_drvdata(pdev, master);

	sdd = spi_master_get_devdata(master);
1077
	sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1078 1079 1080 1081
	sdd->master = master;
	sdd->cntrlr_info = sci;
	sdd->pdev = pdev;
	sdd->sfr_start = mem_res->start;
1082 1083 1084
	if (pdev->dev.of_node) {
		ret = of_alias_get_id(pdev->dev.of_node, "spi");
		if (ret < 0) {
1085 1086
			dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
				ret);
1087 1088 1089 1090 1091 1092
			goto err0;
		}
		sdd->port_id = ret;
	} else {
		sdd->port_id = pdev->id;
	}
1093 1094 1095

	sdd->cur_bpw = 8;

1096 1097 1098
	if (!sdd->pdev->dev.of_node && (!sci->dma_tx || !sci->dma_rx)) {
		dev_warn(&pdev->dev, "Unable to get SPI tx/rx DMA data. Switching to poll mode\n");
		sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1099
	}
1100

1101 1102
	sdd->tx_dma.direction = DMA_MEM_TO_DEV;
	sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1103 1104

	master->dev.of_node = pdev->dev.of_node;
1105
	master->bus_num = sdd->port_id;
1106
	master->setup = s3c64xx_spi_setup;
1107
	master->cleanup = s3c64xx_spi_cleanup;
1108
	master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1109
	master->prepare_message = s3c64xx_spi_prepare_message;
1110
	master->transfer_one = s3c64xx_spi_transfer_one;
1111
	master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1112 1113
	master->num_chipselect = sci->num_cs;
	master->dma_alignment = 8;
1114 1115
	master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
					SPI_BPW_MASK(8);
1116 1117
	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1118
	master->auto_runtime_pm = true;
1119 1120
	if (!is_polling(sdd))
		master->can_dma = s3c64xx_spi_can_dma;
1121

1122 1123 1124
	sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
	if (IS_ERR(sdd->regs)) {
		ret = PTR_ERR(sdd->regs);
1125
		goto err0;
1126 1127
	}

1128
	if (sci->cfg_gpio && sci->cfg_gpio()) {
1129 1130
		dev_err(&pdev->dev, "Unable to config gpio\n");
		ret = -EBUSY;
1131
		goto err0;
1132 1133 1134
	}

	/* Setup clocks */
1135
	sdd->clk = devm_clk_get(&pdev->dev, "spi");
1136 1137 1138
	if (IS_ERR(sdd->clk)) {
		dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
		ret = PTR_ERR(sdd->clk);
1139
		goto err0;
1140 1141
	}

1142
	if (clk_prepare_enable(sdd->clk)) {
1143 1144
		dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
		ret = -EBUSY;
1145
		goto err0;
1146 1147
	}

1148
	sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1149
	sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1150
	if (IS_ERR(sdd->src_clk)) {
1151
		dev_err(&pdev->dev,
1152
			"Unable to acquire clock '%s'\n", clk_name);
1153
		ret = PTR_ERR(sdd->src_clk);
1154
		goto err2;
1155 1156
	}

1157
	if (clk_prepare_enable(sdd->src_clk)) {
1158
		dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1159
		ret = -EBUSY;
1160
		goto err2;
1161 1162
	}

1163 1164 1165 1166 1167 1168
	pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

1169
	/* Setup Deufult Mode */
1170
	s3c64xx_spi_hwinit(sdd, sdd->port_id);
1171 1172 1173 1174

	spin_lock_init(&sdd->lock);
	init_completion(&sdd->xfer_completion);

1175 1176
	ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
				"spi-s3c64xx", sdd);
1177 1178 1179
	if (ret != 0) {
		dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
			irq, ret);
1180
		goto err3;
1181 1182 1183 1184 1185 1186
	}

	writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
	       S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
	       sdd->regs + S3C64XX_SPI_INT_EN);

1187 1188 1189
	ret = devm_spi_register_master(&pdev->dev, master);
	if (ret != 0) {
		dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1190
		goto err3;
1191 1192
	}

1193
	dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1194
					sdd->port_id, master->num_chipselect);
1195
	dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\tDMA=[Rx-%p, Tx-%p]\n",
1196
					mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1,
1197
					sci->dma_rx, sci->dma_tx);
1198

1199 1200 1201
	pm_runtime_mark_last_busy(&pdev->dev);
	pm_runtime_put_autosuspend(&pdev->dev);

1202 1203
	return 0;

1204 1205
err3:
	pm_runtime_put_noidle(&pdev->dev);
1206 1207
	pm_runtime_disable(&pdev->dev);
	pm_runtime_set_suspended(&pdev->dev);
1208

1209
	clk_disable_unprepare(sdd->src_clk);
1210
err2:
1211
	clk_disable_unprepare(sdd->clk);
1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222
err0:
	spi_master_put(master);

	return ret;
}

static int s3c64xx_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);

1223
	pm_runtime_get_sync(&pdev->dev);
1224

1225 1226
	writel(0, sdd->regs + S3C64XX_SPI_INT_EN);

1227
	clk_disable_unprepare(sdd->src_clk);
1228

1229
	clk_disable_unprepare(sdd->clk);
1230

1231 1232 1233 1234
	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	pm_runtime_set_suspended(&pdev->dev);

1235 1236 1237
	return 0;
}

1238
#ifdef CONFIG_PM_SLEEP
1239
static int s3c64xx_spi_suspend(struct device *dev)
1240
{
1241
	struct spi_master *master = dev_get_drvdata(dev);
1242 1243
	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);

1244 1245 1246
	int ret = spi_master_suspend(master);
	if (ret)
		return ret;
1247

1248 1249 1250
	ret = pm_runtime_force_suspend(dev);
	if (ret < 0)
		return ret;
1251 1252 1253 1254 1255 1256

	sdd->cur_speed = 0; /* Output Clock is stopped */

	return 0;
}

1257
static int s3c64xx_spi_resume(struct device *dev)
1258
{
1259
	struct spi_master *master = dev_get_drvdata(dev);
1260
	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1261
	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1262
	int ret;
1263

1264
	if (sci->cfg_gpio)
1265
		sci->cfg_gpio();
1266

1267 1268 1269
	ret = pm_runtime_force_resume(dev);
	if (ret < 0)
		return ret;
1270

1271
	s3c64xx_spi_hwinit(sdd, sdd->port_id);
1272

1273
	return spi_master_resume(master);
1274
}
1275
#endif /* CONFIG_PM_SLEEP */
1276

1277
#ifdef CONFIG_PM
1278 1279
static int s3c64xx_spi_runtime_suspend(struct device *dev)
{
1280
	struct spi_master *master = dev_get_drvdata(dev);
1281 1282
	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);

1283 1284
	clk_disable_unprepare(sdd->clk);
	clk_disable_unprepare(sdd->src_clk);
1285 1286 1287 1288 1289 1290

	return 0;
}

static int s3c64xx_spi_runtime_resume(struct device *dev)
{
1291
	struct spi_master *master = dev_get_drvdata(dev);
1292
	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1293
	int ret;
1294

1295 1296 1297 1298 1299 1300 1301 1302 1303
	ret = clk_prepare_enable(sdd->src_clk);
	if (ret != 0)
		return ret;

	ret = clk_prepare_enable(sdd->clk);
	if (ret != 0) {
		clk_disable_unprepare(sdd->src_clk);
		return ret;
	}
1304 1305 1306

	return 0;
}
1307
#endif /* CONFIG_PM */
1308

1309 1310
static const struct dev_pm_ops s3c64xx_spi_pm = {
	SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1311 1312
	SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
			   s3c64xx_spi_runtime_resume, NULL)
1313 1314
};

1315
static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1316 1317 1318 1319 1320 1321
	.fifo_lvl_mask	= { 0x7f },
	.rx_lvl_offset	= 13,
	.tx_st_done	= 21,
	.high_speed	= true,
};

1322
static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1323 1324 1325 1326 1327
	.fifo_lvl_mask	= { 0x7f, 0x7F },
	.rx_lvl_offset	= 13,
	.tx_st_done	= 21,
};

1328
static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1329 1330 1331 1332 1333 1334
	.fifo_lvl_mask	= { 0x1ff, 0x7F },
	.rx_lvl_offset	= 15,
	.tx_st_done	= 25,
	.high_speed	= true,
};

1335
static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1336 1337 1338 1339 1340 1341 1342
	.fifo_lvl_mask	= { 0x1ff, 0x7F, 0x7F },
	.rx_lvl_offset	= 15,
	.tx_st_done	= 25,
	.high_speed	= true,
	.clk_from_cmu	= true,
};

1343 1344 1345 1346 1347 1348 1349 1350 1351
static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
	.fifo_lvl_mask	= { 0x1ff },
	.rx_lvl_offset	= 15,
	.tx_st_done	= 25,
	.high_speed	= true,
	.clk_from_cmu	= true,
	.quirks		= S3C64XX_SPI_QUIRK_POLL,
};

1352 1353 1354 1355 1356 1357 1358 1359 1360
static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
	.fifo_lvl_mask	= { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
	.rx_lvl_offset	= 15,
	.tx_st_done	= 25,
	.high_speed	= true,
	.clk_from_cmu	= true,
	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,
};

1361
static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1362 1363 1364 1365 1366 1367 1368 1369 1370 1371
	{
		.name		= "s3c2443-spi",
		.driver_data	= (kernel_ulong_t)&s3c2443_spi_port_config,
	}, {
		.name		= "s3c6410-spi",
		.driver_data	= (kernel_ulong_t)&s3c6410_spi_port_config,
	},
	{ },
};

1372
static const struct of_device_id s3c64xx_spi_dt_match[] = {
1373 1374 1375 1376 1377 1378 1379 1380 1381
	{ .compatible = "samsung,s3c2443-spi",
			.data = (void *)&s3c2443_spi_port_config,
	},
	{ .compatible = "samsung,s3c6410-spi",
			.data = (void *)&s3c6410_spi_port_config,
	},
	{ .compatible = "samsung,s5pv210-spi",
			.data = (void *)&s5pv210_spi_port_config,
	},
1382 1383 1384
	{ .compatible = "samsung,exynos4210-spi",
			.data = (void *)&exynos4_spi_port_config,
	},
1385 1386 1387
	{ .compatible = "samsung,exynos5440-spi",
			.data = (void *)&exynos5440_spi_port_config,
	},
1388 1389 1390
	{ .compatible = "samsung,exynos7-spi",
			.data = (void *)&exynos7_spi_port_config,
	},
1391 1392 1393 1394
	{ },
};
MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);

1395 1396 1397
static struct platform_driver s3c64xx_spi_driver = {
	.driver = {
		.name	= "s3c64xx-spi",
1398
		.pm = &s3c64xx_spi_pm,
1399
		.of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1400
	},
1401
	.probe = s3c64xx_spi_probe,
1402
	.remove = s3c64xx_spi_remove,
1403
	.id_table = s3c64xx_spi_driver_ids,
1404 1405 1406
};
MODULE_ALIAS("platform:s3c64xx-spi");

1407
module_platform_driver(s3c64xx_spi_driver);
1408 1409 1410 1411

MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
MODULE_LICENSE("GPL");