dcn10_resource.c 37.1 KB
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/*
* Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dm_services.h"
#include "dc.h"

#include "resource.h"
#include "include/irq_service_interface.h"
#include "dcn10/dcn10_resource.h"

#include "dcn10/dcn10_ipp.h"
#include "dcn10/dcn10_mpc.h"
#include "irq/dcn10/irq_service_dcn10.h"
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#include "dcn10/dcn10_dpp.h"
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#include "dcn10/dcn10_timing_generator.h"
#include "dcn10/dcn10_hw_sequencer.h"
#include "dce110/dce110_hw_sequencer.h"
#include "dcn10/dcn10_opp.h"
#include "dce/dce_link_encoder.h"
#include "dce/dce_stream_encoder.h"
#include "dce/dce_clocks.h"
#include "dce/dce_clock_source.h"
#include "dce/dce_audio.h"
#include "dce/dce_hwseq.h"
#include "../virtual/virtual_stream_encoder.h"
#include "dce110/dce110_resource.h"
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#include "dce112/dce112_resource.h"
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#include "dcn10_hubp.h"
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#include "dcn10_hubbub.h"
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#include "soc15ip.h"
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#include "dcn/dcn_1_0_offset.h"
#include "dcn/dcn_1_0_sh_mask.h"
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#include "nbio/nbio_7_0_offset.h"
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#include "mmhub/mmhub_9_1_offset.h"
#include "mmhub/mmhub_9_1_sh_mask.h"
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#include "reg_helper.h"
#include "dce/dce_abm.h"
#include "dce/dce_dmcu.h"

#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f
	#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
	#define mmDP1_DP_DPHY_INTERNAL_CTRL		0x220f
	#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
	#define mmDP2_DP_DPHY_INTERNAL_CTRL		0x230f
	#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
	#define mmDP3_DP_DPHY_INTERNAL_CTRL		0x240f
	#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
	#define mmDP4_DP_DPHY_INTERNAL_CTRL		0x250f
	#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
	#define mmDP5_DP_DPHY_INTERNAL_CTRL		0x260f
	#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
	#define mmDP6_DP_DPHY_INTERNAL_CTRL		0x270f
	#define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
#endif


enum dcn10_clk_src_array_id {
	DCN10_CLK_SRC_PLL0,
	DCN10_CLK_SRC_PLL1,
	DCN10_CLK_SRC_PLL2,
	DCN10_CLK_SRC_PLL3,
	DCN10_CLK_SRC_TOTAL
};

/* begin *********************
 * macros to expend register list macro defined in HW object header file */

/* DCN */
#define BASE_INNER(seg) \
	DCE_BASE__INST0_SEG ## seg

#define BASE(seg) \
	BASE_INNER(seg)

#define SR(reg_name)\
		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
					mm ## reg_name

#define SRI(reg_name, block, id)\
	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
					mm ## block ## id ## _ ## reg_name


#define SRII(reg_name, block, id)\
	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
					mm ## block ## id ## _ ## reg_name

/* NBIO */
#define NBIO_BASE_INNER(seg) \
	NBIF_BASE__INST0_SEG ## seg

#define NBIO_BASE(seg) \
	NBIO_BASE_INNER(seg)

#define NBIO_SR(reg_name)\
		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) +  \
					mm ## reg_name

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/* MMHUB */
#define MMHUB_BASE_INNER(seg) \
	MMHUB_BASE__INST0_SEG ## seg
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#define MMHUB_BASE(seg) \
	MMHUB_BASE_INNER(seg)
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#define MMHUB_SR(reg_name)\
		.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
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					mm ## reg_name

/* macros to expend register list macro defined in HW object header file
 * end *********************/


static const struct dce_dmcu_registers dmcu_regs = {
		DMCU_DCN10_REG_LIST()
};

static const struct dce_dmcu_shift dmcu_shift = {
		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
};

static const struct dce_dmcu_mask dmcu_mask = {
		DMCU_MASK_SH_LIST_DCN10(_MASK)
};

static const struct dce_abm_registers abm_regs = {
		ABM_DCN10_REG_LIST(0)
};

static const struct dce_abm_shift abm_shift = {
		ABM_MASK_SH_LIST_DCN10(__SHIFT)
};

static const struct dce_abm_mask abm_mask = {
		ABM_MASK_SH_LIST_DCN10(_MASK)
};

#define stream_enc_regs(id)\
[id] = {\
	SE_DCN_REG_LIST(id),\
	.TMDS_CNTL = 0,\
	.AFMT_AVI_INFO0 = 0,\
	.AFMT_AVI_INFO1 = 0,\
	.AFMT_AVI_INFO2 = 0,\
	.AFMT_AVI_INFO3 = 0,\
}

static const struct dce110_stream_enc_registers stream_enc_regs[] = {
	stream_enc_regs(0),
	stream_enc_regs(1),
	stream_enc_regs(2),
	stream_enc_regs(3),
};

static const struct dce_stream_encoder_shift se_shift = {
		SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
};

static const struct dce_stream_encoder_mask se_mask = {
		SE_COMMON_MASK_SH_LIST_DCN10(_MASK),
		.AFMT_GENERIC0_UPDATE = 0,
		.AFMT_GENERIC2_UPDATE = 0,
		.DP_DYN_RANGE = 0,
		.DP_YCBCR_RANGE = 0,
		.HDMI_AVI_INFO_SEND = 0,
		.HDMI_AVI_INFO_CONT = 0,
		.HDMI_AVI_INFO_LINE = 0,
		.DP_SEC_AVI_ENABLE = 0,
		.AFMT_AVI_INFO_VERSION = 0
};

#define audio_regs(id)\
[id] = {\
		AUD_COMMON_REG_LIST(id)\
}

static const struct dce_audio_registers audio_regs[] = {
	audio_regs(0),
	audio_regs(1),
	audio_regs(2),
	audio_regs(3),
};

#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)

static const struct dce_audio_shift audio_shift = {
		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
};

static const struct dce_aduio_mask audio_mask = {
		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
};

#define aux_regs(id)\
[id] = {\
	AUX_REG_LIST(id)\
}

static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
		aux_regs(0),
		aux_regs(1),
		aux_regs(2),
		aux_regs(3),
		aux_regs(4),
		aux_regs(5)
};

#define hpd_regs(id)\
[id] = {\
	HPD_REG_LIST(id)\
}

static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
		hpd_regs(0),
		hpd_regs(1),
		hpd_regs(2),
		hpd_regs(3),
		hpd_regs(4),
		hpd_regs(5)
};

#define link_regs(id)\
[id] = {\
	LE_DCN10_REG_LIST(id), \
	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
}

static const struct dce110_link_enc_registers link_enc_regs[] = {
	link_regs(0),
	link_regs(1),
	link_regs(2),
	link_regs(3),
	link_regs(4),
	link_regs(5),
	link_regs(6),
};

#define ipp_regs(id)\
[id] = {\
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	IPP_REG_LIST_DCN10(id),\
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}

static const struct dcn10_ipp_registers ipp_regs[] = {
	ipp_regs(0),
	ipp_regs(1),
	ipp_regs(2),
	ipp_regs(3),
};

static const struct dcn10_ipp_shift ipp_shift = {
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		IPP_MASK_SH_LIST_DCN10(__SHIFT)
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};

static const struct dcn10_ipp_mask ipp_mask = {
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		IPP_MASK_SH_LIST_DCN10(_MASK),
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};

#define opp_regs(id)\
[id] = {\
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	OPP_REG_LIST_DCN10(id),\
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}

static const struct dcn10_opp_registers opp_regs[] = {
	opp_regs(0),
	opp_regs(1),
	opp_regs(2),
	opp_regs(3),
};

static const struct dcn10_opp_shift opp_shift = {
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		OPP_MASK_SH_LIST_DCN10(__SHIFT)
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};

static const struct dcn10_opp_mask opp_mask = {
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		OPP_MASK_SH_LIST_DCN10(_MASK),
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};

#define tf_regs(id)\
[id] = {\
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	TF_REG_LIST_DCN10(id),\
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}

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static const struct dcn_dpp_registers tf_regs[] = {
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	tf_regs(0),
	tf_regs(1),
	tf_regs(2),
	tf_regs(3),
};

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static const struct dcn_dpp_shift tf_shift = {
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	TF_REG_LIST_SH_MASK_DCN10(__SHIFT)
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};

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static const struct dcn_dpp_mask tf_mask = {
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	TF_REG_LIST_SH_MASK_DCN10(_MASK),
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};

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static const struct dcn_mpc_registers mpc_regs = {
		MPC_COMMON_REG_LIST_DCN1_0(0),
		MPC_COMMON_REG_LIST_DCN1_0(1),
		MPC_COMMON_REG_LIST_DCN1_0(2),
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		MPC_COMMON_REG_LIST_DCN1_0(3),
		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
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};

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static const struct dcn_mpc_shift mpc_shift = {
	MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
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};

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static const struct dcn_mpc_mask mpc_mask = {
	MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),
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};

#define tg_regs(id)\
[id] = {TG_COMMON_REG_LIST_DCN1_0(id)}

static const struct dcn_tg_registers tg_regs[] = {
	tg_regs(0),
	tg_regs(1),
	tg_regs(2),
	tg_regs(3),
};

static const struct dcn_tg_shift tg_shift = {
	TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
};

static const struct dcn_tg_mask tg_mask = {
	TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
};


static const struct bios_registers bios_regs = {
		NBIO_SR(BIOS_SCRATCH_6)
};

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#define hubp_regs(id)\
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[id] = {\
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	HUBP_REG_LIST_DCN10(id)\
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}


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static const struct dcn_mi_registers hubp_regs[] = {
	hubp_regs(0),
	hubp_regs(1),
	hubp_regs(2),
	hubp_regs(3),
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};

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static const struct dcn_mi_shift hubp_shift = {
		HUBP_MASK_SH_LIST_DCN10(__SHIFT)
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};

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static const struct dcn_mi_mask hubp_mask = {
		HUBP_MASK_SH_LIST_DCN10(_MASK)
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};

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static const struct dcn_hubbub_registers hubbub_reg = {
		HUBBUB_REG_LIST_DCN10(0)
};

static const struct dcn_hubbub_shift hubbub_shift = {
		HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
};

static const struct dcn_hubbub_mask hubbub_mask = {
		HUBBUB_MASK_SH_LIST_DCN10(_MASK)
};

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#define clk_src_regs(index, pllid)\
[index] = {\
	CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
}

static const struct dce110_clk_src_regs clk_src_regs[] = {
	clk_src_regs(0, A),
	clk_src_regs(1, B),
	clk_src_regs(2, C),
	clk_src_regs(3, D)
};

static const struct dce110_clk_src_shift cs_shift = {
		CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
};

static const struct dce110_clk_src_mask cs_mask = {
		CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
};


static const struct resource_caps res_cap = {
		.num_timing_generator = 4,
		.num_video_plane = 4,
		.num_audio = 4,
		.num_stream_encoder = 4,
		.num_pll = 4,
};

static const struct dc_debug debug_defaults_drv = {
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		.sanity_checks = true,
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		.disable_dmcu = true,
		.force_abm_enable = false,
		.timing_trace = false,
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		.clock_trace = true,
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		.min_disp_clk_khz = 300000,

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		.disable_pplib_clock_request = true,
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		.disable_pplib_wm_range = false,
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		.pplib_wm_report_mode = WM_REPORT_DEFAULT,
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		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
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		.force_single_disp_pipe_split = true,
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		.disable_dcc = DCC_ENABLE,
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		.voltage_align_fclk = true,
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		.disable_stereo_support = true,
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		.vsr_support = true,
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		.performance_trace = false,
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};

static const struct dc_debug debug_defaults_diags = {
		.disable_dmcu = true,
		.force_abm_enable = false,
		.timing_trace = true,
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		.clock_trace = true,
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		.disable_stutter = true,
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		.disable_pplib_clock_request = true,
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		.disable_pplib_wm_range = true
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};

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static void dcn10_dpp_destroy(struct dpp **dpp)
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{
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	kfree(TO_DCN10_DPP(*dpp));
	*dpp = NULL;
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}

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static struct dpp *dcn10_dpp_create(
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	struct dc_context *ctx,
	uint32_t inst)
{
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	struct dcn10_dpp *dpp =
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		kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
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	if (!dpp)
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		return NULL;

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	dpp1_construct(dpp, ctx, inst,
		       &tf_regs[inst], &tf_shift, &tf_mask);
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	return &dpp->base;
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}

static struct input_pixel_processor *dcn10_ipp_create(
	struct dc_context *ctx, uint32_t inst)
{
	struct dcn10_ipp *ipp =
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		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
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	if (!ipp) {
		BREAK_TO_DEBUGGER();
		return NULL;
	}

	dcn10_ipp_construct(ipp, ctx, inst,
			&ipp_regs[inst], &ipp_shift, &ipp_mask);
	return &ipp->base;
}


static struct output_pixel_processor *dcn10_opp_create(
	struct dc_context *ctx, uint32_t inst)
{
	struct dcn10_opp *opp =
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		kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
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	if (!opp) {
		BREAK_TO_DEBUGGER();
		return NULL;
	}

	dcn10_opp_construct(opp, ctx, inst,
			&opp_regs[inst], &opp_shift, &opp_mask);
	return &opp->base;
}

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static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
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{
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	struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
					  GFP_KERNEL);
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	if (!mpc10)
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		return NULL;

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	dcn10_mpc_construct(mpc10, ctx,
			&mpc_regs,
			&mpc_shift,
			&mpc_mask,
			4);
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	return &mpc10->base;
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}

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static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
{
	struct hubbub *hubbub = kzalloc(sizeof(struct hubbub),
					  GFP_KERNEL);

	if (!hubbub)
		return NULL;

	hubbub1_construct(hubbub, ctx,
			&hubbub_reg,
			&hubbub_shift,
			&hubbub_mask);

	return hubbub;
}

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static struct timing_generator *dcn10_timing_generator_create(
		struct dc_context *ctx,
		uint32_t instance)
{
	struct dcn10_timing_generator *tgn10 =
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		kzalloc(sizeof(struct dcn10_timing_generator), GFP_KERNEL);
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	if (!tgn10)
		return NULL;

	tgn10->base.inst = instance;
	tgn10->base.ctx = ctx;

	tgn10->tg_regs = &tg_regs[instance];
	tgn10->tg_shift = &tg_shift;
	tgn10->tg_mask = &tg_mask;

	dcn10_timing_generator_init(tgn10);

	return &tgn10->base;
}

static const struct encoder_feature_support link_enc_feature = {
		.max_hdmi_deep_color = COLOR_DEPTH_121212,
		.max_hdmi_pixel_clock = 600000,
		.ycbcr420_supported = true,
		.flags.bits.IS_HBR2_CAPABLE = true,
		.flags.bits.IS_HBR3_CAPABLE = true,
		.flags.bits.IS_TPS3_CAPABLE = true,
		.flags.bits.IS_TPS4_CAPABLE = true,
		.flags.bits.IS_YCBCR_CAPABLE = true
};

struct link_encoder *dcn10_link_encoder_create(
	const struct encoder_init_data *enc_init_data)
{
	struct dce110_link_encoder *enc110 =
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		kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
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	if (!enc110)
		return NULL;

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	dce110_link_encoder_construct(enc110,
				      enc_init_data,
				      &link_enc_feature,
				      &link_enc_regs[enc_init_data->transmitter],
				      &link_enc_aux_regs[enc_init_data->channel - 1],
				      &link_enc_hpd_regs[enc_init_data->hpd_source]);

	return &enc110->base;
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}

struct clock_source *dcn10_clock_source_create(
	struct dc_context *ctx,
	struct dc_bios *bios,
	enum clock_source_id id,
	const struct dce110_clk_src_regs *regs,
	bool dp_clk_src)
{
	struct dce110_clk_src *clk_src =
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		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
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	if (!clk_src)
		return NULL;

	if (dce110_clk_src_construct(clk_src, ctx, bios, id,
			regs, &cs_shift, &cs_mask)) {
		clk_src->base.dp_clk_src = dp_clk_src;
		return &clk_src->base;
	}

	BREAK_TO_DEBUGGER();
	return NULL;
}

static void read_dce_straps(
	struct dc_context *ctx,
	struct resource_straps *straps)
{
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	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
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}

static struct audio *create_audio(
		struct dc_context *ctx, unsigned int inst)
{
	return dce_audio_create(ctx, inst,
			&audio_regs[inst], &audio_shift, &audio_mask);
}

static struct stream_encoder *dcn10_stream_encoder_create(
	enum engine_id eng_id,
	struct dc_context *ctx)
{
	struct dce110_stream_encoder *enc110 =
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		kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
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	if (!enc110)
		return NULL;

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	dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
					&stream_enc_regs[eng_id],
					&se_shift, &se_mask);
	return &enc110->base;
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}

static const struct dce_hwseq_registers hwseq_reg = {
		HWSEQ_DCN1_REG_LIST()
};

static const struct dce_hwseq_shift hwseq_shift = {
		HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
};

static const struct dce_hwseq_mask hwseq_mask = {
		HWSEQ_DCN1_MASK_SH_LIST(_MASK)
};

static struct dce_hwseq *dcn10_hwseq_create(
	struct dc_context *ctx)
{
673
	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
674 675 676 677 678 679

	if (hws) {
		hws->ctx = ctx;
		hws->regs = &hwseq_reg;
		hws->shifts = &hwseq_shift;
		hws->masks = &hwseq_mask;
680
		hws->wa.DEGVIDCN10_253 = true;
681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700
	}
	return hws;
}

static const struct resource_create_funcs res_create_funcs = {
	.read_dce_straps = read_dce_straps,
	.create_audio = create_audio,
	.create_stream_encoder = dcn10_stream_encoder_create,
	.create_hwseq = dcn10_hwseq_create,
};

static const struct resource_create_funcs res_create_maximus_funcs = {
	.read_dce_straps = NULL,
	.create_audio = NULL,
	.create_stream_encoder = NULL,
	.create_hwseq = dcn10_hwseq_create,
};

void dcn10_clock_source_destroy(struct clock_source **clk_src)
{
701
	kfree(TO_DCE110_CLK_SRC(*clk_src));
702 703 704
	*clk_src = NULL;
}

705 706
static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx)
{
707
	struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
708 709 710 711 712 713 714 715

	if (!pp_smu)
		return pp_smu;

	dm_pp_get_funcs_rv(ctx, pp_smu);
	return pp_smu;
}

716 717 718 719 720 721 722 723 724
static void destruct(struct dcn10_resource_pool *pool)
{
	unsigned int i;

	for (i = 0; i < pool->base.stream_enc_count; i++) {
		if (pool->base.stream_enc[i] != NULL) {
			/* TODO: free dcn version of stream encoder once implemented
			 * rather than using virtual stream encoder
			 */
725
			kfree(pool->base.stream_enc[i]);
726 727 728 729
			pool->base.stream_enc[i] = NULL;
		}
	}

730
	if (pool->base.mpc != NULL) {
731
		kfree(TO_DCN10_MPC(pool->base.mpc));
732 733
		pool->base.mpc = NULL;
	}
734 735 736 737 738 739

	if (pool->base.hubbub != NULL) {
		kfree(pool->base.hubbub);
		pool->base.hubbub = NULL;
	}

740 741 742 743
	for (i = 0; i < pool->base.pipe_count; i++) {
		if (pool->base.opps[i] != NULL)
			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);

744 745
		if (pool->base.dpps[i] != NULL)
			dcn10_dpp_destroy(&pool->base.dpps[i]);
746 747 748 749

		if (pool->base.ipps[i] != NULL)
			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);

750 751 752
		if (pool->base.hubps[i] != NULL) {
			kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
			pool->base.hubps[i] = NULL;
753 754 755 756 757 758 759
		}

		if (pool->base.irqs != NULL) {
			dal_irq_service_destroy(&pool->base.irqs);
		}

		if (pool->base.timing_generators[i] != NULL)	{
760
			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
761 762 763 764
			pool->base.timing_generators[i] = NULL;
		}
	}

765 766
	for (i = 0; i < pool->base.stream_enc_count; i++)
		kfree(pool->base.stream_enc[i]);
767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792

	for (i = 0; i < pool->base.audio_count; i++) {
		if (pool->base.audios[i])
			dce_aud_destroy(&pool->base.audios[i]);
	}

	for (i = 0; i < pool->base.clk_src_count; i++) {
		if (pool->base.clock_sources[i] != NULL) {
			dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
			pool->base.clock_sources[i] = NULL;
		}
	}

	if (pool->base.dp_clock_source != NULL) {
		dcn10_clock_source_destroy(&pool->base.dp_clock_source);
		pool->base.dp_clock_source = NULL;
	}

	if (pool->base.abm != NULL)
		dce_abm_destroy(&pool->base.abm);

	if (pool->base.dmcu != NULL)
		dce_dmcu_destroy(&pool->base.dmcu);

	if (pool->base.display_clock != NULL)
		dce_disp_clk_destroy(&pool->base.display_clock);
793

794
	kfree(pool->base.pp_smu);
795 796
}

797
static struct hubp *dcn10_hubp_create(
798 799 800
	struct dc_context *ctx,
	uint32_t inst)
{
801 802
	struct dcn10_hubp *hubp1 =
		kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
803

804
	if (!hubp1)
805 806
		return NULL;

807
	dcn10_hubp_construct(hubp1, ctx, inst,
808
			     &hubp_regs[inst], &hubp_shift, &hubp_mask);
809
	return &hubp1->base;
810 811 812 813 814 815
}

static void get_pixel_clock_parameters(
	const struct pipe_ctx *pipe_ctx,
	struct pixel_clk_params *pixel_clk_params)
{
816
	const struct dc_stream_state *stream = pipe_ctx->stream;
817
	pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
818 819 820 821 822 823 824 825
	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
	pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
	/* TODO: un-hardcode*/
	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
		LINK_RATE_REF_FREQ_IN_KHZ;
	pixel_clk_params->flags.ENABLE_SS = 0;
	pixel_clk_params->color_depth =
826
		stream->timing.display_color_depth;
827
	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
828
	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
829

830
	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
831 832
		pixel_clk_params->color_depth = COLOR_DEPTH_888;

833
	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
834 835 836 837
		pixel_clk_params->requested_pix_clk  /= 2;

}

838
static void build_clamping_params(struct dc_stream_state *stream)
839 840
{
	stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
841 842
	stream->clamping.c_depth = stream->timing.display_color_depth;
	stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
843 844
}

845
static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
846 847
{

848
	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
849 850 851

	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
		pipe_ctx->clock_source,
852
		&pipe_ctx->stream_res.pix_clk_params,
853 854
		&pipe_ctx->pll_settings);

855
	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
856 857 858 859 860 861

	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
					&pipe_ctx->stream->bit_depth_params);
	build_clamping_params(pipe_ctx->stream);
}

862
static enum dc_status build_mapped_resource(
863
		const struct dc *dc,
864
		struct dc_state *context,
865
		struct dc_stream_state *stream)
866
{
867
	struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
868

869 870
	/*TODO Seems unneeded anymore */
	/*	if (old_context && resource_is_stream_unchanged(old_context, stream)) {
871
			if (stream != NULL && old_context->streams[i] != NULL) {
872
				 todo: shouldn't have to copy missing parameter here
873 874 875
				resource_build_bit_depth_reduction_params(stream,
						&stream->bit_depth_params);
				stream->clamping.pixel_encoding =
876
						stream->timing.pixel_encoding;
877 878 879 880 881 882 883 884

				resource_build_bit_depth_reduction_params(stream,
								&stream->bit_depth_params);
				build_clamping_params(stream);

				continue;
			}
		}
885
	*/
886

887 888
	if (!pipe_ctx)
		return DC_ERROR_UNEXPECTED;
889

890
	build_pipe_hw_param(pipe_ctx);
891 892 893
	return DC_OK;
}

894
enum dc_status dcn10_add_stream_to_ctx(
895
		struct dc *dc,
896
		struct dc_state *new_ctx,
897
		struct dc_stream_state *dc_stream)
898
{
899
	enum dc_status result = DC_ERROR_UNEXPECTED;
900

901
	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
902

903 904
	if (result == DC_OK)
		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
905 906


907 908
	if (result == DC_OK)
		result = build_mapped_resource(dc, new_ctx, dc_stream);
909 910 911 912 913

	return result;
}

enum dc_status dcn10_validate_guaranteed(
914
		struct dc *dc,
915
		struct dc_stream_state *dc_stream,
916
		struct dc_state *context)
917 918 919
{
	enum dc_status result = DC_ERROR_UNEXPECTED;

920 921
	context->streams[0] = dc_stream;
	dc_stream_retain(context->streams[0]);
922 923
	context->stream_count++;

924
	result = resource_map_pool_resources(dc, context, dc_stream);
925 926

	if (result == DC_OK)
927
		result = resource_map_phy_clock_resources(dc, context, dc_stream);
928 929

	if (result == DC_OK)
930
		result = build_mapped_resource(dc, context, dc_stream);
931 932 933

	if (result == DC_OK) {
		validate_guaranteed_copy_streams(
934
				context, dc->caps.max_streams);
935 936 937 938 939 940 941 942 943
		result = resource_build_scaling_params_for_context(dc, context);
	}
	if (result == DC_OK && !dcn_validate_bandwidth(dc, context))
		return DC_FAIL_BANDWIDTH_VALIDATE;

	return result;
}

static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
944
		struct dc_state *context,
945
		const struct resource_pool *pool,
946
		struct dc_stream_state *stream)
947 948 949 950 951
{
	struct resource_context *res_ctx = &context->res_ctx;
	struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
	struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool);

952
	if (!head_pipe) {
953
		ASSERT(0);
954 955
		return NULL;
	}
956 957

	if (!idle_pipe)
958
		return NULL;
959 960

	idle_pipe->stream = head_pipe->stream;
961
	idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
962
	idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
963

964
	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
965
	idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
966
	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036

	return idle_pipe;
}

enum dcc_control {
	dcc_control__256_256_xxx,
	dcc_control__128_128_xxx,
	dcc_control__256_64_64,
};

enum segment_order {
	segment_order__na,
	segment_order__contiguous,
	segment_order__non_contiguous,
};

static bool dcc_support_pixel_format(
		enum surface_pixel_format format,
		unsigned int *bytes_per_element)
{
	/* DML: get_bytes_per_element */
	switch (format) {
	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
		*bytes_per_element = 2;
		return true;
	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
		*bytes_per_element = 4;
		return true;
	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
		*bytes_per_element = 8;
		return true;
	default:
		return false;
	}
}

static bool dcc_support_swizzle(
		enum swizzle_mode_values swizzle,
		unsigned int bytes_per_element,
		enum segment_order *segment_order_horz,
		enum segment_order *segment_order_vert)
{
	bool standard_swizzle = false;
	bool display_swizzle = false;

	switch (swizzle) {
	case DC_SW_4KB_S:
	case DC_SW_64KB_S:
	case DC_SW_VAR_S:
	case DC_SW_4KB_S_X:
	case DC_SW_64KB_S_X:
	case DC_SW_VAR_S_X:
		standard_swizzle = true;
		break;
	case DC_SW_4KB_D:
	case DC_SW_64KB_D:
	case DC_SW_VAR_D:
	case DC_SW_4KB_D_X:
	case DC_SW_64KB_D_X:
	case DC_SW_VAR_D_X:
		display_swizzle = true;
		break;
	default:
		break;
1037
	}
1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126

	if (bytes_per_element == 1 && standard_swizzle) {
		*segment_order_horz = segment_order__contiguous;
		*segment_order_vert = segment_order__na;
		return true;
	}
	if (bytes_per_element == 2 && standard_swizzle) {
		*segment_order_horz = segment_order__non_contiguous;
		*segment_order_vert = segment_order__contiguous;
		return true;
	}
	if (bytes_per_element == 4 && standard_swizzle) {
		*segment_order_horz = segment_order__non_contiguous;
		*segment_order_vert = segment_order__contiguous;
		return true;
	}
	if (bytes_per_element == 8 && standard_swizzle) {
		*segment_order_horz = segment_order__na;
		*segment_order_vert = segment_order__contiguous;
		return true;
	}
	if (bytes_per_element == 8 && display_swizzle) {
		*segment_order_horz = segment_order__contiguous;
		*segment_order_vert = segment_order__non_contiguous;
		return true;
	}

	return false;
}

static void get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
		unsigned int bytes_per_element)
{
	/* copied from DML.  might want to refactor DML to leverage from DML */
	/* DML : get_blk256_size */
	if (bytes_per_element == 1) {
		*blk256_width = 16;
		*blk256_height = 16;
	} else if (bytes_per_element == 2) {
		*blk256_width = 16;
		*blk256_height = 8;
	} else if (bytes_per_element == 4) {
		*blk256_width = 8;
		*blk256_height = 8;
	} else if (bytes_per_element == 8) {
		*blk256_width = 8;
		*blk256_height = 4;
	}
}

static void det_request_size(
		unsigned int height,
		unsigned int width,
		unsigned int bpe,
		bool *req128_horz_wc,
		bool *req128_vert_wc)
{
	unsigned int detile_buf_size = 164 * 1024;  /* 164KB for DCN1.0 */

	unsigned int blk256_height = 0;
	unsigned int blk256_width = 0;
	unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;

	get_blk256_size(&blk256_width, &blk256_height, bpe);

	swath_bytes_horz_wc = height * blk256_height * bpe;
	swath_bytes_vert_wc = width * blk256_width * bpe;

	*req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
			false : /* full 256B request */
			true; /* half 128b request */

	*req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
			false : /* full 256B request */
			true; /* half 128b request */
}

static bool get_dcc_compression_cap(const struct dc *dc,
		const struct dc_dcc_surface_param *input,
		struct dc_surface_dcc_cap *output)
{
	/* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
	enum dcc_control dcc_control;
	unsigned int bpe;
	enum segment_order segment_order_horz, segment_order_vert;
	bool req128_horz_wc, req128_vert_wc;

	memset(output, 0, sizeof(*output));

1127
	if (dc->debug.disable_dcc == DCC_DISABLE)
1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170
		return false;

	if (!dcc_support_pixel_format(input->format,
			&bpe))
		return false;

	if (!dcc_support_swizzle(input->swizzle_mode, bpe,
			&segment_order_horz, &segment_order_vert))
		return false;

	det_request_size(input->surface_size.height,  input->surface_size.width,
			bpe, &req128_horz_wc, &req128_vert_wc);

	if (!req128_horz_wc && !req128_vert_wc) {
		dcc_control = dcc_control__256_256_xxx;
	} else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
		if (!req128_horz_wc)
			dcc_control = dcc_control__256_256_xxx;
		else if (segment_order_horz == segment_order__contiguous)
			dcc_control = dcc_control__128_128_xxx;
		else
			dcc_control = dcc_control__256_64_64;
	} else if (input->scan == SCAN_DIRECTION_VERTICAL) {
		if (!req128_vert_wc)
			dcc_control = dcc_control__256_256_xxx;
		else if (segment_order_vert == segment_order__contiguous)
			dcc_control = dcc_control__128_128_xxx;
		else
			dcc_control = dcc_control__256_64_64;
	} else {
		if ((req128_horz_wc &&
			segment_order_horz == segment_order__non_contiguous) ||
			(req128_vert_wc &&
			segment_order_vert == segment_order__non_contiguous))
			/* access_dir not known, must use most constraining */
			dcc_control = dcc_control__256_64_64;
		else
			/* reg128 is true for either horz and vert
			 * but segment_order is contiguous
			 */
			dcc_control = dcc_control__128_128_xxx;
	}

1171 1172 1173 1174
	if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
		dcc_control != dcc_control__256_256_xxx)
		return false;

1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191
	switch (dcc_control) {
	case dcc_control__256_256_xxx:
		output->grph.rgb.max_uncompressed_blk_size = 256;
		output->grph.rgb.max_compressed_blk_size = 256;
		output->grph.rgb.independent_64b_blks = false;
		break;
	case dcc_control__128_128_xxx:
		output->grph.rgb.max_uncompressed_blk_size = 128;
		output->grph.rgb.max_compressed_blk_size = 128;
		output->grph.rgb.independent_64b_blks = false;
		break;
	case dcc_control__256_64_64:
		output->grph.rgb.max_uncompressed_blk_size = 256;
		output->grph.rgb.max_compressed_blk_size = 64;
		output->grph.rgb.independent_64b_blks = true;
		break;
	}
1192

1193 1194
	output->capable = true;
	output->const_color_support = false;
1195 1196 1197 1198 1199 1200 1201 1202 1203 1204

	return true;
}


static void dcn10_destroy_resource_pool(struct resource_pool **pool)
{
	struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);

	destruct(dcn10_pool);
1205
	kfree(dcn10_pool);
1206 1207 1208
	*pool = NULL;
}

1209
static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1210 1211
{
	if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1212 1213
			&& caps->max_video_width != 0
			&& plane_state->src_rect.width > caps->max_video_width)
1214 1215 1216 1217
		return DC_FAIL_SURFACE_VALIDATE;

	return DC_OK;
}
1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228

static struct dc_cap_funcs cap_funcs = {
	.get_dcc_compression_cap = get_dcc_compression_cap
};

static struct resource_funcs dcn10_res_pool_funcs = {
	.destroy = dcn10_destroy_resource_pool,
	.link_enc_create = dcn10_link_encoder_create,
	.validate_guaranteed = dcn10_validate_guaranteed,
	.validate_bandwidth = dcn_validate_bandwidth,
	.acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
1229
	.validate_plane = dcn10_validate_plane,
1230
	.add_stream_to_ctx = dcn10_add_stream_to_ctx
1231 1232
};

1233 1234 1235 1236 1237 1238 1239 1240
static uint32_t read_pipe_fuses(struct dc_context *ctx)
{
	uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
	/* RV1 support max 4 pipes */
	value = value & 0xf;
	return value;
}

1241 1242
static bool construct(
	uint8_t num_virtual_links,
1243
	struct dc *dc,
1244 1245 1246
	struct dcn10_resource_pool *pool)
{
	int i;
1247
	int j;
1248
	struct dc_context *ctx = dc->ctx;
1249
	uint32_t pipe_fuses = read_pipe_fuses(ctx);
1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265

	ctx->dc_bios->regs = &bios_regs;

	pool->base.res_cap = &res_cap;
	pool->base.funcs = &dcn10_res_pool_funcs;

	/*
	 * TODO fill in from actual raven resource when we create
	 * more than virtual encoder
	 */

	/*************************************************
	 *  Resource + asic cap harcoding                *
	 *************************************************/
	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

1266 1267 1268
	/* max pipe num for ASIC before check pipe fuses */
	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

1269
	dc->caps.max_video_width = 3840;
1270 1271 1272 1273
	dc->caps.max_downscale_ratio = 200;
	dc->caps.i2c_speed_in_khz = 100;
	dc->caps.max_cursor_size = 256;
	dc->caps.max_slave_planes = 1;
1274
	dc->caps.is_apu = true;
1275

1276
	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1277
		dc->debug = debug_defaults_drv;
1278
	else
1279
		dc->debug = debug_defaults_diags;
1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313

	/*************************************************
	 *  Create resources                             *
	 *************************************************/

	pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
			dcn10_clock_source_create(ctx, ctx->dc_bios,
				CLOCK_SOURCE_COMBO_PHY_PLL0,
				&clk_src_regs[0], false);
	pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
			dcn10_clock_source_create(ctx, ctx->dc_bios,
				CLOCK_SOURCE_COMBO_PHY_PLL1,
				&clk_src_regs[1], false);
	pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
			dcn10_clock_source_create(ctx, ctx->dc_bios,
				CLOCK_SOURCE_COMBO_PHY_PLL2,
				&clk_src_regs[2], false);
	pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
			dcn10_clock_source_create(ctx, ctx->dc_bios,
				CLOCK_SOURCE_COMBO_PHY_PLL3,
				&clk_src_regs[3], false);

	pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;

	pool->base.dp_clock_source =
			dcn10_clock_source_create(ctx, ctx->dc_bios,
				CLOCK_SOURCE_ID_DP_DTO,
				/* todo: not reuse phy_pll registers */
				&clk_src_regs[0], true);

	for (i = 0; i < pool->base.clk_src_count; i++) {
		if (pool->base.clock_sources[i] == NULL) {
			dm_error("DC: failed to create clock sources!\n");
			BREAK_TO_DEBUGGER();
1314
			goto fail;
1315 1316 1317 1318
		}
	}

	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1319
		pool->base.display_clock = dce120_disp_clk_create(ctx);
1320 1321 1322
		if (pool->base.display_clock == NULL) {
			dm_error("DC: failed to create display clock!\n");
			BREAK_TO_DEBUGGER();
1323
			goto fail;
1324 1325 1326 1327 1328 1329 1330 1331 1332 1333
		}
	}

	pool->base.dmcu = dcn10_dmcu_create(ctx,
			&dmcu_regs,
			&dmcu_shift,
			&dmcu_mask);
	if (pool->base.dmcu == NULL) {
		dm_error("DC: failed to create dmcu!\n");
		BREAK_TO_DEBUGGER();
1334
		goto fail;
1335 1336 1337 1338 1339 1340 1341 1342 1343
	}

	pool->base.abm = dce_abm_create(ctx,
			&abm_regs,
			&abm_shift,
			&abm_mask);
	if (pool->base.abm == NULL) {
		dm_error("DC: failed to create abm!\n");
		BREAK_TO_DEBUGGER();
1344
		goto fail;
1345 1346 1347
	}

	dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
1348 1349
	memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
	memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1350

1351
	if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1352
		dc->dcn_soc->urgent_latency = 3;
1353
		dc->debug.disable_dmcu = true;
1354
		dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
1355 1356 1357
	}


1358 1359 1360 1361
	dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
	ASSERT(dc->dcn_soc->number_of_channels < 3);
	if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
		dc->dcn_soc->number_of_channels = 2;
1362

1363 1364 1365 1366 1367
	if (dc->dcn_soc->number_of_channels == 1) {
		dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
		dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
		dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
		dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
1368
		if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1369
			dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
1370
		}
1371 1372
	}

1373 1374
	pool->base.pp_smu = dcn10_pp_smu_create(ctx);

1375
	if (!dc->debug.disable_pplib_clock_request)
1376 1377
		dcn_bw_update_from_pplib(dc);
	dcn_bw_sync_calcs_and_dml(dc);
1378 1379
	if (!dc->debug.disable_pplib_wm_range) {
		dc->res_pool = &pool->base;
1380
		dcn_bw_notify_pplib_of_wm_ranges(dc);
1381
	}
1382 1383 1384 1385 1386 1387

	{
		struct irq_service_init_data init_data;
		init_data.ctx = dc->ctx;
		pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
		if (!pool->base.irqs)
1388
			goto fail;
1389 1390
	}

1391 1392
	/* index to valid pipe resource  */
	j = 0;
1393
	/* mem input -> ipp -> dpp -> opp -> TG */
1394
	for (i = 0; i < pool->base.pipe_count; i++) {
1395 1396 1397 1398 1399 1400
		/* if pipe is disabled, skip instance of HW pipe,
		 * i.e, skip ASIC register instance
		 */
		if ((pipe_fuses & (1 << i)) != 0)
			continue;

1401 1402
		pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
		if (pool->base.hubps[j] == NULL) {
1403 1404 1405
			BREAK_TO_DEBUGGER();
			dm_error(
				"DC: failed to create memory input!\n");
1406
			goto fail;
1407 1408
		}

1409 1410
		pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
		if (pool->base.ipps[j] == NULL) {
1411 1412 1413
			BREAK_TO_DEBUGGER();
			dm_error(
				"DC: failed to create input pixel processor!\n");
1414
			goto fail;
1415 1416
		}

1417 1418
		pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
		if (pool->base.dpps[j] == NULL) {
1419 1420
			BREAK_TO_DEBUGGER();
			dm_error(
1421
				"DC: failed to create dpp!\n");
1422
			goto fail;
1423 1424
		}

1425 1426
		pool->base.opps[j] = dcn10_opp_create(ctx, i);
		if (pool->base.opps[j] == NULL) {
1427 1428 1429
			BREAK_TO_DEBUGGER();
			dm_error(
				"DC: failed to create output pixel processor!\n");
1430
			goto fail;
1431 1432
		}

1433
		pool->base.timing_generators[j] = dcn10_timing_generator_create(
1434
				ctx, i);
1435
		if (pool->base.timing_generators[j] == NULL) {
1436 1437
			BREAK_TO_DEBUGGER();
			dm_error("DC: failed to create tg!\n");
1438
			goto fail;
1439
		}
1440

1441 1442
		/* check next valid pipe */
		j++;
1443
	}
1444 1445 1446 1447 1448 1449 1450 1451 1452 1453

	/* valid pipe num */
	pool->base.pipe_count = j;

	/* within dml lib, it is hard code to 4. If ASIC pipe is fused,
	 * the value may be changed
	 */
	dc->dml.ip.max_num_dpp = pool->base.pipe_count;
	dc->dcn_ip->max_num_dpp = pool->base.pipe_count;

1454 1455 1456 1457
	pool->base.mpc = dcn10_mpc_create(ctx);
	if (pool->base.mpc == NULL) {
		BREAK_TO_DEBUGGER();
		dm_error("DC: failed to create mpc!\n");
1458
		goto fail;
1459 1460
	}

1461
	pool->base.hubbub = dcn10_hubbub_create(ctx);
1462
	if (pool->base.hubbub == NULL) {
1463
		BREAK_TO_DEBUGGER();
1464
		dm_error("DC: failed to create hubbub!\n");
1465 1466 1467
		goto fail;
	}

1468 1469 1470
	if (!resource_construct(num_virtual_links, dc, &pool->base,
			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
			&res_create_funcs : &res_create_maximus_funcs)))
1471
			goto fail;
1472 1473

	dcn10_hw_sequencer_construct(dc);
1474
	dc->caps.max_planes =  pool->base.pipe_count;
1475

1476
	dc->cap_funcs = cap_funcs;
1477 1478 1479

	return true;

1480
fail:
1481 1482 1483 1484 1485 1486 1487 1488

	destruct(pool);

	return false;
}

struct resource_pool *dcn10_create_resource_pool(
		uint8_t num_virtual_links,
1489
		struct dc *dc)
1490 1491
{
	struct dcn10_resource_pool *pool =
1492
		kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1493 1494 1495 1496 1497 1498 1499 1500 1501 1502

	if (!pool)
		return NULL;

	if (construct(num_virtual_links, dc, pool))
		return &pool->base;

	BREAK_TO_DEBUGGER();
	return NULL;
}