at91_can.c 35.3 KB
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// SPDX-License-Identifier: GPL-2.0-only
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/*
 * at91_can.c - CAN network driver for AT91 SoC CAN controller
 *
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 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
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 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de>
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 */

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#include <linux/bitfield.h>
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#include <linux/clk.h>
#include <linux/errno.h>
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#include <linux/ethtool.h>
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#include <linux/if_arp.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/netdevice.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/rtnetlink.h>
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#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/types.h>

#include <linux/can/dev.h>
#include <linux/can/error.h>

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#define AT91_MB_MASK(i) ((1 << (i)) - 1)
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/* Common registers */
enum at91_reg {
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	AT91_MR = 0x000,
	AT91_IER = 0x004,
	AT91_IDR = 0x008,
	AT91_IMR = 0x00C,
	AT91_SR = 0x010,
	AT91_BR = 0x014,
	AT91_TIM = 0x018,
	AT91_TIMESTP = 0x01C,
	AT91_ECR = 0x020,
	AT91_TCR = 0x024,
	AT91_ACR = 0x028,
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};

/* Mailbox registers (0 <= i <= 15) */
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#define AT91_MMR(i) ((enum at91_reg)(0x200 + ((i) * 0x20)))
#define AT91_MAM(i) ((enum at91_reg)(0x204 + ((i) * 0x20)))
#define AT91_MID(i) ((enum at91_reg)(0x208 + ((i) * 0x20)))
#define AT91_MFID(i) ((enum at91_reg)(0x20C + ((i) * 0x20)))
#define AT91_MSR(i) ((enum at91_reg)(0x210 + ((i) * 0x20)))
#define AT91_MDL(i) ((enum at91_reg)(0x214 + ((i) * 0x20)))
#define AT91_MDH(i) ((enum at91_reg)(0x218 + ((i) * 0x20)))
#define AT91_MCR(i) ((enum at91_reg)(0x21C + ((i) * 0x20)))
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/* Register bits */
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#define AT91_MR_CANEN BIT(0)
#define AT91_MR_LPM BIT(1)
#define AT91_MR_ABM BIT(2)
#define AT91_MR_OVL BIT(3)
#define AT91_MR_TEOF BIT(4)
#define AT91_MR_TTM BIT(5)
#define AT91_MR_TIMFRZ BIT(6)
#define AT91_MR_DRPT BIT(7)
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#define AT91_SR_RBSY BIT(29)
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#define AT91_BR_PHASE2_MASK GENMASK(2, 0)
#define AT91_BR_PHASE1_MASK GENMASK(6, 4)
#define AT91_BR_PROPAG_MASK GENMASK(10, 8)
#define AT91_BR_SJW_MASK GENMASK(13, 12)
#define AT91_BR_BRP_MASK GENMASK(22, 16)
#define AT91_BR_SMP BIT(24)

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#define AT91_ECR_REC_MASK GENMASK(8, 0)
#define AT91_ECR_TEC_MASK GENMASK(23, 16)

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#define AT91_MMR_MTIMEMARK_MASK GENMASK(15, 0)
#define AT91_MMR_PRIOR_MASK GENMASK(19, 16)
#define AT91_MMR_MOT_MASK GENMASK(26, 24)
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#define AT91_MID_MIDVB_MASK GENMASK(17, 0)
#define AT91_MID_MIDVA_MASK GENMASK(28, 18)
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#define AT91_MID_MIDE BIT(29)
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#define AT91_MSR_MTIMESTAMP_MASK GENMASK(15, 0)
#define AT91_MSR_MDLC_MASK GENMASK(19, 16)
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#define AT91_MSR_MRTR BIT(20)
#define AT91_MSR_MABT BIT(22)
#define AT91_MSR_MRDY BIT(23)
#define AT91_MSR_MMI BIT(24)
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#define AT91_MCR_MDLC_MASK GENMASK(19, 16)
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#define AT91_MCR_MRTR BIT(20)
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#define AT91_MCR_MACR BIT(22)
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#define AT91_MCR_MTCR BIT(23)
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/* Mailbox Modes */
enum at91_mb_mode {
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	AT91_MB_MODE_DISABLED = 0,
	AT91_MB_MODE_RX = 1,
	AT91_MB_MODE_RX_OVRWR = 2,
	AT91_MB_MODE_TX = 3,
	AT91_MB_MODE_CONSUMER = 4,
	AT91_MB_MODE_PRODUCER = 5,
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};

/* Interrupt mask bits */
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#define AT91_IRQ_ERRA BIT(16)
#define AT91_IRQ_WARN BIT(17)
#define AT91_IRQ_ERRP BIT(18)
#define AT91_IRQ_BOFF BIT(19)
#define AT91_IRQ_SLEEP BIT(20)
#define AT91_IRQ_WAKEUP BIT(21)
#define AT91_IRQ_TOVF BIT(22)
#define AT91_IRQ_TSTP BIT(23)
#define AT91_IRQ_CERR BIT(24)
#define AT91_IRQ_SERR BIT(25)
#define AT91_IRQ_AERR BIT(26)
#define AT91_IRQ_FERR BIT(27)
#define AT91_IRQ_BERR BIT(28)

#define AT91_IRQ_ERR_ALL (0x1fff0000)
#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
			    AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
			   AT91_IRQ_ERRP | AT91_IRQ_BOFF)

#define AT91_IRQ_ALL (0x1fffffff)
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enum at91_devtype {
	AT91_DEVTYPE_SAM9263,
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	AT91_DEVTYPE_SAM9X5,
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};

struct at91_devtype_data {
	unsigned int rx_first;
	unsigned int rx_split;
	unsigned int rx_last;
	unsigned int tx_shift;
	enum at91_devtype type;
};

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struct at91_priv {
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	struct can_priv can;		/* must be the first member! */
	struct napi_struct napi;
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	void __iomem *reg_base;
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	u32 reg_sr;
	unsigned int tx_next;
	unsigned int tx_echo;
	unsigned int rx_next;
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	struct at91_devtype_data devtype_data;
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	struct clk *clk;
	struct at91_can_data *pdata;
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	canid_t mb0_id;
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};

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static const struct at91_devtype_data at91_at91sam9263_data = {
	.rx_first = 1,
	.rx_split = 8,
	.rx_last = 11,
	.tx_shift = 2,
	.type = AT91_DEVTYPE_SAM9263,
};

static const struct at91_devtype_data at91_at91sam9x5_data = {
	.rx_first = 0,
	.rx_split = 4,
	.rx_last = 5,
	.tx_shift = 1,
	.type = AT91_DEVTYPE_SAM9X5,
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};

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static const struct can_bittiming_const at91_bittiming_const = {
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	.name		= KBUILD_MODNAME,
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	.tseg1_min	= 4,
	.tseg1_max	= 16,
	.tseg2_min	= 2,
	.tseg2_max	= 8,
	.sjw_max	= 4,
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	.brp_min	= 2,
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	.brp_max	= 128,
	.brp_inc	= 1,
};

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#define AT91_IS(_model) \
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static inline int __maybe_unused at91_is_sam##_model(const struct at91_priv *priv) \
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{ \
	return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
}

AT91_IS(9263);
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AT91_IS(9X5);
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static inline unsigned int get_mb_rx_first(const struct at91_priv *priv)
{
	return priv->devtype_data.rx_first;
}

static inline unsigned int get_mb_rx_last(const struct at91_priv *priv)
{
	return priv->devtype_data.rx_last;
}

static inline unsigned int get_mb_rx_split(const struct at91_priv *priv)
{
	return priv->devtype_data.rx_split;
}

static inline unsigned int get_mb_rx_num(const struct at91_priv *priv)
{
	return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1;
}

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static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv)
{
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	return get_mb_rx_split(priv) - 1;
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}

static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv)
{
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	return AT91_MB_MASK(get_mb_rx_split(priv)) &
		~AT91_MB_MASK(get_mb_rx_first(priv));
}

static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv)
{
	return priv->devtype_data.tx_shift;
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}

static inline unsigned int get_mb_tx_num(const struct at91_priv *priv)
{
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	return 1 << get_mb_tx_shift(priv);
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}

static inline unsigned int get_mb_tx_first(const struct at91_priv *priv)
{
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	return get_mb_rx_last(priv) + 1;
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}

static inline unsigned int get_mb_tx_last(const struct at91_priv *priv)
{
	return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1;
}

static inline unsigned int get_next_prio_shift(const struct at91_priv *priv)
{
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	return get_mb_tx_shift(priv);
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}

static inline unsigned int get_next_prio_mask(const struct at91_priv *priv)
{
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	return 0xf << get_mb_tx_shift(priv);
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}

static inline unsigned int get_next_mb_mask(const struct at91_priv *priv)
{
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	return AT91_MB_MASK(get_mb_tx_shift(priv));
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}

static inline unsigned int get_next_mask(const struct at91_priv *priv)
{
	return get_next_mb_mask(priv) | get_next_prio_mask(priv);
}

static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv)
{
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	return AT91_MB_MASK(get_mb_rx_last(priv) + 1) &
		~AT91_MB_MASK(get_mb_rx_first(priv));
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}

static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv)
{
	return AT91_MB_MASK(get_mb_tx_last(priv) + 1) &
		~AT91_MB_MASK(get_mb_tx_first(priv));
}

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static inline unsigned int get_tx_next_mb(const struct at91_priv *priv)
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{
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	return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
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}

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static inline unsigned int get_tx_next_prio(const struct at91_priv *priv)
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{
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	return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf;
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}

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static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
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{
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	return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
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}

static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
{
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	return readl_relaxed(priv->reg_base + reg);
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}

static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
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			      u32 value)
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{
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	writel_relaxed(value, priv->reg_base + reg);
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}

static inline void set_mb_mode_prio(const struct at91_priv *priv,
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				    unsigned int mb, enum at91_mb_mode mode,
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				    u8 prio)
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{
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	const u32 reg_mmr = FIELD_PREP(AT91_MMR_MOT_MASK, mode) |
		FIELD_PREP(AT91_MMR_PRIOR_MASK, prio);

	at91_write(priv, AT91_MMR(mb), reg_mmr);
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}

static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
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			       enum at91_mb_mode mode)
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{
	set_mb_mode_prio(priv, mb, mode, 0);
}

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static inline u32 at91_can_id_to_reg_mid(canid_t can_id)
{
	u32 reg_mid;

	if (can_id & CAN_EFF_FLAG)
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		reg_mid = FIELD_PREP(AT91_MID_MIDVA_MASK | AT91_MID_MIDVB_MASK, can_id) |
			AT91_MID_MIDE;
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	else
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		reg_mid = FIELD_PREP(AT91_MID_MIDVA_MASK, can_id);
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	return reg_mid;
}

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static void at91_setup_mailboxes(struct net_device *dev)
{
	struct at91_priv *priv = netdev_priv(dev);
	unsigned int i;
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	u32 reg_mid;
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	/* Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first
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	 * mailbox is disabled. The next 11 mailboxes are used as a
	 * reception FIFO. The last mailbox is configured with
	 * overwrite option. The overwrite flag indicates a FIFO
	 * overflow.
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	 */
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	reg_mid = at91_can_id_to_reg_mid(priv->mb0_id);
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	for (i = 0; i < get_mb_rx_first(priv); i++) {
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		set_mb_mode(priv, i, AT91_MB_MODE_DISABLED);
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		at91_write(priv, AT91_MID(i), reg_mid);
		at91_write(priv, AT91_MCR(i), 0x0);	/* clear dlc */
	}

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	for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++)
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		set_mb_mode(priv, i, AT91_MB_MODE_RX);
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	set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR);
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	/* reset acceptance mask and id register */
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	for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) {
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		at91_write(priv, AT91_MAM(i), 0x0);
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		at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
	}

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	/* The last 4 mailboxes are used for transmitting. */
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	for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++)
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		set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);

	/* Reset tx and rx helper pointers */
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	priv->tx_next = priv->tx_echo = 0;
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	priv->rx_next = get_mb_rx_first(priv);
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}

static int at91_set_bittiming(struct net_device *dev)
{
	const struct at91_priv *priv = netdev_priv(dev);
	const struct can_bittiming *bt = &priv->can.bittiming;
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	u32 reg_br = 0;

	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
		reg_br |= AT91_BR_SMP;
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	reg_br |= FIELD_PREP(AT91_BR_BRP_MASK, bt->brp - 1) |
		FIELD_PREP(AT91_BR_SJW_MASK, bt->sjw - 1) |
		FIELD_PREP(AT91_BR_PROPAG_MASK, bt->prop_seg - 1) |
		FIELD_PREP(AT91_BR_PHASE1_MASK, bt->phase_seg1 - 1) |
		FIELD_PREP(AT91_BR_PHASE2_MASK, bt->phase_seg2 - 1);
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	netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br);
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	at91_write(priv, AT91_BR, reg_br);

	return 0;
}

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static int at91_get_berr_counter(const struct net_device *dev,
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				 struct can_berr_counter *bec)
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{
	const struct at91_priv *priv = netdev_priv(dev);
	u32 reg_ecr = at91_read(priv, AT91_ECR);

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	bec->rxerr = FIELD_GET(AT91_ECR_REC_MASK, reg_ecr);
	bec->txerr = FIELD_GET(AT91_ECR_TEC_MASK, reg_ecr);
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	return 0;
}

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static void at91_chip_start(struct net_device *dev)
{
	struct at91_priv *priv = netdev_priv(dev);
	u32 reg_mr, reg_ier;

	/* disable interrupts */
	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);

	/* disable chip */
	reg_mr = at91_read(priv, AT91_MR);
	at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);

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	at91_set_bittiming(dev);
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	at91_setup_mailboxes(dev);

	/* enable chip */
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	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
		reg_mr = AT91_MR_CANEN | AT91_MR_ABM;
	else
		reg_mr = AT91_MR_CANEN;
	at91_write(priv, AT91_MR, reg_mr);
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	priv->can.state = CAN_STATE_ERROR_ACTIVE;

	/* Enable interrupts */
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	reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
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	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
	at91_write(priv, AT91_IER, reg_ier);
}

static void at91_chip_stop(struct net_device *dev, enum can_state state)
{
	struct at91_priv *priv = netdev_priv(dev);
	u32 reg_mr;

	/* disable interrupts */
	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);

	reg_mr = at91_read(priv, AT91_MR);
	at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);

	priv->can.state = state;
}

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/* theory of operation:
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 *
 * According to the datasheet priority 0 is the highest priority, 15
 * is the lowest. If two mailboxes have the same priority level the
 * message of the mailbox with the lowest number is sent first.
 *
 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
 * the next mailbox with prio 0, and so on, until all mailboxes are
 * used. Then we start from the beginning with mailbox
 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
 * prio 1. When we reach the last mailbox with prio 15, we have to
 * stop sending, waiting for all messages to be delivered, then start
 * again with mailbox AT91_MB_TX_FIRST prio 0.
 *
 * We use the priv->tx_next as counter for the next transmission
 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
 * encode the mailbox number, the upper 4 bits the mailbox priority:
 *
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 * priv->tx_next = (prio << get_next_prio_shift(priv)) |
 *                 (mb - get_mb_tx_first(priv));
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 *
 */
static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
	struct at91_priv *priv = netdev_priv(dev);
	struct can_frame *cf = (struct can_frame *)skb->data;
	unsigned int mb, prio;
	u32 reg_mid, reg_mcr;

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	if (can_dev_dropped_skb(dev, skb))
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		return NETDEV_TX_OK;

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	mb = get_tx_next_mb(priv);
	prio = get_tx_next_prio(priv);

	if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
		netif_stop_queue(dev);

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		netdev_err(dev, "BUG! TX buffer full when queue awake!\n");
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		return NETDEV_TX_BUSY;
	}
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	reg_mid = at91_can_id_to_reg_mid(cf->can_id);
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	reg_mcr = FIELD_PREP(AT91_MCR_MDLC_MASK, cf->len) |
		AT91_MCR_MTCR;

	if (cf->can_id & CAN_RTR_FLAG)
		reg_mcr |= AT91_MCR_MRTR;
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	/* disable MB while writing ID (see datasheet) */
	set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
	at91_write(priv, AT91_MID(mb), reg_mid);
	set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);

	at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
	at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));

	/* This triggers transmission */
	at91_write(priv, AT91_MCR(mb), reg_mcr);

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	/* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
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	can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv), 0);
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	/* we have to stop the queue and deliver all messages in case
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	 * of a prio+mb counter wrap around. This is the case if
	 * tx_next buffer prio and mailbox equals 0.
	 *
	 * also stop the queue if next buffer is still in use
	 * (== not ready)
	 */
	priv->tx_next++;
	if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
	      AT91_MSR_MRDY) ||
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	    (priv->tx_next & get_next_mask(priv)) == 0)
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		netif_stop_queue(dev);

	/* Enable interrupt for this mailbox */
	at91_write(priv, AT91_IER, 1 << mb);

	return NETDEV_TX_OK;
}

/**
 * at91_activate_rx_low - activate lower rx mailboxes
 * @priv: a91 context
 *
 * Reenables the lower mailboxes for reception of new CAN messages
 */
static inline void at91_activate_rx_low(const struct at91_priv *priv)
{
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	u32 mask = get_mb_rx_low_mask(priv);
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	at91_write(priv, AT91_TCR, mask);
}

/**
 * at91_activate_rx_mb - reactive single rx mailbox
 * @priv: a91 context
 * @mb: mailbox to reactivate
 *
 * Reenables given mailbox for reception of new CAN messages
 */
static inline void at91_activate_rx_mb(const struct at91_priv *priv,
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				       unsigned int mb)
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{
	u32 mask = 1 << mb;
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	at91_write(priv, AT91_TCR, mask);
}

/**
 * at91_rx_overflow_err - send error frame due to rx overflow
 * @dev: net device
 */
static void at91_rx_overflow_err(struct net_device *dev)
{
	struct net_device_stats *stats = &dev->stats;
	struct sk_buff *skb;
	struct can_frame *cf;

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	netdev_dbg(dev, "RX buffer overflow\n");
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	stats->rx_over_errors++;
	stats->rx_errors++;

	skb = alloc_can_err_skb(dev, &cf);
	if (unlikely(!skb))
		return;

	cf->can_id |= CAN_ERR_CRTL;
	cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;

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	netif_receive_skb(skb);
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}

/**
 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
 * @dev: net device
 * @mb: mailbox number to read from
 * @cf: can frame where to store message
 *
 * Reads a CAN message from the given mailbox and stores data into
 * given can frame. "mb" and "cf" must be valid.
 */
static void at91_read_mb(struct net_device *dev, unsigned int mb,
597
			 struct can_frame *cf)
598 599 600 601 602 603
{
	const struct at91_priv *priv = netdev_priv(dev);
	u32 reg_msr, reg_mid;

	reg_mid = at91_read(priv, AT91_MID(mb));
	if (reg_mid & AT91_MID_MIDE)
604 605
		cf->can_id = FIELD_GET(AT91_MID_MIDVA_MASK | AT91_MID_MIDVB_MASK, reg_mid) |
			CAN_EFF_FLAG;
606
	else
607
		cf->can_id = FIELD_GET(AT91_MID_MIDVA_MASK, reg_mid);
608 609

	reg_msr = at91_read(priv, AT91_MSR(mb));
610
	cf->len = can_cc_dlc2len(FIELD_GET(AT91_MSR_MDLC_MASK, reg_msr));
611

612
	if (reg_msr & AT91_MSR_MRTR) {
613
		cf->can_id |= CAN_RTR_FLAG;
614
	} else {
615 616 617
		*(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
		*(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
	}
618

619 620 621
	/* allow RX of extended frames */
	at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);

622
	if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI))
623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648
		at91_rx_overflow_err(dev);
}

/**
 * at91_read_msg - read CAN message from mailbox
 * @dev: net device
 * @mb: mail box to read from
 *
 * Reads a CAN message from given mailbox, and put into linux network
 * RX queue, does all housekeeping chores (stats, ...)
 */
static void at91_read_msg(struct net_device *dev, unsigned int mb)
{
	struct net_device_stats *stats = &dev->stats;
	struct can_frame *cf;
	struct sk_buff *skb;

	skb = alloc_can_skb(dev, &cf);
	if (unlikely(!skb)) {
		stats->rx_dropped++;
		return;
	}

	at91_read_mb(dev, mb, cf);

	stats->rx_packets++;
649 650 651
	if (!(cf->can_id & CAN_RTR_FLAG))
		stats->rx_bytes += cf->len;

652
	netif_receive_skb(skb);
653 654 655 656 657 658 659 660 661
}

/**
 * at91_poll_rx - read multiple CAN messages from mailboxes
 * @dev: net device
 * @quota: max number of pkgs we're allowed to receive
 *
 * Theory of Operation:
 *
662 663 664
 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last())
 * on the chip are reserved for RX. We split them into 2 groups. The
 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last().
665 666 667 668 669 670
 *
 * Like it or not, but the chip always saves a received CAN message
 * into the first free mailbox it finds (starting with the
 * lowest). This makes it very difficult to read the messages in the
 * right order from the chip. This is how we work around that problem:
 *
671
 * The first message goes into mb nr. 1 and issues an interrupt. All
672
 * rx ints are disabled in the interrupt handler and a napi poll is
673
 * scheduled. We read the mailbox, but do _not_ re-enable the mb (to
674 675 676
 * receive another message).
 *
 *    lower mbxs      upper
677 678
 *     ____^______    __^__
 *    /           \  /     \
679
 * +-+-+-+-+-+-+-+-++-+-+-+-+
680
 * | |x|x|x|x|x|x|x|| | | | |
681 682 683
 * +-+-+-+-+-+-+-+-++-+-+-+-+
 *  0 0 0 0 0 0  0 0 0 0 1 1  \ mail
 *  0 1 2 3 4 5  6 7 8 9 0 1  / box
684 685 686 687
 *  ^
 *  |
 *   \
 *     unused, due to chip bug
688 689 690
 *
 * The variable priv->rx_next points to the next mailbox to read a
 * message from. As long we're in the lower mailboxes we just read the
691
 * mailbox but not re-enable it.
692
 *
693
 * With completion of the last of the lower mailboxes, we re-enable the
694 695 696
 * whole first group, but continue to look for filled mailboxes in the
 * upper mailboxes. Imagine the second group like overflow mailboxes,
 * which takes CAN messages if the lower goup is full. While in the
697
 * upper group we re-enable the mailbox right after reading it. Giving
698 699 700 701 702 703 704 705 706 707 708 709 710 711
 * the chip more room to store messages.
 *
 * After finishing we look again in the lower group if we've still
 * quota.
 *
 */
static int at91_poll_rx(struct net_device *dev, int quota)
{
	struct at91_priv *priv = netdev_priv(dev);
	u32 reg_sr = at91_read(priv, AT91_SR);
	const unsigned long *addr = (unsigned long *)&reg_sr;
	unsigned int mb;
	int received = 0;

712 713
	if (priv->rx_next > get_mb_rx_low_last(priv) &&
	    reg_sr & get_mb_rx_low_mask(priv))
714
		netdev_info(dev,
715
			    "order of incoming frames cannot be guaranteed\n");
716 717

 again:
718 719
	for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next);
	     mb < get_mb_tx_first(priv) && quota > 0;
720
	     reg_sr = at91_read(priv, AT91_SR),
721
	     mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) {
722 723 724
		at91_read_msg(dev, mb);

		/* reactivate mailboxes */
725
		if (mb == get_mb_rx_low_last(priv))
726 727
			/* all lower mailboxed, if just finished it */
			at91_activate_rx_low(priv);
728
		else if (mb > get_mb_rx_low_last(priv))
729 730 731 732 733 734 735 736
			/* only the mailbox we read */
			at91_activate_rx_mb(priv, mb);

		received++;
		quota--;
	}

	/* upper group completed, look again in lower */
737
	if (priv->rx_next > get_mb_rx_low_last(priv) &&
738
	    mb > get_mb_rx_last(priv)) {
739
		priv->rx_next = get_mb_rx_first(priv);
740 741
		if (quota > 0)
			goto again;
742 743 744 745 746 747
	}

	return received;
}

static void at91_poll_err_frame(struct net_device *dev,
748
				struct can_frame *cf, u32 reg_sr)
749 750 751 752 753
{
	struct at91_priv *priv = netdev_priv(dev);

	/* CRC error */
	if (reg_sr & AT91_IRQ_CERR) {
754
		netdev_dbg(dev, "CERR irq\n");
755 756 757 758 759 760 761
		dev->stats.rx_errors++;
		priv->can.can_stats.bus_error++;
		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
	}

	/* Stuffing Error */
	if (reg_sr & AT91_IRQ_SERR) {
762
		netdev_dbg(dev, "SERR irq\n");
763 764 765 766 767 768 769 770
		dev->stats.rx_errors++;
		priv->can.can_stats.bus_error++;
		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
		cf->data[2] |= CAN_ERR_PROT_STUFF;
	}

	/* Acknowledgement Error */
	if (reg_sr & AT91_IRQ_AERR) {
771
		netdev_dbg(dev, "AERR irq\n");
772 773 774 775 776 777
		dev->stats.tx_errors++;
		cf->can_id |= CAN_ERR_ACK;
	}

	/* Form error */
	if (reg_sr & AT91_IRQ_FERR) {
778
		netdev_dbg(dev, "FERR irq\n");
779 780 781 782 783 784 785 786
		dev->stats.rx_errors++;
		priv->can.can_stats.bus_error++;
		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
		cf->data[2] |= CAN_ERR_PROT_FORM;
	}

	/* Bit Error */
	if (reg_sr & AT91_IRQ_BERR) {
787
		netdev_dbg(dev, "BERR irq\n");
788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808
		dev->stats.tx_errors++;
		priv->can.can_stats.bus_error++;
		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
		cf->data[2] |= CAN_ERR_PROT_BIT;
	}
}

static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
{
	struct sk_buff *skb;
	struct can_frame *cf;

	if (quota == 0)
		return 0;

	skb = alloc_can_err_skb(dev, &cf);
	if (unlikely(!skb))
		return 0;

	at91_poll_err_frame(dev, cf, reg_sr);

809
	netif_receive_skb(skb);
810 811 812 813 814 815 816 817 818 819 820

	return 1;
}

static int at91_poll(struct napi_struct *napi, int quota)
{
	struct net_device *dev = napi->dev;
	const struct at91_priv *priv = netdev_priv(dev);
	u32 reg_sr = at91_read(priv, AT91_SR);
	int work_done = 0;

821
	if (reg_sr & get_irq_mb_rx(priv))
822 823
		work_done += at91_poll_rx(dev, quota - work_done);

824
	/* The error bits are clear on read,
825 826 827 828 829 830 831 832 833
	 * so use saved value from irq handler.
	 */
	reg_sr |= priv->reg_sr;
	if (reg_sr & AT91_IRQ_ERR_FRAME)
		work_done += at91_poll_err(dev, quota - work_done, reg_sr);

	if (work_done < quota) {
		/* enable IRQs for frame errors and all mailboxes >= rx_next */
		u32 reg_ier = AT91_IRQ_ERR_FRAME;
834

835
		reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next);
836

837
		napi_complete_done(napi, work_done);
838 839 840 841 842 843
		at91_write(priv, AT91_IER, reg_ier);
	}

	return work_done;
}

844
/* theory of operation:
845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872
 *
 * priv->tx_echo holds the number of the oldest can_frame put for
 * transmission into the hardware, but not yet ACKed by the CAN tx
 * complete IRQ.
 *
 * We iterate from priv->tx_echo to priv->tx_next and check if the
 * packet has been transmitted, echo it back to the CAN framework. If
 * we discover a not yet transmitted package, stop looking for more.
 *
 */
static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
{
	struct at91_priv *priv = netdev_priv(dev);
	u32 reg_msr;
	unsigned int mb;

	/* masking of reg_sr not needed, already done by at91_irq */

	for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
		mb = get_tx_echo_mb(priv);

		/* no event in mailbox? */
		if (!(reg_sr & (1 << mb)))
			break;

		/* Disable irq for this TX mailbox */
		at91_write(priv, AT91_IDR, 1 << mb);

873
		/* only echo if mailbox signals us a transfer
874 875 876 877 878
		 * complete (MSR_MRDY). Otherwise it's a tansfer
		 * abort. "can_bus_off()" takes care about the skbs
		 * parked in the echo queue.
		 */
		reg_msr = at91_read(priv, AT91_MSR(mb));
879 880 881 882 883 884 885 886
		if (unlikely(!(reg_msr & AT91_MSR_MRDY &&
			       ~reg_msr & AT91_MSR_MABT)))
			continue;

		/* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
		dev->stats.tx_bytes +=
			can_get_echo_skb(dev, mb - get_mb_tx_first(priv), NULL);
		dev->stats.tx_packets++;
887 888
	}

889
	/* restart queue if we don't have a wrap around but restart if
890 891 892
	 * we get a TX int for the last can frame directly before a
	 * wrap around.
	 */
893 894
	if ((priv->tx_next & get_next_mask(priv)) != 0 ||
	    (priv->tx_echo & get_next_mask(priv)) == 0)
895 896 897 898
		netif_wake_queue(dev);
}

static void at91_irq_err_state(struct net_device *dev,
899
			       struct can_frame *cf, enum can_state new_state)
900 901
{
	struct at91_priv *priv = netdev_priv(dev);
902 903
	u32 reg_idr = 0, reg_ier = 0;
	struct can_berr_counter bec;
904

905
	at91_get_berr_counter(dev, &bec);
906 907 908

	switch (priv->can.state) {
	case CAN_STATE_ERROR_ACTIVE:
909
		/* from: ERROR_ACTIVE
910 911 912 913 914
		 * to  : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
		 * =>  : there was a warning int
		 */
		if (new_state >= CAN_STATE_ERROR_WARNING &&
		    new_state <= CAN_STATE_BUS_OFF) {
915
			netdev_dbg(dev, "Error Warning IRQ\n");
916 917 918
			priv->can.can_stats.error_warning++;

			cf->can_id |= CAN_ERR_CRTL;
919
			cf->data[1] = (bec.txerr > bec.rxerr) ?
920 921 922
				CAN_ERR_CRTL_TX_WARNING :
				CAN_ERR_CRTL_RX_WARNING;
		}
923
		fallthrough;
924
	case CAN_STATE_ERROR_WARNING:
925
		/* from: ERROR_ACTIVE, ERROR_WARNING
926 927 928 929 930
		 * to  : ERROR_PASSIVE, BUS_OFF
		 * =>  : error passive int
		 */
		if (new_state >= CAN_STATE_ERROR_PASSIVE &&
		    new_state <= CAN_STATE_BUS_OFF) {
931
			netdev_dbg(dev, "Error Passive IRQ\n");
932 933 934
			priv->can.can_stats.error_passive++;

			cf->can_id |= CAN_ERR_CRTL;
935
			cf->data[1] = (bec.txerr > bec.rxerr) ?
936 937 938 939 940
				CAN_ERR_CRTL_TX_PASSIVE :
				CAN_ERR_CRTL_RX_PASSIVE;
		}
		break;
	case CAN_STATE_BUS_OFF:
941
		/* from: BUS_OFF
942 943 944 945 946
		 * to  : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
		 */
		if (new_state <= CAN_STATE_ERROR_PASSIVE) {
			cf->can_id |= CAN_ERR_RESTARTED;

947
			netdev_dbg(dev, "restarted\n");
948 949 950 951 952 953 954 955 956 957 958 959 960
			priv->can.can_stats.restarts++;

			netif_carrier_on(dev);
			netif_wake_queue(dev);
		}
		break;
	default:
		break;
	}

	/* process state changes depending on the new state */
	switch (new_state) {
	case CAN_STATE_ERROR_ACTIVE:
961
		/* actually we want to enable AT91_IRQ_WARN here, but
962 963 964 965
		 * it screws up the system under certain
		 * circumstances. so just enable AT91_IRQ_ERRP, thus
		 * the "fallthrough"
		 */
966
		netdev_dbg(dev, "Error Active\n");
967 968
		cf->can_id |= CAN_ERR_PROT;
		cf->data[2] = CAN_ERR_PROT_ACTIVE;
969
		fallthrough;
970
	case CAN_STATE_ERROR_WARNING:
971 972 973 974 975 976 977 978 979 980 981 982 983 984
		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
		reg_ier = AT91_IRQ_ERRP;
		break;
	case CAN_STATE_ERROR_PASSIVE:
		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
		reg_ier = AT91_IRQ_BOFF;
		break;
	case CAN_STATE_BUS_OFF:
		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
			AT91_IRQ_WARN | AT91_IRQ_BOFF;
		reg_ier = 0;

		cf->can_id |= CAN_ERR_BUSOFF;

985
		netdev_dbg(dev, "bus-off\n");
986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002
		netif_carrier_off(dev);
		priv->can.can_stats.bus_off++;

		/* turn off chip, if restart is disabled */
		if (!priv->can.restart_ms) {
			at91_chip_stop(dev, CAN_STATE_BUS_OFF);
			return;
		}
		break;
	default:
		break;
	}

	at91_write(priv, AT91_IDR, reg_idr);
	at91_write(priv, AT91_IER, reg_ier);
}

1003
static int at91_get_state_by_bec(const struct net_device *dev,
1004
				 enum can_state *state)
1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024
{
	struct can_berr_counter bec;
	int err;

	err = at91_get_berr_counter(dev, &bec);
	if (err)
		return err;

	if (bec.txerr < 96 && bec.rxerr < 96)
		*state = CAN_STATE_ERROR_ACTIVE;
	else if (bec.txerr < 128 && bec.rxerr < 128)
		*state = CAN_STATE_ERROR_WARNING;
	else if (bec.txerr < 256 && bec.rxerr < 256)
		*state = CAN_STATE_ERROR_PASSIVE;
	else
		*state = CAN_STATE_BUS_OFF;

	return 0;
}

1025 1026 1027 1028 1029 1030 1031
static void at91_irq_err(struct net_device *dev)
{
	struct at91_priv *priv = netdev_priv(dev);
	struct sk_buff *skb;
	struct can_frame *cf;
	enum can_state new_state;
	u32 reg_sr;
1032
	int err;
1033

1034 1035 1036 1037
	if (at91_is_sam9263(priv)) {
		reg_sr = at91_read(priv, AT91_SR);

		/* we need to look at the unmasked reg_sr */
1038
		if (unlikely(reg_sr & AT91_IRQ_BOFF)) {
1039
			new_state = CAN_STATE_BUS_OFF;
1040
		} else if (unlikely(reg_sr & AT91_IRQ_ERRP)) {
1041
			new_state = CAN_STATE_ERROR_PASSIVE;
1042
		} else if (unlikely(reg_sr & AT91_IRQ_WARN)) {
1043
			new_state = CAN_STATE_ERROR_WARNING;
1044
		} else if (likely(reg_sr & AT91_IRQ_ERRA)) {
1045
			new_state = CAN_STATE_ERROR_ACTIVE;
1046
		} else {
1047 1048 1049 1050 1051 1052 1053
			netdev_err(dev, "BUG! hardware in undefined state\n");
			return;
		}
	} else {
		err = at91_get_state_by_bec(dev, &new_state);
		if (err)
			return;
1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065
	}

	/* state hasn't changed */
	if (likely(new_state == priv->can.state))
		return;

	skb = alloc_can_err_skb(dev, &cf);
	if (unlikely(!skb))
		return;

	at91_irq_err_state(dev, cf, new_state);

1066
	netif_rx(skb);
1067 1068 1069 1070

	priv->can.state = new_state;
}

1071
/* interrupt handler
1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090
 */
static irqreturn_t at91_irq(int irq, void *dev_id)
{
	struct net_device *dev = dev_id;
	struct at91_priv *priv = netdev_priv(dev);
	irqreturn_t handled = IRQ_NONE;
	u32 reg_sr, reg_imr;

	reg_sr = at91_read(priv, AT91_SR);
	reg_imr = at91_read(priv, AT91_IMR);

	/* Ignore masked interrupts */
	reg_sr &= reg_imr;
	if (!reg_sr)
		goto exit;

	handled = IRQ_HANDLED;

	/* Receive or error interrupt? -> napi */
1091
	if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) {
1092
		/* The error bits are clear on read,
1093 1094 1095 1096
		 * save for later use.
		 */
		priv->reg_sr = reg_sr;
		at91_write(priv, AT91_IDR,
1097
			   get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME);
1098 1099 1100 1101
		napi_schedule(&priv->napi);
	}

	/* Transmission complete interrupt */
1102
	if (reg_sr & get_irq_mb_tx(priv))
1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115
		at91_irq_tx(dev, reg_sr);

	at91_irq_err(dev);

 exit:
	return handled;
}

static int at91_open(struct net_device *dev)
{
	struct at91_priv *priv = netdev_priv(dev);
	int err;

1116 1117 1118
	err = clk_prepare_enable(priv->clk);
	if (err)
		return err;
1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141

	/* check or determine and set bittime */
	err = open_candev(dev);
	if (err)
		goto out;

	/* register interrupt handler */
	if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
			dev->name, dev)) {
		err = -EAGAIN;
		goto out_close;
	}

	/* start chip and queuing */
	at91_chip_start(dev);
	napi_enable(&priv->napi);
	netif_start_queue(dev);

	return 0;

 out_close:
	close_candev(dev);
 out:
1142
	clk_disable_unprepare(priv->clk);
1143 1144 1145 1146

	return err;
}

1147
/* stop CAN bus activity
1148 1149 1150 1151 1152 1153 1154 1155 1156 1157
 */
static int at91_close(struct net_device *dev)
{
	struct at91_priv *priv = netdev_priv(dev);

	netif_stop_queue(dev);
	napi_disable(&priv->napi);
	at91_chip_stop(dev, CAN_STATE_STOPPED);

	free_irq(dev->irq, dev);
1158
	clk_disable_unprepare(priv->clk);
1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183

	close_candev(dev);

	return 0;
}

static int at91_set_mode(struct net_device *dev, enum can_mode mode)
{
	switch (mode) {
	case CAN_MODE_START:
		at91_chip_start(dev);
		netif_wake_queue(dev);
		break;

	default:
		return -EOPNOTSUPP;
	}

	return 0;
}

static const struct net_device_ops at91_netdev_ops = {
	.ndo_open	= at91_open,
	.ndo_stop	= at91_close,
	.ndo_start_xmit	= at91_start_xmit,
1184
	.ndo_change_mtu = can_change_mtu,
1185 1186
};

1187 1188 1189 1190
static const struct ethtool_ops at91_ethtool_ops = {
	.get_ts_info = ethtool_op_get_ts_info,
};

1191 1192
static ssize_t mb0_id_show(struct device *dev,
			   struct device_attribute *attr, char *buf)
1193 1194 1195 1196
{
	struct at91_priv *priv = netdev_priv(to_net_dev(dev));

	if (priv->mb0_id & CAN_EFF_FLAG)
1197
		return sysfs_emit(buf, "0x%08x\n", priv->mb0_id);
1198
	else
1199
		return sysfs_emit(buf, "0x%03x\n", priv->mb0_id);
1200 1201
}

1202
static ssize_t mb0_id_store(struct device *dev,
1203 1204
			    struct device_attribute *attr,
			    const char *buf, size_t count)
1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218
{
	struct net_device *ndev = to_net_dev(dev);
	struct at91_priv *priv = netdev_priv(ndev);
	unsigned long can_id;
	ssize_t ret;
	int err;

	rtnl_lock();

	if (ndev->flags & IFF_UP) {
		ret = -EBUSY;
		goto out;
	}

1219
	err = kstrtoul(buf, 0, &can_id);
1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237
	if (err) {
		ret = err;
		goto out;
	}

	if (can_id & CAN_EFF_FLAG)
		can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
	else
		can_id &= CAN_SFF_MASK;

	priv->mb0_id = can_id;
	ret = count;

 out:
	rtnl_unlock();
	return ret;
}

1238
static DEVICE_ATTR_RW(mb0_id);
1239 1240 1241 1242 1243 1244

static struct attribute *at91_sysfs_attrs[] = {
	&dev_attr_mb0_id.attr,
	NULL,
};

1245
static const struct attribute_group at91_sysfs_attr_group = {
1246 1247 1248
	.attrs = at91_sysfs_attrs,
};

1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279
#if defined(CONFIG_OF)
static const struct of_device_id at91_can_dt_ids[] = {
	{
		.compatible = "atmel,at91sam9x5-can",
		.data = &at91_at91sam9x5_data,
	}, {
		.compatible = "atmel,at91sam9263-can",
		.data = &at91_at91sam9263_data,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(of, at91_can_dt_ids);
#endif

static const struct at91_devtype_data *at91_can_get_driver_data(struct platform_device *pdev)
{
	if (pdev->dev.of_node) {
		const struct of_device_id *match;

		match = of_match_node(at91_can_dt_ids, pdev->dev.of_node);
		if (!match) {
			dev_err(&pdev->dev, "no matching node found in dtb\n");
			return NULL;
		}
		return (const struct at91_devtype_data *)match->data;
	}
	return (const struct at91_devtype_data *)
		platform_get_device_id(pdev)->driver_data;
}

1280
static int at91_can_probe(struct platform_device *pdev)
1281
{
1282
	const struct at91_devtype_data *devtype_data;
1283 1284 1285 1286 1287 1288 1289
	struct net_device *dev;
	struct at91_priv *priv;
	struct resource *res;
	struct clk *clk;
	void __iomem *addr;
	int err, irq;

1290 1291 1292 1293 1294 1295
	devtype_data = at91_can_get_driver_data(pdev);
	if (!devtype_data) {
		dev_err(&pdev->dev, "no driver data\n");
		err = -ENODEV;
		goto exit;
	}
1296

1297 1298 1299 1300 1301 1302 1303 1304 1305
	clk = clk_get(&pdev->dev, "can_clk");
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "no clock defined\n");
		err = -ENODEV;
		goto exit;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_irq(pdev, 0);
1306
	if (!res || irq <= 0) {
1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317
		err = -ENODEV;
		goto exit_put;
	}

	if (!request_mem_region(res->start,
				resource_size(res),
				pdev->name)) {
		err = -EBUSY;
		goto exit_put;
	}

1318
	addr = ioremap(res->start, resource_size(res));
1319 1320 1321 1322 1323
	if (!addr) {
		err = -ENOMEM;
		goto exit_release;
	}

1324 1325
	dev = alloc_candev(sizeof(struct at91_priv),
			   1 << devtype_data->tx_shift);
1326 1327 1328 1329 1330 1331
	if (!dev) {
		err = -ENOMEM;
		goto exit_iounmap;
	}

	dev->netdev_ops	= &at91_netdev_ops;
1332
	dev->ethtool_ops = &at91_ethtool_ops;
1333 1334 1335 1336 1337 1338 1339
	dev->irq = irq;
	dev->flags |= IFF_ECHO;

	priv = netdev_priv(dev);
	priv->can.clock.freq = clk_get_rate(clk);
	priv->can.bittiming_const = &at91_bittiming_const;
	priv->can.do_set_mode = at91_set_mode;
1340
	priv->can.do_get_berr_counter = at91_get_berr_counter;
1341 1342
	priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
		CAN_CTRLMODE_LISTENONLY;
1343 1344
	priv->reg_base = addr;
	priv->devtype_data = *devtype_data;
1345
	priv->clk = clk;
1346
	priv->pdata = dev_get_platdata(&pdev->dev);
1347
	priv->mb0_id = 0x7ff;
1348

1349
	netif_napi_add_weight(dev, &priv->napi, at91_poll, get_mb_rx_num(priv));
1350

1351 1352 1353
	if (at91_is_sam9263(priv))
		dev->sysfs_groups[0] = &at91_sysfs_attr_group;

1354
	platform_set_drvdata(pdev, dev);
1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368
	SET_NETDEV_DEV(dev, &pdev->dev);

	err = register_candev(dev);
	if (err) {
		dev_err(&pdev->dev, "registering netdev failed\n");
		goto exit_free;
	}

	dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
		 priv->reg_base, dev->irq);

	return 0;

 exit_free:
1369
	free_candev(dev);
1370 1371 1372 1373 1374 1375 1376 1377 1378 1379
 exit_iounmap:
	iounmap(addr);
 exit_release:
	release_mem_region(res->start, resource_size(res));
 exit_put:
	clk_put(clk);
 exit:
	return err;
}

1380
static void at91_can_remove(struct platform_device *pdev)
1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394
{
	struct net_device *dev = platform_get_drvdata(pdev);
	struct at91_priv *priv = netdev_priv(dev);
	struct resource *res;

	unregister_netdev(dev);

	iounmap(priv->reg_base);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(res->start, resource_size(res));

	clk_put(priv->clk);

1395
	free_candev(dev);
1396 1397
}

1398 1399
static const struct platform_device_id at91_can_id_table[] = {
	{
1400
		.name = "at91sam9x5_can",
1401
		.driver_data = (kernel_ulong_t)&at91_at91sam9x5_data,
1402
	}, {
1403
		.name = "at91_can",
1404
		.driver_data = (kernel_ulong_t)&at91_at91sam9263_data,
1405 1406 1407 1408
	}, {
		/* sentinel */
	}
};
1409
MODULE_DEVICE_TABLE(platform, at91_can_id_table);
1410

1411
static struct platform_driver at91_can_driver = {
1412
	.probe = at91_can_probe,
1413
	.remove_new = at91_can_remove,
1414 1415
	.driver = {
		.name = KBUILD_MODNAME,
1416
		.of_match_table = of_match_ptr(at91_can_dt_ids),
1417
	},
1418
	.id_table = at91_can_id_table,
1419 1420
};

1421
module_platform_driver(at91_can_driver);
1422 1423 1424

MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
MODULE_LICENSE("GPL v2");
1425
MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver");