pinctrl-nomadik.c 43.9 KB
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/*
 * Generic GPIO driver for logic cells found in the Nomadik SoC
 *
 * Copyright (C) 2008,2009 STMicroelectronics
 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
 *   Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
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 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/clk.h>
#include <linux/err.h>
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#include <linux/gpio.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/slab.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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/* Since we request GPIOs from ourself */
#include <linux/pinctrl/consumer.h>
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#include <asm/mach/irq.h>

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#include <plat/pincfg.h>
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#include <plat/gpio-nomadik.h>
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#include "pinctrl-nomadik.h"

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/*
 * The GPIO module in the Nomadik family of Systems-on-Chip is an
 * AMBA device, managing 32 pins and alternate functions.  The logic block
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 * is currently used in the Nomadik and ux500.
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 *
 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
 */

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#define NMK_GPIO_PER_CHIP	32

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struct nmk_gpio_chip {
	struct gpio_chip chip;
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	struct irq_domain *domain;
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	void __iomem *addr;
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	struct clk *clk;
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	unsigned int bank;
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	unsigned int parent_irq;
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	int secondary_parent_irq;
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	u32 (*get_secondary_status)(unsigned int bank);
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	void (*set_ioforce)(bool enable);
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	spinlock_t lock;
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	bool sleepmode;
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	/* Keep track of configured edges */
	u32 edge_rising;
	u32 edge_falling;
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	u32 real_wake;
	u32 rwimsc;
	u32 fwimsc;
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	u32 rimsc;
	u32 fimsc;
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	u32 pull_up;
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	u32 lowemi;
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};

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struct nmk_pinctrl {
	struct device *dev;
	struct pinctrl_dev *pctl;
	const struct nmk_pinctrl_soc_data *soc;
};

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static struct nmk_gpio_chip *
nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];

static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);

#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)

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static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
				unsigned offset, int gpio_mode)
{
	u32 bit = 1 << offset;
	u32 afunc, bfunc;

	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
	if (gpio_mode & NMK_GPIO_ALT_A)
		afunc |= bit;
	if (gpio_mode & NMK_GPIO_ALT_B)
		bfunc |= bit;
	writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
	writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
}

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static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
				unsigned offset, enum nmk_gpio_slpm mode)
{
	u32 bit = 1 << offset;
	u32 slpm;

	slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
	if (mode == NMK_GPIO_SLPM_NOCHANGE)
		slpm |= bit;
	else
		slpm &= ~bit;
	writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
}

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static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
				unsigned offset, enum nmk_gpio_pull pull)
{
	u32 bit = 1 << offset;
	u32 pdis;

	pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
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	if (pull == NMK_GPIO_PULL_NONE) {
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		pdis |= bit;
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		nmk_chip->pull_up &= ~bit;
	} else {
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		pdis &= ~bit;
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	}

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	writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);

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	if (pull == NMK_GPIO_PULL_UP) {
		nmk_chip->pull_up |= bit;
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		writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
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	} else if (pull == NMK_GPIO_PULL_DOWN) {
		nmk_chip->pull_up &= ~bit;
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		writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
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	}
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}

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static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
				  unsigned offset, bool lowemi)
{
	u32 bit = BIT(offset);
	bool enabled = nmk_chip->lowemi & bit;

	if (lowemi == enabled)
		return;

	if (lowemi)
		nmk_chip->lowemi |= bit;
	else
		nmk_chip->lowemi &= ~bit;

	writel_relaxed(nmk_chip->lowemi,
		       nmk_chip->addr + NMK_GPIO_LOWEMI);
}

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static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
				  unsigned offset)
{
	writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
}

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static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
				  unsigned offset, int val)
{
	if (val)
		writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
	else
		writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
}

static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
				  unsigned offset, int val)
{
	writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
	__nmk_gpio_set_output(nmk_chip, offset, val);
}

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static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
				     unsigned offset, int gpio_mode,
				     bool glitch)
{
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	u32 rwimsc = nmk_chip->rwimsc;
	u32 fwimsc = nmk_chip->fwimsc;
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	if (glitch && nmk_chip->set_ioforce) {
		u32 bit = BIT(offset);

		/* Prevent spurious wakeups */
		writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
		writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);

		nmk_chip->set_ioforce(true);
	}

	__nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);

	if (glitch && nmk_chip->set_ioforce) {
		nmk_chip->set_ioforce(false);

		writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
		writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
	}
}

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static void
nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
{
	u32 falling = nmk_chip->fimsc & BIT(offset);
	u32 rising = nmk_chip->rimsc & BIT(offset);
	int gpio = nmk_chip->chip.base + offset;
	int irq = NOMADIK_GPIO_TO_IRQ(gpio);
	struct irq_data *d = irq_get_irq_data(irq);

	if (!rising && !falling)
		return;

	if (!d || !irqd_irq_disabled(d))
		return;

	if (rising) {
		nmk_chip->rimsc &= ~BIT(offset);
		writel_relaxed(nmk_chip->rimsc,
			       nmk_chip->addr + NMK_GPIO_RIMSC);
	}

	if (falling) {
		nmk_chip->fimsc &= ~BIT(offset);
		writel_relaxed(nmk_chip->fimsc,
			       nmk_chip->addr + NMK_GPIO_FIMSC);
	}

	dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
}

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static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
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			     pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
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{
	static const char *afnames[] = {
		[NMK_GPIO_ALT_GPIO]	= "GPIO",
		[NMK_GPIO_ALT_A]	= "A",
		[NMK_GPIO_ALT_B]	= "B",
		[NMK_GPIO_ALT_C]	= "C"
	};
	static const char *pullnames[] = {
		[NMK_GPIO_PULL_NONE]	= "none",
		[NMK_GPIO_PULL_UP]	= "up",
		[NMK_GPIO_PULL_DOWN]	= "down",
		[3] /* illegal */	= "??"
	};
	static const char *slpmnames[] = {
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		[NMK_GPIO_SLPM_INPUT]		= "input/wakeup",
		[NMK_GPIO_SLPM_NOCHANGE]	= "no-change/no-wakeup",
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	};

	int pin = PIN_NUM(cfg);
	int pull = PIN_PULL(cfg);
	int af = PIN_ALT(cfg);
	int slpm = PIN_SLPM(cfg);
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	int output = PIN_DIR(cfg);
	int val = PIN_VAL(cfg);
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	bool glitch = af == NMK_GPIO_ALT_C;
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	dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
		pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
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		output ? "output " : "input",
		output ? (val ? "high" : "low") : "");

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	if (sleep) {
		int slpm_pull = PIN_SLPM_PULL(cfg);
		int slpm_output = PIN_SLPM_DIR(cfg);
		int slpm_val = PIN_SLPM_VAL(cfg);

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		af = NMK_GPIO_ALT_GPIO;

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		/*
		 * The SLPM_* values are normal values + 1 to allow zero to
		 * mean "same as normal".
		 */
		if (slpm_pull)
			pull = slpm_pull - 1;
		if (slpm_output)
			output = slpm_output - 1;
		if (slpm_val)
			val = slpm_val - 1;

		dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
			pin,
			slpm_pull ? pullnames[pull] : "same",
			slpm_output ? (output ? "output" : "input") : "same",
			slpm_val ? (val ? "high" : "low") : "same");
	}

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	if (output)
		__nmk_gpio_make_output(nmk_chip, offset, val);
	else {
		__nmk_gpio_make_input(nmk_chip, offset);
		__nmk_gpio_set_pull(nmk_chip, offset, pull);
	}
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	__nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));

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	/*
	 * If the pin is switching to altfunc, and there was an interrupt
	 * installed on it which has been lazy disabled, actually mask the
	 * interrupt to prevent spurious interrupts that would occur while the
	 * pin is under control of the peripheral.  Only SKE does this.
	 */
	if (af != NMK_GPIO_ALT_GPIO)
		nmk_gpio_disable_lazy_irq(nmk_chip, offset);

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	/*
	 * If we've backed up the SLPM registers (glitch workaround), modify
	 * the backups since they will be restored.
	 */
	if (slpmregs) {
		if (slpm == NMK_GPIO_SLPM_NOCHANGE)
			slpmregs[nmk_chip->bank] |= BIT(offset);
		else
			slpmregs[nmk_chip->bank] &= ~BIT(offset);
	} else
		__nmk_gpio_set_slpm(nmk_chip, offset, slpm);

	__nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
}

/*
 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
 *  - Save SLPM registers
 *  - Set SLPM=0 for the IOs you want to switch and others to 1
 *  - Configure the GPIO registers for the IOs that are being switched
 *  - Set IOFORCE=1
 *  - Modify the AFLSA/B registers for the IOs that are being switched
 *  - Set IOFORCE=0
 *  - Restore SLPM registers
 *  - Any spurious wake up event during switch sequence to be ignored and
 *    cleared
 */
static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
{
	int i;

	for (i = 0; i < NUM_BANKS; i++) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
		unsigned int temp = slpm[i];

		if (!chip)
			break;

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		clk_enable(chip->clk);

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		slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
		writel(temp, chip->addr + NMK_GPIO_SLPC);
	}
}

static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
{
	int i;

	for (i = 0; i < NUM_BANKS; i++) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];

		if (!chip)
			break;

		writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
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		clk_disable(chip->clk);
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	}
}

static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
{
	static unsigned int slpm[NUM_BANKS];
	unsigned long flags;
	bool glitch = false;
	int ret = 0;
	int i;

	for (i = 0; i < num; i++) {
		if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
			glitch = true;
			break;
		}
	}

	spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);

	if (glitch) {
		memset(slpm, 0xff, sizeof(slpm));

		for (i = 0; i < num; i++) {
			int pin = PIN_NUM(cfgs[i]);
			int offset = pin % NMK_GPIO_PER_CHIP;

			if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
				slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
		}

		nmk_gpio_glitch_slpm_init(slpm);
	}

	for (i = 0; i < num; i++) {
		struct nmk_gpio_chip *nmk_chip;
		int pin = PIN_NUM(cfgs[i]);

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		nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
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		if (!nmk_chip) {
			ret = -EINVAL;
			break;
		}

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		clk_enable(nmk_chip->clk);
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		spin_lock(&nmk_chip->lock);
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		__nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
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				 cfgs[i], sleep, glitch ? slpm : NULL);
		spin_unlock(&nmk_chip->lock);
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		clk_disable(nmk_chip->clk);
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	}

	if (glitch)
		nmk_gpio_glitch_slpm_restore(slpm);

	spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);

	return ret;
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}

/**
 * nmk_config_pin - configure a pin's mux attributes
 * @cfg: pin confguration
 *
 * Configures a pin's mode (alternate function or GPIO), its pull up status,
 * and its sleep mode based on the specified configuration.  The @cfg is
 * usually one of the SoC specific macros defined in mach/<soc>-pins.h.  These
 * are constructed using, and can be further enhanced with, the macros in
 * plat/pincfg.h.
 *
 * If a pin's mode is set to GPIO, it is configured as an input to avoid
 * side-effects.  The gpio can be manipulated later using standard GPIO API
 * calls.
 */
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int nmk_config_pin(pin_cfg_t cfg, bool sleep)
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{
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	return __nmk_config_pins(&cfg, 1, sleep);
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}
EXPORT_SYMBOL(nmk_config_pin);

/**
 * nmk_config_pins - configure several pins at once
 * @cfgs: array of pin configurations
 * @num: number of elments in the array
 *
 * Configures several pins using nmk_config_pin().  Refer to that function for
 * further information.
 */
int nmk_config_pins(pin_cfg_t *cfgs, int num)
{
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	return __nmk_config_pins(cfgs, num, false);
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}
EXPORT_SYMBOL(nmk_config_pins);

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int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
{
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	return __nmk_config_pins(cfgs, num, true);
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}
EXPORT_SYMBOL(nmk_config_pins_sleep);

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/**
 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
 * @gpio: pin number
 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
 *
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 * This register is actually in the pinmux layer, not the GPIO block itself.
 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
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 *
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 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
 * entered) regardless of the altfunction selected. Also wake-up detection is
 * ENABLED.
 *
 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
 * (for altfunction GPIO) or respective on-chip peripherals (for other
 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
 *
 * Note that enable_irq_wake() will automatically enable wakeup detection.
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 */
int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
{
	struct nmk_gpio_chip *nmk_chip;
	unsigned long flags;

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	nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
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	if (!nmk_chip)
		return -EINVAL;

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	clk_enable(nmk_chip->clk);
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	spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
	spin_lock(&nmk_chip->lock);

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	__nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
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	spin_unlock(&nmk_chip->lock);
	spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
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	clk_disable(nmk_chip->clk);
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	return 0;
}

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/**
 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
 * @gpio: pin number
 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
 *
 * Enables/disables pull up/down on a specified pin.  This only takes effect if
 * the pin is configured as an input (either explicitly or by the alternate
 * function).
 *
 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
 * configured as an input.  Otherwise, due to the way the controller registers
 * work, this function will change the value output on the pin.
 */
int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
{
	struct nmk_gpio_chip *nmk_chip;
	unsigned long flags;

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	nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
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	if (!nmk_chip)
		return -EINVAL;

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	clk_enable(nmk_chip->clk);
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	spin_lock_irqsave(&nmk_chip->lock, flags);
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	__nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
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	spin_unlock_irqrestore(&nmk_chip->lock, flags);
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	clk_disable(nmk_chip->clk);
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	return 0;
}

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/* Mode functions */
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/**
 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
 * @gpio: pin number
 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
 *	       NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
 *
 * Sets the mode of the specified pin to one of the alternate functions or
 * plain GPIO.
 */
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int nmk_gpio_set_mode(int gpio, int gpio_mode)
{
	struct nmk_gpio_chip *nmk_chip;
	unsigned long flags;

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	nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
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	if (!nmk_chip)
		return -EINVAL;

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	clk_enable(nmk_chip->clk);
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	spin_lock_irqsave(&nmk_chip->lock, flags);
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	__nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
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	spin_unlock_irqrestore(&nmk_chip->lock, flags);
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	clk_disable(nmk_chip->clk);
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	return 0;
}
EXPORT_SYMBOL(nmk_gpio_set_mode);

int nmk_gpio_get_mode(int gpio)
{
	struct nmk_gpio_chip *nmk_chip;
	u32 afunc, bfunc, bit;

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	nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
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	if (!nmk_chip)
		return -EINVAL;

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	bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
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	clk_enable(nmk_chip->clk);

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	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;

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	clk_disable(nmk_chip->clk);

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	return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
}
EXPORT_SYMBOL(nmk_gpio_get_mode);


/* IRQ functions */
static inline int nmk_gpio_get_bitmask(int gpio)
{
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	return 1 << (gpio % NMK_GPIO_PER_CHIP);
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}

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static void nmk_gpio_irq_ack(struct irq_data *d)
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{
	struct nmk_gpio_chip *nmk_chip;

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	nmk_chip = irq_data_get_irq_chip_data(d);
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	if (!nmk_chip)
		return;
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	clk_enable(nmk_chip->clk);
618
	writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
619
	clk_disable(nmk_chip->clk);
620 621
}

622 623 624 625 626
enum nmk_gpio_irq_type {
	NORMAL,
	WAKE,
};

627
static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
628 629
				  int gpio, enum nmk_gpio_irq_type which,
				  bool enable)
630
{
631
	u32 bitmask = nmk_gpio_get_bitmask(gpio);
632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647
	u32 *rimscval;
	u32 *fimscval;
	u32 rimscreg;
	u32 fimscreg;

	if (which == NORMAL) {
		rimscreg = NMK_GPIO_RIMSC;
		fimscreg = NMK_GPIO_FIMSC;
		rimscval = &nmk_chip->rimsc;
		fimscval = &nmk_chip->fimsc;
	} else  {
		rimscreg = NMK_GPIO_RWIMSC;
		fimscreg = NMK_GPIO_FWIMSC;
		rimscval = &nmk_chip->rwimsc;
		fimscval = &nmk_chip->fwimsc;
	}
648

649
	/* we must individually set/clear the two edges */
650
	if (nmk_chip->edge_rising & bitmask) {
651
		if (enable)
652
			*rimscval |= bitmask;
653
		else
654 655
			*rimscval &= ~bitmask;
		writel(*rimscval, nmk_chip->addr + rimscreg);
656 657
	}
	if (nmk_chip->edge_falling & bitmask) {
658
		if (enable)
659
			*fimscval |= bitmask;
660
		else
661 662
			*fimscval &= ~bitmask;
		writel(*fimscval, nmk_chip->addr + fimscreg);
663
	}
664
}
665

666 667 668
static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
				int gpio, bool on)
{
669 670 671 672 673 674
	/*
	 * Ensure WAKEUP_ENABLE is on.  No need to disable it if wakeup is
	 * disabled, since setting SLPM to 1 increases power consumption, and
	 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
	 */
	if (nmk_chip->sleepmode && on) {
675
		__nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base,
676
				    NMK_GPIO_SLPM_WAKEUP_ENABLE);
677 678
	}

679 680 681 682
	__nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
}

static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
683 684 685
{
	struct nmk_gpio_chip *nmk_chip;
	unsigned long flags;
686
	u32 bitmask;
687

688
	nmk_chip = irq_data_get_irq_chip_data(d);
689
	bitmask = nmk_gpio_get_bitmask(d->hwirq);
690
	if (!nmk_chip)
691
		return -EINVAL;
692

693
	clk_enable(nmk_chip->clk);
694 695 696
	spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
	spin_lock(&nmk_chip->lock);

697
	__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
698 699

	if (!(nmk_chip->real_wake & bitmask))
700
		__nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
701 702 703

	spin_unlock(&nmk_chip->lock);
	spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
704
	clk_disable(nmk_chip->clk);
705 706

	return 0;
707 708
}

709
static void nmk_gpio_irq_mask(struct irq_data *d)
710
{
711
	nmk_gpio_irq_maskunmask(d, false);
712
}
713

714
static void nmk_gpio_irq_unmask(struct irq_data *d)
715
{
716
	nmk_gpio_irq_maskunmask(d, true);
717 718
}

719
static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
720
{
721 722
	struct nmk_gpio_chip *nmk_chip;
	unsigned long flags;
723
	u32 bitmask;
724

725
	nmk_chip = irq_data_get_irq_chip_data(d);
726 727
	if (!nmk_chip)
		return -EINVAL;
728
	bitmask = nmk_gpio_get_bitmask(d->hwirq);
729

730
	clk_enable(nmk_chip->clk);
731 732 733
	spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
	spin_lock(&nmk_chip->lock);

734
	if (irqd_irq_disabled(d))
735
		__nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
736 737 738 739 740

	if (on)
		nmk_chip->real_wake |= bitmask;
	else
		nmk_chip->real_wake &= ~bitmask;
741 742 743

	spin_unlock(&nmk_chip->lock);
	spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
744
	clk_disable(nmk_chip->clk);
745 746

	return 0;
747 748
}

749
static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
750
{
751
	bool enabled = !irqd_irq_disabled(d);
752
	bool wake = irqd_is_wakeup_set(d);
753 754 755 756
	struct nmk_gpio_chip *nmk_chip;
	unsigned long flags;
	u32 bitmask;

757
	nmk_chip = irq_data_get_irq_chip_data(d);
758
	bitmask = nmk_gpio_get_bitmask(d->hwirq);
759 760 761 762 763 764 765
	if (!nmk_chip)
		return -EINVAL;
	if (type & IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;
	if (type & IRQ_TYPE_LEVEL_LOW)
		return -EINVAL;

766
	clk_enable(nmk_chip->clk);
767 768
	spin_lock_irqsave(&nmk_chip->lock, flags);

769
	if (enabled)
770
		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
771

772
	if (enabled || wake)
773
		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
774

775 776 777 778 779 780 781 782
	nmk_chip->edge_rising &= ~bitmask;
	if (type & IRQ_TYPE_EDGE_RISING)
		nmk_chip->edge_rising |= bitmask;

	nmk_chip->edge_falling &= ~bitmask;
	if (type & IRQ_TYPE_EDGE_FALLING)
		nmk_chip->edge_falling |= bitmask;

783
	if (enabled)
784
		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
785

786
	if (enabled || wake)
787
		__nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
788

789
	spin_unlock_irqrestore(&nmk_chip->lock, flags);
790
	clk_disable(nmk_chip->clk);
791 792 793 794

	return 0;
}

795 796 797
static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
{
	struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
798

799 800
	clk_enable(nmk_chip->clk);
	nmk_gpio_irq_unmask(d);
801 802 803
	return 0;
}

804 805 806 807 808 809 810 811
static void nmk_gpio_irq_shutdown(struct irq_data *d)
{
	struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);

	nmk_gpio_irq_mask(d);
	clk_disable(nmk_chip->clk);
}

812 813
static struct irq_chip nmk_gpio_irq_chip = {
	.name		= "Nomadik-GPIO",
814 815 816 817 818
	.irq_ack	= nmk_gpio_irq_ack,
	.irq_mask	= nmk_gpio_irq_mask,
	.irq_unmask	= nmk_gpio_irq_unmask,
	.irq_set_type	= nmk_gpio_irq_set_type,
	.irq_set_wake	= nmk_gpio_irq_set_wake,
819 820
	.irq_startup	= nmk_gpio_irq_startup,
	.irq_shutdown	= nmk_gpio_irq_shutdown,
821 822
};

823 824
static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
				   u32 status)
825 826
{
	struct nmk_gpio_chip *nmk_chip;
827
	struct irq_chip *host_chip = irq_get_chip(irq);
828 829
	unsigned int first_irq;

830
	chained_irq_enter(host_chip, desc);
831

832
	nmk_chip = irq_get_handler_data(irq);
833
	first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
834 835 836 837 838
	while (status) {
		int bit = __ffs(status);

		generic_handle_irq(first_irq + bit);
		status &= ~BIT(bit);
839
	}
840

841
	chained_irq_exit(host_chip, desc);
842 843
}

844 845
static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
846
	struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
847 848 849 850 851
	u32 status;

	clk_enable(nmk_chip->clk);
	status = readl(nmk_chip->addr + NMK_GPIO_IS);
	clk_disable(nmk_chip->clk);
852 853 854 855 856 857 858

	__nmk_gpio_irq_handler(irq, desc, status);
}

static void nmk_gpio_secondary_irq_handler(unsigned int irq,
					   struct irq_desc *desc)
{
859
	struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
860 861 862 863 864
	u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);

	__nmk_gpio_irq_handler(irq, desc, status);
}

865 866
static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
{
867 868
	irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
	irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
869 870

	if (nmk_chip->secondary_parent_irq >= 0) {
871
		irq_set_chained_handler(nmk_chip->secondary_parent_irq,
872
					nmk_gpio_secondary_irq_handler);
873
		irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
874 875
	}

876 877 878 879
	return 0;
}

/* I/O Functions */
880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898

static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	/*
	 * Map back to global GPIO space and request muxing, the direction
	 * parameter does not matter for this controller.
	 */
	int gpio = chip->base + offset;

	return pinctrl_request_gpio(gpio);
}

static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	int gpio = chip->base + offset;

	pinctrl_free_gpio(gpio);
}

899 900 901 902 903
static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
{
	struct nmk_gpio_chip *nmk_chip =
		container_of(chip, struct nmk_gpio_chip, chip);

904 905
	clk_enable(nmk_chip->clk);

906
	writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
907 908 909

	clk_disable(nmk_chip->clk);

910 911 912 913 914 915 916 917
	return 0;
}

static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
{
	struct nmk_gpio_chip *nmk_chip =
		container_of(chip, struct nmk_gpio_chip, chip);
	u32 bit = 1 << offset;
918 919 920
	int value;

	clk_enable(nmk_chip->clk);
921

922
	value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
923

924 925 926
	clk_disable(nmk_chip->clk);

	return value;
927 928 929 930 931 932 933 934
}

static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
				int val)
{
	struct nmk_gpio_chip *nmk_chip =
		container_of(chip, struct nmk_gpio_chip, chip);

935 936
	clk_enable(nmk_chip->clk);

937
	__nmk_gpio_set_output(nmk_chip, offset, val);
938 939

	clk_disable(nmk_chip->clk);
940 941
}

942 943 944 945 946 947
static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
				int val)
{
	struct nmk_gpio_chip *nmk_chip =
		container_of(chip, struct nmk_gpio_chip, chip);

948 949
	clk_enable(nmk_chip->clk);

950
	__nmk_gpio_make_output(nmk_chip, offset, val);
951

952 953
	clk_disable(nmk_chip->clk);

954 955 956
	return 0;
}

957 958 959 960 961
static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct nmk_gpio_chip *nmk_chip =
		container_of(chip, struct nmk_gpio_chip, chip);

962
	return irq_find_mapping(nmk_chip->domain, offset);
963 964
}

965 966 967 968
#ifdef CONFIG_DEBUG_FS

#include <linux/seq_file.h>

969 970
static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip,
				  unsigned offset, unsigned gpio)
971
{
972
	const char *label = gpiochip_is_requested(chip, offset);
973 974
	struct nmk_gpio_chip *nmk_chip =
		container_of(chip, struct nmk_gpio_chip, chip);
975 976 977 978
	int mode;
	bool is_out;
	bool pull;
	u32 bit = 1 << offset;
979 980 981 982 983 984 985
	const char *modes[] = {
		[NMK_GPIO_ALT_GPIO]	= "gpio",
		[NMK_GPIO_ALT_A]	= "altA",
		[NMK_GPIO_ALT_B]	= "altB",
		[NMK_GPIO_ALT_C]	= "altC",
	};

986
	clk_enable(nmk_chip->clk);
987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021
	is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
	pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
	mode = nmk_gpio_get_mode(gpio);

	seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
		   gpio, label ?: "(none)",
		   is_out ? "out" : "in ",
		   chip->get
		   ? (chip->get(chip, offset) ? "hi" : "lo")
		   : "?  ",
		   (mode < 0) ? "unknown" : modes[mode],
		   pull ? "pull" : "none");

	if (label && !is_out) {
		int		irq = gpio_to_irq(gpio);
		struct irq_desc	*desc = irq_to_desc(irq);

		/* This races with request_irq(), set_irq_type(),
		 * and set_irq_wake() ... but those are "rare".
		 */
		if (irq >= 0 && desc->action) {
			char *trigger;
			u32 bitmask = nmk_gpio_get_bitmask(gpio);

			if (nmk_chip->edge_rising & bitmask)
				trigger = "edge-rising";
			else if (nmk_chip->edge_falling & bitmask)
				trigger = "edge-falling";
			else
				trigger = "edge-undefined";

			seq_printf(s, " irq-%d %s%s",
				   irq, trigger,
				   irqd_is_wakeup_set(&desc->irq_data)
				   ? " wakeup" : "");
1022
		}
1023 1024 1025 1026 1027 1028 1029 1030
	}
	clk_disable(nmk_chip->clk);
}

static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	unsigned		i;
	unsigned		gpio = chip->base;
1031

1032 1033
	for (i = 0; i < chip->ngpio; i++, gpio++) {
		nmk_gpio_dbg_show_one(s, chip, i, gpio);
1034 1035 1036 1037 1038
		seq_printf(s, "\n");
	}
}

#else
1039 1040 1041 1042 1043
static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
					 struct gpio_chip *chip,
					 unsigned offset, unsigned gpio)
{
}
1044 1045 1046
#define nmk_gpio_dbg_show	NULL
#endif

1047 1048
/* This structure is replicated for each GPIO block allocated at probe time */
static struct gpio_chip nmk_gpio_template = {
1049 1050
	.request		= nmk_gpio_request,
	.free			= nmk_gpio_free,
1051 1052 1053 1054
	.direction_input	= nmk_gpio_make_input,
	.get			= nmk_gpio_get_input,
	.direction_output	= nmk_gpio_make_output,
	.set			= nmk_gpio_set_output,
1055
	.to_irq			= nmk_gpio_to_irq,
1056
	.dbg_show		= nmk_gpio_dbg_show,
1057 1058 1059
	.can_sleep		= 0,
};

1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087
void nmk_gpio_clocks_enable(void)
{
	int i;

	for (i = 0; i < NUM_BANKS; i++) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];

		if (!chip)
			continue;

		clk_enable(chip->clk);
	}
}

void nmk_gpio_clocks_disable(void)
{
	int i;

	for (i = 0; i < NUM_BANKS; i++) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];

		if (!chip)
			continue;

		clk_disable(chip->clk);
	}
}

1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106
/*
 * Called from the suspend/resume path to only keep the real wakeup interrupts
 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
 * and not the rest of the interrupts which we needed to have as wakeups for
 * cpuidle.
 *
 * PM ops are not used since this needs to be done at the end, after all the
 * other drivers are done with their suspend callbacks.
 */
void nmk_gpio_wakeups_suspend(void)
{
	int i;

	for (i = 0; i < NUM_BANKS; i++) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];

		if (!chip)
			break;

1107 1108
		clk_enable(chip->clk);

1109 1110 1111 1112 1113
		writel(chip->rwimsc & chip->real_wake,
		       chip->addr + NMK_GPIO_RWIMSC);
		writel(chip->fwimsc & chip->real_wake,
		       chip->addr + NMK_GPIO_FWIMSC);

1114
		clk_disable(chip->clk);
1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127
	}
}

void nmk_gpio_wakeups_resume(void)
{
	int i;

	for (i = 0; i < NUM_BANKS; i++) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];

		if (!chip)
			break;

1128 1129
		clk_enable(chip->clk);

1130 1131 1132
		writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
		writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);

1133
		clk_disable(chip->clk);
1134 1135 1136
	}
}

1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155
/*
 * Read the pull up/pull down status.
 * A bit set in 'pull_up' means that pull up
 * is selected if pull is enabled in PDIS register.
 * Note: only pull up/down set via this driver can
 * be detected due to HW limitations.
 */
void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
{
	if (gpio_bank < NUM_BANKS) {
		struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];

		if (!chip)
			return;

		*pull_up = chip->pull_up;
	}
}

1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176
int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
			  irq_hw_number_t hwirq)
{
	struct nmk_gpio_chip *nmk_chip = d->host_data;

	if (!nmk_chip)
		return -EINVAL;

	irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
	set_irq_flags(irq, IRQF_VALID);
	irq_set_chip_data(irq, nmk_chip);
	irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);

	return 0;
}

const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
	.map = nmk_gpio_irq_map,
	.xlate = irq_domain_xlate_twocell,
};

1177
static int __devinit nmk_gpio_probe(struct platform_device *dev)
1178
{
1179
	struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1180
	struct device_node *np = dev->dev.of_node;
1181 1182
	struct nmk_gpio_chip *nmk_chip;
	struct gpio_chip *chip;
1183
	struct resource *res;
1184
	struct clk *clk;
1185
	int secondary_irq;
1186
	void __iomem *base;
1187
	int irq;
1188 1189
	int ret;

1190 1191
	if (!pdata && !np) {
		dev_err(&dev->dev, "No platform data or device tree found\n");
1192
		return -ENODEV;
1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205
	}

	if (np) {
		pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
		if (!pdata)
			return -ENOMEM;

		if (of_get_property(np, "supports-sleepmode", NULL))
			pdata->supports_sleepmode = true;

		if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
			dev_err(&dev->dev, "gpio-bank property not found\n");
			ret = -EINVAL;
1206
			goto out;
1207 1208 1209 1210 1211
		}

		pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
		pdata->num_gpio   = NMK_GPIO_PER_CHIP;
	}
1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!res) {
		ret = -ENOENT;
		goto out;
	}

	irq = platform_get_irq(dev, 0);
	if (irq < 0) {
		ret = irq;
		goto out;
	}

1225 1226 1227 1228 1229 1230
	secondary_irq = platform_get_irq(dev, 1);
	if (secondary_irq >= 0 && !pdata->get_secondary_status) {
		ret = -EINVAL;
		goto out;
	}

1231 1232 1233 1234 1235
	if (request_mem_region(res->start, resource_size(res),
			       dev_name(&dev->dev)) == NULL) {
		ret = -EBUSY;
		goto out;
	}
1236

1237 1238 1239 1240 1241 1242
	base = ioremap(res->start, resource_size(res));
	if (!base) {
		ret = -ENOMEM;
		goto out_release;
	}

1243 1244 1245
	clk = clk_get(&dev->dev, NULL);
	if (IS_ERR(clk)) {
		ret = PTR_ERR(clk);
1246
		goto out_unmap;
1247 1248
	}

1249 1250 1251
	nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
	if (!nmk_chip) {
		ret = -ENOMEM;
1252
		goto out_clk;
1253
	}
1254

1255 1256 1257 1258
	/*
	 * The virt address in nmk_chip->addr is in the nomadik register space,
	 * so we can simply convert the resource address, without remapping
	 */
1259
	nmk_chip->bank = dev->id;
1260
	nmk_chip->clk = clk;
1261
	nmk_chip->addr = base;
1262
	nmk_chip->chip = nmk_gpio_template;
1263
	nmk_chip->parent_irq = irq;
1264 1265
	nmk_chip->secondary_parent_irq = secondary_irq;
	nmk_chip->get_secondary_status = pdata->get_secondary_status;
1266
	nmk_chip->set_ioforce = pdata->set_ioforce;
1267
	nmk_chip->sleepmode = pdata->supports_sleepmode;
1268
	spin_lock_init(&nmk_chip->lock);
1269 1270 1271

	chip = &nmk_chip->chip;
	chip->base = pdata->first_gpio;
1272
	chip->ngpio = pdata->num_gpio;
1273
	chip->label = pdata->name ?: dev_name(&dev->dev);
1274 1275 1276
	chip->dev = &dev->dev;
	chip->owner = THIS_MODULE;

1277 1278 1279 1280
	clk_enable(nmk_chip->clk);
	nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
	clk_disable(nmk_chip->clk);

1281
#ifdef CONFIG_OF_GPIO
1282
	chip->of_node = np;
1283
#endif
1284

1285 1286 1287 1288
	ret = gpiochip_add(&nmk_chip->chip);
	if (ret)
		goto out_free;

1289 1290 1291
	BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));

	nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1292

1293
	platform_set_drvdata(dev, nmk_chip);
1294

1295 1296 1297 1298 1299 1300 1301 1302 1303
	nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP,
						NOMADIK_GPIO_TO_IRQ(pdata->first_gpio),
						0, &nmk_gpio_irq_simple_ops, nmk_chip);
	if (!nmk_chip->domain) {
		pr_err("%s: Failed to create irqdomain\n", np->full_name);
		ret = -ENOSYS;
		goto out_free;
	}

1304 1305
	nmk_gpio_init_irq(nmk_chip);

1306 1307
	dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);

1308 1309
	return 0;

1310
out_free:
1311
	kfree(nmk_chip);
1312 1313 1314
out_clk:
	clk_disable(clk);
	clk_put(clk);
1315 1316
out_unmap:
	iounmap(base);
1317 1318 1319
out_release:
	release_mem_region(res->start, resource_size(res));
out:
1320 1321
	dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
		  pdata->first_gpio, pdata->first_gpio+31);
1322 1323 1324
	if (np)
		kfree(pdata);

1325 1326 1327
	return ret;
}

1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353
static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	return npct->soc->ngroups;
}

static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
				       unsigned selector)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	return npct->soc->groups[selector].name;
}

static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
			      const unsigned **pins,
			      unsigned *num_pins)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	*pins = npct->soc->groups[selector].pins;
	*num_pins = npct->soc->groups[selector].npins;
	return 0;
}

1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370
static struct pinctrl_gpio_range *
nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
	int i;

	for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
		struct pinctrl_gpio_range *range;

		range = &npct->soc->gpio_ranges[i];
		if (offset >= range->pin_base &&
		    offset <= (range->pin_base + range->npins - 1))
			return range;
	}
	return NULL;
}

1371 1372 1373
static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
		   unsigned offset)
{
1374 1375 1376 1377 1378 1379 1380 1381 1382 1383
	struct pinctrl_gpio_range *range;
	struct gpio_chip *chip;

	range = nmk_match_gpio_range(pctldev, offset);
	if (!range || !range->gc) {
		seq_printf(s, "invalid pin offset");
		return;
	}
	chip = range->gc;
	nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset);
1384 1385 1386 1387 1388 1389 1390 1391 1392
}

static struct pinctrl_ops nmk_pinctrl_ops = {
	.get_groups_count = nmk_get_groups_cnt,
	.get_group_name = nmk_get_group_name,
	.get_group_pins = nmk_get_group_pins,
	.pin_dbg_show = nmk_pin_dbg_show,
};

1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571
static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	return npct->soc->nfunctions;
}

static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
					 unsigned function)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	return npct->soc->functions[function].name;
}

static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
				   unsigned function,
				   const char * const **groups,
				   unsigned * const num_groups)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	*groups = npct->soc->functions[function].groups;
	*num_groups = npct->soc->functions[function].ngroups;

	return 0;
}

static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
			  unsigned group)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
	const struct nmk_pingroup *g;
	static unsigned int slpm[NUM_BANKS];
	unsigned long flags;
	bool glitch;
	int ret = -EINVAL;
	int i;

	g = &npct->soc->groups[group];

	if (g->altsetting < 0)
		return -EINVAL;

	dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);

	/* Handle this special glitch on altfunction C */
	glitch = (g->altsetting == NMK_GPIO_ALT_C);

	if (glitch) {
		spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);

		/* Initially don't put any pins to sleep when switching */
		memset(slpm, 0xff, sizeof(slpm));

		/*
		 * Then mask the pins that need to be sleeping now when we're
		 * switching to the ALT C function.
		 */
		for (i = 0; i < g->npins; i++)
			slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
		nmk_gpio_glitch_slpm_init(slpm);
	}

	for (i = 0; i < g->npins; i++) {
		struct pinctrl_gpio_range *range;
		struct nmk_gpio_chip *nmk_chip;
		struct gpio_chip *chip;
		unsigned bit;

		range = nmk_match_gpio_range(pctldev, g->pins[i]);
		if (!range) {
			dev_err(npct->dev,
				"invalid pin offset %d in group %s at index %d\n",
				g->pins[i], g->name, i);
			goto out_glitch;
		}
		if (!range->gc) {
			dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
				g->pins[i], g->name, i);
			goto out_glitch;
		}
		chip = range->gc;
		nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
		dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);

		clk_enable(nmk_chip->clk);
		bit = g->pins[i] % NMK_GPIO_PER_CHIP;
		/*
		 * If the pin is switching to altfunc, and there was an
		 * interrupt installed on it which has been lazy disabled,
		 * actually mask the interrupt to prevent spurious interrupts
		 * that would occur while the pin is under control of the
		 * peripheral. Only SKE does this.
		 */
		nmk_gpio_disable_lazy_irq(nmk_chip, bit);

		__nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch);
		clk_disable(nmk_chip->clk);
	}

	/* When all pins are successfully reconfigured we get here */
	ret = 0;

out_glitch:
	if (glitch) {
		nmk_gpio_glitch_slpm_restore(slpm);
		spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
	}

	return ret;
}

static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
			    unsigned function, unsigned group)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
	const struct nmk_pingroup *g;

	g = &npct->soc->groups[group];

	if (g->altsetting < 0)
		return;

	/* Poke out the mux, set the pin to some default state? */
	dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
}

int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
			    struct pinctrl_gpio_range *range,
			    unsigned offset)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
	struct nmk_gpio_chip *nmk_chip;
	struct gpio_chip *chip;
	unsigned bit;

	if (!range) {
		dev_err(npct->dev, "invalid range\n");
		return -EINVAL;
	}
	if (!range->gc) {
		dev_err(npct->dev, "missing GPIO chip in range\n");
		return -EINVAL;
	}
	chip = range->gc;
	nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);

	dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);

	clk_enable(nmk_chip->clk);
	bit = offset % NMK_GPIO_PER_CHIP;
	/* There is no glitch when converting any pin to GPIO */
	__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
	clk_disable(nmk_chip->clk);

	return 0;
}

void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
			   struct pinctrl_gpio_range *range,
			   unsigned offset)
{
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);

	dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
	/* Set the pin to some default state, GPIO is usually default */
}

static struct pinmux_ops nmk_pinmux_ops = {
	.get_functions_count = nmk_pmx_get_funcs_cnt,
	.get_function_name = nmk_pmx_get_func_name,
	.get_function_groups = nmk_pmx_get_func_groups,
	.enable = nmk_pmx_enable,
	.disable = nmk_pmx_disable,
	.gpio_request_enable = nmk_gpio_request_enable,
	.gpio_disable_free = nmk_gpio_disable_free,
};

1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682
int nmk_pin_config_get(struct pinctrl_dev *pctldev,
		       unsigned pin,
		       unsigned long *config)
{
	/* Not implemented */
	return -EINVAL;
}

int nmk_pin_config_set(struct pinctrl_dev *pctldev,
		       unsigned pin,
		       unsigned long config)
{
	static const char *pullnames[] = {
		[NMK_GPIO_PULL_NONE]	= "none",
		[NMK_GPIO_PULL_UP]	= "up",
		[NMK_GPIO_PULL_DOWN]	= "down",
		[3] /* illegal */	= "??"
	};
	static const char *slpmnames[] = {
		[NMK_GPIO_SLPM_INPUT]		= "input/wakeup",
		[NMK_GPIO_SLPM_NOCHANGE]	= "no-change/no-wakeup",
	};
	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
	struct nmk_gpio_chip *nmk_chip;
	struct pinctrl_gpio_range *range;
	struct gpio_chip *chip;
	unsigned bit;

	/*
	 * The pin config contains pin number and altfunction fields, here
	 * we just ignore that part. It's being handled by the framework and
	 * pinmux callback respectively.
	 */
	pin_cfg_t cfg = (pin_cfg_t) config;
	int pull = PIN_PULL(cfg);
	int slpm = PIN_SLPM(cfg);
	int output = PIN_DIR(cfg);
	int val = PIN_VAL(cfg);
	bool lowemi = PIN_LOWEMI(cfg);
	bool gpiomode = PIN_GPIOMODE(cfg);
	bool sleep = PIN_SLEEPMODE(cfg);

	range = nmk_match_gpio_range(pctldev, pin);
	if (!range) {
		dev_err(npct->dev, "invalid pin offset %d\n", pin);
		return -EINVAL;
	}
	if (!range->gc) {
		dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
			pin);
		return -EINVAL;
	}
	chip = range->gc;
	nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);

	if (sleep) {
		int slpm_pull = PIN_SLPM_PULL(cfg);
		int slpm_output = PIN_SLPM_DIR(cfg);
		int slpm_val = PIN_SLPM_VAL(cfg);

		/* All pins go into GPIO mode at sleep */
		gpiomode = true;

		/*
		 * The SLPM_* values are normal values + 1 to allow zero to
		 * mean "same as normal".
		 */
		if (slpm_pull)
			pull = slpm_pull - 1;
		if (slpm_output)
			output = slpm_output - 1;
		if (slpm_val)
			val = slpm_val - 1;

		dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
			pin,
			slpm_pull ? pullnames[pull] : "same",
			slpm_output ? (output ? "output" : "input") : "same",
			slpm_val ? (val ? "high" : "low") : "same");
	}

	dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
		pin, cfg, pullnames[pull], slpmnames[slpm],
		output ? "output " : "input",
		output ? (val ? "high" : "low") : "",
		lowemi ? "on" : "off" );

	clk_enable(nmk_chip->clk);
	bit = pin % NMK_GPIO_PER_CHIP;
	if (gpiomode)
		/* No glitch when going to GPIO mode */
		__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
	if (output)
		__nmk_gpio_make_output(nmk_chip, bit, val);
	else {
		__nmk_gpio_make_input(nmk_chip, bit);
		__nmk_gpio_set_pull(nmk_chip, bit, pull);
	}
	/* TODO: isn't this only applicable on output pins? */
	__nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);

	__nmk_gpio_set_slpm(nmk_chip, bit, slpm);
	clk_disable(nmk_chip->clk);
	return 0;
}

static struct pinconf_ops nmk_pinconf_ops = {
	.pin_config_get = nmk_pin_config_get,
	.pin_config_set = nmk_pin_config_set,
};

1683 1684 1685
static struct pinctrl_desc nmk_pinctrl_desc = {
	.name = "pinctrl-nomadik",
	.pctlops = &nmk_pinctrl_ops,
1686
	.pmxops = &nmk_pinmux_ops,
1687
	.confops = &nmk_pinconf_ops,
1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737
	.owner = THIS_MODULE,
};

static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
{
	const struct platform_device_id *platid = platform_get_device_id(pdev);
	struct nmk_pinctrl *npct;
	int i;

	npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
	if (!npct)
		return -ENOMEM;

	/* Poke in other ASIC variants here */
	if (platid->driver_data == PINCTRL_NMK_DB8500)
		nmk_pinctrl_db8500_init(&npct->soc);

	/*
	 * We need all the GPIO drivers to probe FIRST, or we will not be able
	 * to obtain references to the struct gpio_chip * for them, and we
	 * need this to proceed.
	 */
	for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
		if (!nmk_gpio_chips[i]) {
			dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
			devm_kfree(&pdev->dev, npct);
			return -EPROBE_DEFER;
		}
		npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
	}

	nmk_pinctrl_desc.pins = npct->soc->pins;
	nmk_pinctrl_desc.npins = npct->soc->npins;
	npct->dev = &pdev->dev;
	npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
	if (!npct->pctl) {
		dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
		return -EINVAL;
	}

	/* We will handle a range of GPIO pins */
	for (i = 0; i < npct->soc->gpio_num_ranges; i++)
		pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);

	platform_set_drvdata(pdev, npct);
	dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");

	return 0;
}

1738 1739 1740 1741 1742
static const struct of_device_id nmk_gpio_match[] = {
	{ .compatible = "st,nomadik-gpio", },
	{}
};

1743 1744
static struct platform_driver nmk_gpio_driver = {
	.driver = {
1745 1746
		.owner = THIS_MODULE,
		.name = "gpio",
1747
		.of_match_table = nmk_gpio_match,
1748
	},
1749 1750 1751
	.probe = nmk_gpio_probe,
};

1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765
static const struct platform_device_id nmk_pinctrl_id[] = {
	{ "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
	{ "pinctrl-db8500", PINCTRL_NMK_DB8500 },
};

static struct platform_driver nmk_pinctrl_driver = {
	.driver = {
		.owner = THIS_MODULE,
		.name = "pinctrl-nomadik",
	},
	.probe = nmk_pinctrl_probe,
	.id_table = nmk_pinctrl_id,
};

1766 1767
static int __init nmk_gpio_init(void)
{
1768 1769 1770 1771 1772 1773
	int ret;

	ret = platform_driver_register(&nmk_gpio_driver);
	if (ret)
		return ret;
	return platform_driver_register(&nmk_pinctrl_driver);
1774 1775
}

1776
core_initcall(nmk_gpio_init);
1777 1778 1779 1780

MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
MODULE_DESCRIPTION("Nomadik GPIO Driver");
MODULE_LICENSE("GPL");