pxa2xx-i2s.c 9.79 KB
Newer Older
1 2 3 4 5
/*
 * pxa2xx-i2s.c  --  ALSA Soc Audio Layer
 *
 * Copyright 2005 Wolfson Microelectronics PLC.
 * Author: Liam Girdwood
6
 *         lrg@slimlogic.co.uk
7 8 9 10 11 12 13 14 15 16 17
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
18
#include <linux/clk.h>
19
#include <linux/platform_device.h>
20
#include <linux/io.h>
21 22 23 24
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
25
#include <sound/pxa2xx-lib.h>
26
#include <sound/dmaengine_pcm.h>
27

28 29
#include <mach/hardware.h>
#include <mach/audio.h>
30

31
#include "pxa2xx-i2s.h"
32

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
/*
 * I2S Controller Register and Bit Definitions
 */
#define SACR0		__REG(0x40400000)  /* Global Control Register */
#define SACR1		__REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
#define SASR0		__REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
#define SAIMR		__REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
#define SAICR		__REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
#define SADIV		__REG(0x40400060)  /* Audio Clock Divider Register. */
#define SADR		__REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */

#define SACR0_RFTH(x)	((x) << 12)	/* Rx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_TFTH(x)	((x) << 8)	/* Tx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_STRF	(1 << 5)	/* FIFO Select for EFWR Special Function */
#define SACR0_EFWR	(1 << 4)	/* Enable EFWR Function  */
#define SACR0_RST	(1 << 3)	/* FIFO, i2s Register Reset */
49
#define SACR0_BCKD	(1 << 2)	/* Bit Clock Direction */
50 51
#define SACR0_ENB	(1 << 0)	/* Enable I2S Link */
#define SACR1_ENLBF	(1 << 5)	/* Enable Loopback */
52
#define SACR1_DRPL	(1 << 4)	/* Disable Replaying Function */
53 54 55 56 57 58 59 60 61 62
#define SACR1_DREC	(1 << 3)	/* Disable Recording Function */
#define SACR1_AMSL	(1 << 0)	/* Specify Alternate Mode */

#define SASR0_I2SOFF	(1 << 7)	/* Controller Status */
#define SASR0_ROR	(1 << 6)	/* Rx FIFO Overrun */
#define SASR0_TUR	(1 << 5)	/* Tx FIFO Underrun */
#define SASR0_RFS	(1 << 4)	/* Rx FIFO Service Request */
#define SASR0_TFS	(1 << 3)	/* Tx FIFO Service Request */
#define SASR0_BSY	(1 << 2)	/* I2S Busy */
#define SASR0_RNE	(1 << 1)	/* Rx FIFO Not Empty */
63
#define SASR0_TNF	(1 << 0)	/* Tx FIFO Not Empty */
64 65 66 67 68 69 70 71

#define SAICR_ROR	(1 << 6)	/* Clear Rx FIFO Overrun Interrupt */
#define SAICR_TUR	(1 << 5)	/* Clear Tx FIFO Underrun Interrupt */

#define SAIMR_ROR	(1 << 6)	/* Enable Rx FIFO Overrun Condition Interrupt */
#define SAIMR_TUR	(1 << 5)	/* Enable Tx FIFO Underrun Condition Interrupt */
#define SAIMR_RFS	(1 << 4)	/* Enable Rx FIFO Service Interrupt */
#define SAIMR_TFS	(1 << 3)	/* Enable Tx FIFO Service Interrupt */
72

73 74 75 76 77 78
struct pxa_i2s_port {
	u32 sadiv;
	u32 sacr0;
	u32 sacr1;
	u32 saimr;
	int master;
79
	u32 fmt;
80 81
};
static struct pxa_i2s_port pxa_i2s;
82
static struct clk *clk_i2s;
83
static int clk_ena = 0;
84

85 86 87
static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_out = {
	.addr		= __PREG(SADR),
	.addr_width	= DMA_SLAVE_BUSWIDTH_4_BYTES,
88
	.chan_name	= "tx",
89
	.maxburst	= 32,
90 91
};

92 93 94
static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_in = {
	.addr		= __PREG(SADR),
	.addr_width	= DMA_SLAVE_BUSWIDTH_4_BYTES,
95
	.chan_name	= "rx",
96
	.maxburst	= 32,
97 98
};

99 100
static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
			      struct snd_soc_dai *dai)
101 102
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
103
	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
104

105 106 107
	if (IS_ERR(clk_i2s))
		return PTR_ERR(clk_i2s);

108
	if (!cpu_dai->active)
109 110 111 112 113 114 115 116 117 118 119
		SACR0 = 0;

	return 0;
}

/* wait for I2S controller to be ready */
static int pxa_i2s_wait(void)
{
	int i;

	/* flush the Rx FIFO */
120
	for (i = 0; i < 16; i++)
121 122 123 124
		SADR;
	return 0;
}

125
static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
126
		unsigned int fmt)
127
{
128 129 130 131 132 133 134 135 136
	/* interface format */
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		pxa_i2s.fmt = 0;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		pxa_i2s.fmt = SACR1_AMSL;
		break;
	}
137

138 139
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
140
		pxa_i2s.master = 1;
141 142 143 144 145 146 147 148 149
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		pxa_i2s.master = 0;
		break;
	default:
		break;
	}
	return 0;
}
150

151
static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
152 153 154 155 156 157 158 159 160
		int clk_id, unsigned int freq, int dir)
{
	if (clk_id != PXA2XX_I2S_SYSCLK)
		return -ENODEV;

	return 0;
}

static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
161 162
				struct snd_pcm_hw_params *params,
				struct snd_soc_dai *dai)
163
{
164
	struct snd_dmaengine_dai_dma_data *dma_data;
165

166 167
	if (WARN_ON(IS_ERR(clk_i2s)))
		return -EINVAL;
168
	clk_prepare_enable(clk_i2s);
169
	clk_ena = 1;
170 171 172
	pxa_i2s_wait();

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
173
		dma_data = &pxa2xx_i2s_pcm_stereo_out;
174
	else
175 176
		dma_data = &pxa2xx_i2s_pcm_stereo_in;

177
	snd_soc_dai_set_dma_data(dai, substream, dma_data);
178 179 180 181 182 183 184 185

	/* is port used by another stream */
	if (!(SACR0 & SACR0_ENB)) {
		SACR0 = 0;
		if (pxa_i2s.master)
			SACR0 |= SACR0_BCKD;

		SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
186
		SACR1 |= pxa_i2s.fmt;
187 188 189 190 191 192
	}
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		SAIMR |= SAIMR_TFS;
	else
		SAIMR |= SAIMR_RFS;

193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216
	switch (params_rate(params)) {
	case 8000:
		SADIV = 0x48;
		break;
	case 11025:
		SADIV = 0x34;
		break;
	case 16000:
		SADIV = 0x24;
		break;
	case 22050:
		SADIV = 0x1a;
		break;
	case 44100:
		SADIV = 0xd;
		break;
	case 48000:
		SADIV = 0xc;
		break;
	case 96000: /* not in manual and possibly slightly inaccurate */
		SADIV = 0x6;
		break;
	}

217 218 219
	return 0;
}

220 221
static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			      struct snd_soc_dai *dai)
222 223 224 225 226
{
	int ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
227 228 229 230
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
			SACR1 &= ~SACR1_DRPL;
		else
			SACR1 &= ~SACR1_DREC;
231 232 233 234 235 236 237 238 239 240 241 242 243 244 245
		SACR0 |= SACR0_ENB;
		break;
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

246 247
static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
				struct snd_soc_dai *dai)
248 249 250 251 252 253 254 255 256
{
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		SACR1 |= SACR1_DRPL;
		SAIMR &= ~SAIMR_TFS;
	} else {
		SACR1 |= SACR1_DREC;
		SAIMR &= ~SAIMR_RFS;
	}

257
	if ((SACR1 & (SACR1_DREC | SACR1_DRPL)) == (SACR1_DREC | SACR1_DRPL)) {
258 259
		SACR0 &= ~SACR0_ENB;
		pxa_i2s_wait();
260
		if (clk_ena) {
261
			clk_disable_unprepare(clk_i2s);
262
			clk_ena = 0;
263
		}
264 265 266 267
	}
}

#ifdef CONFIG_PM
268
static int pxa2xx_i2s_suspend(struct snd_soc_dai *dai)
269 270 271 272 273 274 275 276 277 278 279 280 281
{
	/* store registers */
	pxa_i2s.sacr0 = SACR0;
	pxa_i2s.sacr1 = SACR1;
	pxa_i2s.saimr = SAIMR;
	pxa_i2s.sadiv = SADIV;

	/* deactivate link */
	SACR0 &= ~SACR0_ENB;
	pxa_i2s_wait();
	return 0;
}

282
static int pxa2xx_i2s_resume(struct snd_soc_dai *dai)
283 284 285
{
	pxa_i2s_wait();

286
	SACR0 = pxa_i2s.sacr0 & ~SACR0_ENB;
287 288 289
	SACR1 = pxa_i2s.sacr1;
	SAIMR = pxa_i2s.saimr;
	SADIV = pxa_i2s.sadiv;
290 291

	SACR0 = pxa_i2s.sacr0;
292 293 294 295 296 297 298 299 300

	return 0;
}

#else
#define pxa2xx_i2s_suspend	NULL
#define pxa2xx_i2s_resume	NULL
#endif

301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319
static int pxa2xx_i2s_probe(struct snd_soc_dai *dai)
{
	clk_i2s = clk_get(dai->dev, "I2SCLK");
	if (IS_ERR(clk_i2s))
		return PTR_ERR(clk_i2s);

	/*
	 * PXA Developer's Manual:
	 * If SACR0[ENB] is toggled in the middle of a normal operation,
	 * the SACR0[RST] bit must also be set and cleared to reset all
	 * I2S controller registers.
	 */
	SACR0 = SACR0_RST;
	SACR0 = 0;
	/* Make sure RPL and REC are disabled */
	SACR1 = SACR1_DRPL | SACR1_DREC;
	/* Along with FIFO servicing */
	SAIMR &= ~(SAIMR_RFS | SAIMR_TFS);

320 321 322
	snd_soc_dai_init_dma_data(dai, &pxa2xx_i2s_pcm_stereo_out,
		&pxa2xx_i2s_pcm_stereo_in);

323 324 325 326 327 328 329 330 331 332
	return 0;
}

static int  pxa2xx_i2s_remove(struct snd_soc_dai *dai)
{
	clk_put(clk_i2s);
	clk_i2s = ERR_PTR(-ENOENT);
	return 0;
}

333 334 335
#define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
		SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
		SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
336

337
static const struct snd_soc_dai_ops pxa_i2s_dai_ops = {
338 339 340 341 342 343 344 345
	.startup	= pxa2xx_i2s_startup,
	.shutdown	= pxa2xx_i2s_shutdown,
	.trigger	= pxa2xx_i2s_trigger,
	.hw_params	= pxa2xx_i2s_hw_params,
	.set_fmt	= pxa2xx_i2s_set_dai_fmt,
	.set_sysclk	= pxa2xx_i2s_set_dai_sysclk,
};

346 347 348
static struct snd_soc_dai_driver pxa_i2s_dai = {
	.probe = pxa2xx_i2s_probe,
	.remove = pxa2xx_i2s_remove,
349 350 351 352
	.suspend = pxa2xx_i2s_suspend,
	.resume = pxa2xx_i2s_resume,
	.playback = {
		.channels_min = 2,
353 354 355
		.channels_max = 2,
		.rates = PXA2XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
356 357
	.capture = {
		.channels_min = 2,
358 359 360
		.channels_max = 2,
		.rates = PXA2XX_I2S_RATES,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
361
	.ops = &pxa_i2s_dai_ops,
362
	.symmetric_rates = 1,
363 364
};

365 366
static const struct snd_soc_component_driver pxa_i2s_component = {
	.name		= "pxa-i2s",
367 368 369
	.ops		= &pxa2xx_pcm_ops,
	.pcm_new	= pxa2xx_soc_pcm_new,
	.pcm_free	= pxa2xx_pcm_free_dma_buffers,
370 371
};

372
static int pxa2xx_i2s_drv_probe(struct platform_device *pdev)
373
{
374 375
	return devm_snd_soc_register_component(&pdev->dev, &pxa_i2s_component,
					       &pxa_i2s_dai, 1);
376 377 378
}

static struct platform_driver pxa2xx_i2s_driver = {
379
	.probe = pxa2xx_i2s_drv_probe,
380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399

	.driver = {
		.name = "pxa2xx-i2s",
	},
};

static int __init pxa2xx_i2s_init(void)
{
	clk_i2s = ERR_PTR(-ENOENT);
	return platform_driver_register(&pxa2xx_i2s_driver);
}

static void __exit pxa2xx_i2s_exit(void)
{
	platform_driver_unregister(&pxa2xx_i2s_driver);
}

module_init(pxa2xx_i2s_init);
module_exit(pxa2xx_i2s_exit);

400
/* Module information */
401
MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
402 403
MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
MODULE_LICENSE("GPL");
404
MODULE_ALIAS("platform:pxa2xx-i2s");