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/* $Id: he.c,v 1.18 2003/05/06 22:57:15 chas Exp $ */

/*

  he.c

  ForeRunnerHE ATM Adapter driver for ATM on Linux
  Copyright (C) 1999-2001  Naval Research Laboratory

  This library is free software; you can redistribute it and/or
  modify it under the terms of the GNU Lesser General Public
  License as published by the Free Software Foundation; either
  version 2.1 of the License, or (at your option) any later version.

  This library is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  Lesser General Public License for more details.

  You should have received a copy of the GNU Lesser General Public
  License along with this library; if not, write to the Free Software
  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

*/

/*

  he.c

  ForeRunnerHE ATM Adapter driver for ATM on Linux
  Copyright (C) 1999-2001  Naval Research Laboratory

  Permission to use, copy, modify and distribute this software and its
  documentation is hereby granted, provided that both the copyright
  notice and this permission notice appear in all copies of the software,
  derivative works or modified versions, and any portions thereof, and
  that both notices appear in supporting documentation.

  NRL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION AND
  DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES WHATSOEVER
  RESULTING FROM THE USE OF THIS SOFTWARE.

  This driver was written using the "Programmer's Reference Manual for
  ForeRunnerHE(tm)", MANU0361-01 - Rev. A, 08/21/98.

  AUTHORS:
	chas williams <chas@cmf.nrl.navy.mil>
	eric kinzie <ekinzie@cmf.nrl.navy.mil>

  NOTES:
	4096 supported 'connections'
	group 0 is used for all traffic
	interrupt queue 0 is used for all interrupts
Chas Williams's avatar
Chas Williams committed
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	aal0 support (based on work from ulrich.u.muller@nokia.com)
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 */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/skbuff.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <asm/byteorder.h>
#include <asm/uaccess.h>

#include <linux/atmdev.h>
#include <linux/atm.h>
#include <linux/sonet.h>

#define USE_TASKLET
#undef USE_SCATTERGATHER
#undef USE_CHECKSUM_HW			/* still confused about this */
#define USE_RBPS
#undef USE_RBPS_POOL			/* if memory is tight try this */
#undef USE_RBPL_POOL			/* if memory is tight try this */
#define USE_TPD_POOL
/* #undef CONFIG_ATM_HE_USE_SUNI */

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/* compatibility */
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69)
typedef void irqreturn_t;
#define IRQ_NONE
#define IRQ_HANDLED
#define IRQ_RETVAL(x)
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#endif

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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9)
#define __devexit_p(func)		func
#endif

#ifndef MODULE_LICENSE
#define MODULE_LICENSE(x)
#endif

#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3)
#define pci_set_drvdata(pci_dev, data)	(pci_dev)->driver_data = (data)
#define pci_get_drvdata(pci_dev)	(pci_dev)->driver_data
#endif

#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,44)
#define pci_pool_create(a, b, c, d, e)	pci_pool_create(a, b, c, d, e, SLAB_KERNEL)
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#endif

#include "he.h"

#include "suni.h"

#include <linux/atm_he.h>

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#define hprintk(fmt,args...)	printk(KERN_ERR DEV_LABEL "%d: " fmt, he_dev->number , ##args)
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#undef DEBUG
#ifdef DEBUG
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#define HPRINTK(fmt,args...)	printk(KERN_DEBUG DEV_LABEL "%d: " fmt, he_dev->number , ##args)
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#else
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#define HPRINTK(fmt,args...)	do { } while (0)
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#endif /* DEBUG */


/* version definition */

static char *version = "$Id: he.c,v 1.18 2003/05/06 22:57:15 chas Exp $";

/* declarations */

static int he_open(struct atm_vcc *vcc, short vpi, int vci);
static void he_close(struct atm_vcc *vcc);
static int he_send(struct atm_vcc *vcc, struct sk_buff *skb);
static int he_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg);
static irqreturn_t he_irq_handler(int irq, void *dev_id, struct pt_regs *regs);
static void he_tasklet(unsigned long data);
static int he_proc_read(struct atm_dev *dev,loff_t *pos,char *page);
static int he_start(struct atm_dev *dev);
static void he_stop(struct he_dev *dev);
static void he_phy_put(struct atm_dev *, unsigned char, unsigned long);
static unsigned char he_phy_get(struct atm_dev *, unsigned long);

static u8 read_prom_byte(struct he_dev *he_dev, int addr);

/* globals */

struct he_dev *he_devs = NULL;
static short disable64 = -1;
static short nvpibits = -1;
static short nvcibits = -1;
static short rx_skb_reserve = 16;
static short irq_coalesce = 1;
static short sdh = 1;

static struct atmdev_ops he_ops =
{
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	.open =		he_open,
	.close =	he_close,	
	.ioctl =	he_ioctl,	
	.send =		he_send,
	.phy_put =	he_phy_put,
	.phy_get =	he_phy_get,
	.proc_read =	he_proc_read,
	.owner =	THIS_MODULE
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};

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#define he_writel(dev, val, reg)	do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
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#define he_readl(dev, reg)		readl((dev)->membase + (reg))

/* section 2.12 connection memory access */

static __inline__ void
he_writel_internal(struct he_dev *he_dev, unsigned val, unsigned addr,
								unsigned flags)
{
	he_writel(he_dev, val, CON_DAT);
#ifdef CONFIG_IA64_SGI_SN2
	(void) he_readl(he_dev, CON_DAT);
#endif
	he_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL);
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	while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
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}

#define he_writel_rcm(dev, val, reg) 				\
			he_writel_internal(dev, val, reg, CON_CTL_RCM)

#define he_writel_tcm(dev, val, reg) 				\
			he_writel_internal(dev, val, reg, CON_CTL_TCM)

#define he_writel_mbox(dev, val, reg) 				\
			he_writel_internal(dev, val, reg, CON_CTL_MBOX)

static unsigned
he_readl_internal(struct he_dev *he_dev, unsigned addr, unsigned flags)
{
	he_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL);
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	while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
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	return he_readl(he_dev, CON_DAT);
}

#define he_readl_rcm(dev, reg) \
			he_readl_internal(dev, reg, CON_CTL_RCM)

#define he_readl_tcm(dev, reg) \
			he_readl_internal(dev, reg, CON_CTL_TCM)

#define he_readl_mbox(dev, reg) \
			he_readl_internal(dev, reg, CON_CTL_MBOX)


/* figure 2.2 connection id */

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#define he_mkcid(dev, vpi, vci)		(((vpi << (dev)->vcibits) | vci) & 0x1fff)
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/* 2.5.1 per connection transmit state registers */

#define he_writel_tsr0(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 0)
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#define he_readl_tsr0(dev, cid) \
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		he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 0)
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#define he_writel_tsr1(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 1)
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#define he_writel_tsr2(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 2)
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#define he_writel_tsr3(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 3)
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#define he_writel_tsr4(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 4)
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	/* from page 2-20
	 *
	 * NOTE While the transmit connection is active, bits 23 through 0
	 *      of this register must not be written by the host.  Byte
	 *      enables should be used during normal operation when writing
	 *      the most significant byte.
	 */

#define he_writel_tsr4_upper(dev, val, cid) \
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		he_writel_internal(dev, val, CONFIG_TSRA | (cid << 3) | 4, \
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							CON_CTL_TCM \
							| CON_BYTE_DISABLE_2 \
							| CON_BYTE_DISABLE_1 \
							| CON_BYTE_DISABLE_0)

#define he_readl_tsr4(dev, cid) \
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		he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 4)
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#define he_writel_tsr5(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 5)
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#define he_writel_tsr6(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 6)
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#define he_writel_tsr7(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 7)
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#define he_writel_tsr8(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 0)
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#define he_writel_tsr9(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 1)
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#define he_writel_tsr10(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 2)
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#define he_writel_tsr11(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 3)
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#define he_writel_tsr12(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 0)
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#define he_writel_tsr13(dev, val, cid) \
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		he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 1)
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#define he_writel_tsr14(dev, val, cid) \
		he_writel_tcm(dev, val, CONFIG_TSRD | cid)

#define he_writel_tsr14_upper(dev, val, cid) \
		he_writel_internal(dev, val, CONFIG_TSRD | cid, \
							CON_CTL_TCM \
							| CON_BYTE_DISABLE_2 \
							| CON_BYTE_DISABLE_1 \
							| CON_BYTE_DISABLE_0)

/* 2.7.1 per connection receive state registers */

#define he_writel_rsr0(dev, val, cid) \
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		he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 0)
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#define he_readl_rsr0(dev, cid) \
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		he_readl_rcm(dev, 0x00000 | (cid << 3) | 0)
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#define he_writel_rsr1(dev, val, cid) \
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		he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 1)
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#define he_writel_rsr2(dev, val, cid) \
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		he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 2)
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#define he_writel_rsr3(dev, val, cid) \
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		he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 3)
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#define he_writel_rsr4(dev, val, cid) \
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		he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 4)
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#define he_writel_rsr5(dev, val, cid) \
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		he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 5)
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#define he_writel_rsr6(dev, val, cid) \
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		he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 6)
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#define he_writel_rsr7(dev, val, cid) \
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		he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 7)
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static __inline__ struct atm_vcc*
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__find_vcc(struct he_dev *he_dev, unsigned cid)
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{
	struct atm_vcc *vcc;
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	struct hlist_node *node;
	struct sock *s;
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	short vpi;
	int vci;

	vpi = cid >> he_dev->vcibits;
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	vci = cid & ((1 << he_dev->vcibits) - 1);
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	sk_for_each(s, node, &vcc_sklist) {
		vcc = atm_sk(s);
		if (vcc->dev == he_dev->atm_dev &&
		    vcc->vci == vci && vcc->vpi == vpi &&
		    vcc->qos.rxtp.traffic_class != ATM_NONE) {
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				return vcc;
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		}
	}
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	return NULL;
}

static int __devinit
he_init_one(struct pci_dev *pci_dev, const struct pci_device_id *pci_ent)
{
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	struct atm_dev *atm_dev = NULL;
	struct he_dev *he_dev = NULL;
	int err = 0;
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	printk(KERN_INFO "he: %s\n", version);

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	if (pci_enable_device(pci_dev))
		return -EIO;
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	if (pci_set_dma_mask(pci_dev, HE_DMA_MASK) != 0) {
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		printk(KERN_WARNING "he: no suitable dma available\n");
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		err = -EIO;
		goto init_one_failure;
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	}

	atm_dev = atm_dev_register(DEV_LABEL, &he_ops, -1, 0);
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	if (!atm_dev) {
		err = -ENODEV;
		goto init_one_failure;
	}
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	pci_set_drvdata(pci_dev, atm_dev);

	he_dev = (struct he_dev *) kmalloc(sizeof(struct he_dev),
							GFP_KERNEL);
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	if (!he_dev) {
		err = -ENOMEM;
		goto init_one_failure;
	}
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	memset(he_dev, 0, sizeof(struct he_dev));

	he_dev->pci_dev = pci_dev;
	he_dev->atm_dev = atm_dev;
	he_dev->atm_dev->dev_data = he_dev;
	HE_DEV(atm_dev) = he_dev;
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	he_dev->number = atm_dev->number;
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	if (he_start(atm_dev)) {
		he_stop(he_dev);
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		err = -ENODEV;
		goto init_one_failure;
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	}
	he_dev->next = NULL;
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	if (he_devs)
		he_dev->next = he_devs;
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	he_devs = he_dev;
	return 0;
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init_one_failure:
	if (atm_dev)
		atm_dev_deregister(atm_dev);
	if (he_dev)
		kfree(he_dev);
	pci_disable_device(pci_dev);
	return err;
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}

static void __devexit
he_remove_one (struct pci_dev *pci_dev)
{
	struct atm_dev *atm_dev;
	struct he_dev *he_dev;

	atm_dev = pci_get_drvdata(pci_dev);
	he_dev = HE_DEV(atm_dev);

	/* need to remove from he_devs */

	he_stop(he_dev);
	atm_dev_deregister(atm_dev);
	kfree(he_dev);

	pci_set_drvdata(pci_dev, NULL);
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	pci_disable_device(pci_dev);
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}


static unsigned
rate_to_atmf(unsigned rate)		/* cps to atm forum format */
{
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#define NONZERO (1 << 14)
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	unsigned exp = 0;
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	if (rate == 0)
		return 0;
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	rate <<= 9;
	while (rate > 0x3ff) {
		++exp;
		rate >>= 1;
	}
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	return (NONZERO | (exp << 9) | (rate & 0x1ff));
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}

static void __init
he_init_rx_lbfp0(struct he_dev *he_dev)
{
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	unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
	unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
	unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
	unsigned row_offset = he_dev->r0_startrow * he_dev->bytes_per_row;
	
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	lbufd_index = 0;
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	lbm_offset = he_readl(he_dev, RCMLBM_BA);
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	he_writel(he_dev, lbufd_index, RLBF0_H);

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	for (i = 0, lbuf_count = 0; i < he_dev->r0_numbuffs; ++i) {
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		lbufd_index += 2;
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		lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
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		he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
		he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);

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		if (++lbuf_count == lbufs_per_row) {
			lbuf_count = 0;
			row_offset += he_dev->bytes_per_row;
		}
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		lbm_offset += 4;
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	}
		
	he_writel(he_dev, lbufd_index - 2, RLBF0_T);
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	he_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C);
}

static void __init
he_init_rx_lbfp1(struct he_dev *he_dev)
{
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	unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
	unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
	unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
	unsigned row_offset = he_dev->r1_startrow * he_dev->bytes_per_row;
	
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	lbufd_index = 1;
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	lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
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	he_writel(he_dev, lbufd_index, RLBF1_H);

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	for (i = 0, lbuf_count = 0; i < he_dev->r1_numbuffs; ++i) {
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		lbufd_index += 2;
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		lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
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		he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
		he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);

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		if (++lbuf_count == lbufs_per_row) {
			lbuf_count = 0;
			row_offset += he_dev->bytes_per_row;
		}
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		lbm_offset += 4;
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	}
		
	he_writel(he_dev, lbufd_index - 2, RLBF1_T);
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	he_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C);
}

static void __init
he_init_tx_lbfp(struct he_dev *he_dev)
{
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	unsigned i, lbm_offset, lbufd_index, lbuf_addr, lbuf_count;
	unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
	unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
	unsigned row_offset = he_dev->tx_startrow * he_dev->bytes_per_row;
	
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	lbufd_index = he_dev->r0_numbuffs + he_dev->r1_numbuffs;
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	lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
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	he_writel(he_dev, lbufd_index, TLBF_H);

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	for (i = 0, lbuf_count = 0; i < he_dev->tx_numbuffs; ++i) {
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		lbufd_index += 1;
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		lbuf_addr = (row_offset + (lbuf_count * lbuf_bufsize)) / 32;
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		he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
		he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);

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		if (++lbuf_count == lbufs_per_row) {
			lbuf_count = 0;
			row_offset += he_dev->bytes_per_row;
		}
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		lbm_offset += 2;
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	}
		
	he_writel(he_dev, lbufd_index - 1, TLBF_T);
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}

static int __init
he_init_tpdrq(struct he_dev *he_dev)
{
	he_dev->tpdrq_base = pci_alloc_consistent(he_dev->pci_dev,
		CONFIG_TPDRQ_SIZE * sizeof(struct he_tpdrq), &he_dev->tpdrq_phys);
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	if (he_dev->tpdrq_base == NULL) {
Chas Williams's avatar
Chas Williams committed
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		hprintk("failed to alloc tpdrq\n");
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		return -ENOMEM;
	}
	memset(he_dev->tpdrq_base, 0,
				CONFIG_TPDRQ_SIZE * sizeof(struct he_tpdrq));

	he_dev->tpdrq_tail = he_dev->tpdrq_base;
	he_dev->tpdrq_head = he_dev->tpdrq_base;

	he_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H);
	he_writel(he_dev, 0, TPDRQ_T);	
	he_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S);

	return 0;
}

static void __init
he_init_cs_block(struct he_dev *he_dev)
{
	unsigned clock, rate, delta;
	int reg;

	/* 5.1.7 cs block initialization */

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	for (reg = 0; reg < 0x20; ++reg)
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		he_writel_mbox(he_dev, 0x0, CS_STTIM0 + reg);

	/* rate grid timer reload values */

	clock = he_is622(he_dev) ? 66667000 : 50000000;
	rate = he_dev->atm_dev->link_rate;
	delta = rate / 16 / 2;

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	for (reg = 0; reg < 0x10; ++reg) {
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		/* 2.4 internal transmit function
		 *
	 	 * we initialize the first row in the rate grid.
		 * values are period (in clock cycles) of timer
		 */
		unsigned period = clock / rate;

		he_writel_mbox(he_dev, period, CS_TGRLD0 + reg);
		rate -= delta;
	}

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	if (he_is622(he_dev)) {
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		/* table 5.2 (4 cells per lbuf) */
		he_writel_mbox(he_dev, 0x000800fa, CS_ERTHR0);
		he_writel_mbox(he_dev, 0x000c33cb, CS_ERTHR1);
		he_writel_mbox(he_dev, 0x0010101b, CS_ERTHR2);
		he_writel_mbox(he_dev, 0x00181dac, CS_ERTHR3);
		he_writel_mbox(he_dev, 0x00280600, CS_ERTHR4);

		/* table 5.3, 5.4, 5.5, 5.6, 5.7 */
		he_writel_mbox(he_dev, 0x023de8b3, CS_ERCTL0);
		he_writel_mbox(he_dev, 0x1801, CS_ERCTL1);
		he_writel_mbox(he_dev, 0x68b3, CS_ERCTL2);
		he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
		he_writel_mbox(he_dev, 0x68b3, CS_ERSTAT1);
		he_writel_mbox(he_dev, 0x14585, CS_RTFWR);

		he_writel_mbox(he_dev, 0x4680, CS_RTATR);

		/* table 5.8 */
		he_writel_mbox(he_dev, 0x00159ece, CS_TFBSET);
		he_writel_mbox(he_dev, 0x68b3, CS_WCRMAX);
		he_writel_mbox(he_dev, 0x5eb3, CS_WCRMIN);
		he_writel_mbox(he_dev, 0xe8b3, CS_WCRINC);
		he_writel_mbox(he_dev, 0xdeb3, CS_WCRDEC);
		he_writel_mbox(he_dev, 0x68b3, CS_WCRCEIL);

		/* table 5.9 */
		he_writel_mbox(he_dev, 0x5, CS_OTPPER);
		he_writel_mbox(he_dev, 0x14, CS_OTWPER);
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	} else {
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		/* table 5.1 (4 cells per lbuf) */
		he_writel_mbox(he_dev, 0x000400ea, CS_ERTHR0);
		he_writel_mbox(he_dev, 0x00063388, CS_ERTHR1);
		he_writel_mbox(he_dev, 0x00081018, CS_ERTHR2);
		he_writel_mbox(he_dev, 0x000c1dac, CS_ERTHR3);
		he_writel_mbox(he_dev, 0x0014051a, CS_ERTHR4);

		/* table 5.3, 5.4, 5.5, 5.6, 5.7 */
		he_writel_mbox(he_dev, 0x0235e4b1, CS_ERCTL0);
		he_writel_mbox(he_dev, 0x4701, CS_ERCTL1);
		he_writel_mbox(he_dev, 0x64b1, CS_ERCTL2);
		he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
		he_writel_mbox(he_dev, 0x64b1, CS_ERSTAT1);
		he_writel_mbox(he_dev, 0xf424, CS_RTFWR);

		he_writel_mbox(he_dev, 0x4680, CS_RTATR);

		/* table 5.8 */
		he_writel_mbox(he_dev, 0x000563b7, CS_TFBSET);
		he_writel_mbox(he_dev, 0x64b1, CS_WCRMAX);
		he_writel_mbox(he_dev, 0x5ab1, CS_WCRMIN);
		he_writel_mbox(he_dev, 0xe4b1, CS_WCRINC);
		he_writel_mbox(he_dev, 0xdab1, CS_WCRDEC);
		he_writel_mbox(he_dev, 0x64b1, CS_WCRCEIL);

		/* table 5.9 */
		he_writel_mbox(he_dev, 0x6, CS_OTPPER);
		he_writel_mbox(he_dev, 0x1e, CS_OTWPER);
	}

	he_writel_mbox(he_dev, 0x8, CS_OTTLIM);

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	for (reg = 0; reg < 0x8; ++reg)
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		he_writel_mbox(he_dev, 0x0, CS_HGRRT0 + reg);

}

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static int __init
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he_init_cs_block_rcm(struct he_dev *he_dev)
{
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	unsigned (*rategrid)[16][16];
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	unsigned rate, delta;
	int i, j, reg;

	unsigned rate_atmf, exp, man;
	unsigned long long rate_cps;
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	int mult, buf, buf_limit = 4;
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	rategrid = kmalloc( sizeof(unsigned) * 16 * 16, GFP_KERNEL);
	if (!rategrid)
		return -ENOMEM;

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	/* initialize rate grid group table */

	for (reg = 0x0; reg < 0xff; ++reg)
		he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);

	/* initialize rate controller groups */

	for (reg = 0x100; reg < 0x1ff; ++reg)
		he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
	
	/* initialize tNrm lookup table */

	/* the manual makes reference to a routine in a sample driver
	   for proper configuration; fortunately, we only need this
	   in order to support abr connection */
	
	/* initialize rate to group table */

	rate = he_dev->atm_dev->link_rate;
	delta = rate / 32;

	/*
	 * 2.4 transmit internal functions
	 * 
	 * we construct a copy of the rate grid used by the scheduler
	 * in order to construct the rate to group table below
	 */

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	for (j = 0; j < 16; j++) {
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		(*rategrid)[0][j] = rate;
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		rate -= delta;
	}

	for (i = 1; i < 16; i++)
		for (j = 0; j < 16; j++)
			if (i > 14)
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				(*rategrid)[i][j] = (*rategrid)[i - 1][j] / 4;
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			else
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				(*rategrid)[i][j] = (*rategrid)[i - 1][j] / 2;
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	/*
	 * 2.4 transmit internal function
	 *
	 * this table maps the upper 5 bits of exponent and mantissa
	 * of the atm forum representation of the rate into an index
	 * on rate grid  
	 */

	rate_atmf = 0;
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	while (rate_atmf < 0x400) {
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		man = (rate_atmf & 0x1f) << 4;
		exp = rate_atmf >> 5;

		/* 
			instead of '/ 512', use '>> 9' to prevent a call
			to divdu3 on x86 platforms
		*/
		rate_cps = (unsigned long long) (1 << exp) * (man + 512) >> 9;

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		if (rate_cps < 10)
			rate_cps = 10;	/* 2.2.1 minimum payload rate is 10 cps */
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		for (i = 255; i > 0; i--)
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			if ((*rategrid)[i/16][i%16] >= rate_cps)
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				break;	 /* pick nearest rate instead? */
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		/*
		 * each table entry is 16 bits: (rate grid index (8 bits)
		 * and a buffer limit (8 bits)
		 * there are two table entries in each 32-bit register
		 */

#ifdef notdef
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		buf = rate_cps * he_dev->tx_numbuffs /
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				(he_dev->atm_dev->link_rate * 2);
#else
		/* this is pretty, but avoids _divdu3 and is mostly correct */
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		mult = he_dev->atm_dev->link_rate / ATM_OC3_PCR;
		if (rate_cps > (272 * mult))
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			buf = 4;
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		else if (rate_cps > (204 * mult))
			buf = 3;
		else if (rate_cps > (136 * mult))
			buf = 2;
		else if (rate_cps > (68 * mult))
			buf = 1;
		else
			buf = 0;
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#endif
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		if (buf > buf_limit)
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			buf = buf_limit;
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		reg = (reg << 16) | ((i << 8) | buf);
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#define RTGTBL_OFFSET 0x400
	  
		if (rate_atmf & 0x1)
			he_writel_rcm(he_dev, reg,
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				CONFIG_RCMABR + RTGTBL_OFFSET + (rate_atmf >> 1));
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		++rate_atmf;
	}
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	kfree(rategrid);
	return 0;
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}

static int __init
he_init_group(struct he_dev *he_dev, int group)
{
	int i;

#ifdef USE_RBPS
	/* small buffer pool */
#ifdef USE_RBPS_POOL
	he_dev->rbps_pool = pci_pool_create("rbps", he_dev->pci_dev,
			CONFIG_RBPS_BUFSIZE, 8, 0);
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	if (he_dev->rbps_pool == NULL) {
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		hprintk("unable to create rbps pages\n");
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		return -ENOMEM;
	}
#else /* !USE_RBPS_POOL */
	he_dev->rbps_pages = pci_alloc_consistent(he_dev->pci_dev,
		CONFIG_RBPS_SIZE * CONFIG_RBPS_BUFSIZE, &he_dev->rbps_pages_phys);
	if (he_dev->rbps_pages == NULL) {
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		hprintk("unable to create rbps page pool\n");
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		return -ENOMEM;
	}
#endif /* USE_RBPS_POOL */

	he_dev->rbps_base = pci_alloc_consistent(he_dev->pci_dev,
		CONFIG_RBPS_SIZE * sizeof(struct he_rbp), &he_dev->rbps_phys);
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	if (he_dev->rbps_base == NULL) {
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		hprintk("failed to alloc rbps\n");
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		return -ENOMEM;
	}
	memset(he_dev->rbps_base, 0, CONFIG_RBPS_SIZE * sizeof(struct he_rbp));
	he_dev->rbps_virt = kmalloc(CONFIG_RBPS_SIZE * sizeof(struct he_virt), GFP_KERNEL);

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	for (i = 0; i < CONFIG_RBPS_SIZE; ++i) {
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		dma_addr_t dma_handle;
		void *cpuaddr;

#ifdef USE_RBPS_POOL 
		cpuaddr = pci_pool_alloc(he_dev->rbps_pool, SLAB_KERNEL|SLAB_DMA, &dma_handle);
		if (cpuaddr == NULL)
			return -ENOMEM;
#else
		cpuaddr = he_dev->rbps_pages + (i * CONFIG_RBPS_BUFSIZE);
		dma_handle = he_dev->rbps_pages_phys + (i * CONFIG_RBPS_BUFSIZE);
#endif

		he_dev->rbps_virt[i].virt = cpuaddr;
		he_dev->rbps_base[i].status = RBP_LOANED | RBP_SMALLBUF | (i << RBP_INDEX_OFF);
		he_dev->rbps_base[i].phys = dma_handle;

	}
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	he_dev->rbps_tail = &he_dev->rbps_base[CONFIG_RBPS_SIZE - 1];
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	he_writel(he_dev, he_dev->rbps_phys, G0_RBPS_S + (group * 32));
	he_writel(he_dev, RBPS_MASK(he_dev->rbps_tail),
						G0_RBPS_T + (group * 32));
	he_writel(he_dev, CONFIG_RBPS_BUFSIZE/4,
						G0_RBPS_BS + (group * 32));
	he_writel(he_dev,
			RBP_THRESH(CONFIG_RBPS_THRESH) |
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			RBP_QSIZE(CONFIG_RBPS_SIZE - 1) |
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			RBP_INT_ENB,
						G0_RBPS_QI + (group * 32));
#else /* !USE_RBPS */
	he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
	he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
	he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
	he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
						G0_RBPS_BS + (group * 32));
#endif /* USE_RBPS */

	/* large buffer pool */
#ifdef USE_RBPL_POOL
	he_dev->rbpl_pool = pci_pool_create("rbpl", he_dev->pci_dev,
			CONFIG_RBPL_BUFSIZE, 8, 0);
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	if (he_dev->rbpl_pool == NULL) {
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		hprintk("unable to create rbpl pool\n");
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		return -ENOMEM;
	}
#else /* !USE_RBPL_POOL */
	he_dev->rbpl_pages = (void *) pci_alloc_consistent(he_dev->pci_dev,
		CONFIG_RBPL_SIZE * CONFIG_RBPL_BUFSIZE, &he_dev->rbpl_pages_phys);
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	if (he_dev->rbpl_pages == NULL) {
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		hprintk("unable to create rbpl pages\n");
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		return -ENOMEM;
	}
#endif /* USE_RBPL_POOL */

	he_dev->rbpl_base = pci_alloc_consistent(he_dev->pci_dev,
		CONFIG_RBPL_SIZE * sizeof(struct he_rbp), &he_dev->rbpl_phys);
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	if (he_dev->rbpl_base == NULL) {
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		hprintk("failed to alloc rbpl\n");
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		return -ENOMEM;
	}
	memset(he_dev->rbpl_base, 0, CONFIG_RBPL_SIZE * sizeof(struct he_rbp));
	he_dev->rbpl_virt = kmalloc(CONFIG_RBPL_SIZE * sizeof(struct he_virt), GFP_KERNEL);

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	for (i = 0; i < CONFIG_RBPL_SIZE; ++i) {
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		dma_addr_t dma_handle;
		void *cpuaddr;

#ifdef USE_RBPL_POOL
		cpuaddr = pci_pool_alloc(he_dev->rbpl_pool, SLAB_KERNEL|SLAB_DMA, &dma_handle);
		if (cpuaddr == NULL)
			return -ENOMEM;
#else
		cpuaddr = he_dev->rbpl_pages + (i * CONFIG_RBPL_BUFSIZE);
		dma_handle = he_dev->rbpl_pages_phys + (i * CONFIG_RBPL_BUFSIZE);
#endif

		he_dev->rbpl_virt[i].virt = cpuaddr;
		he_dev->rbpl_base[i].status = RBP_LOANED | (i << RBP_INDEX_OFF);
		he_dev->rbpl_base[i].phys = dma_handle;
	}
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	he_dev->rbpl_tail = &he_dev->rbpl_base[CONFIG_RBPL_SIZE - 1];
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	he_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32));
	he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail),
						G0_RBPL_T + (group * 32));
	he_writel(he_dev, CONFIG_RBPL_BUFSIZE/4,
						G0_RBPL_BS + (group * 32));
	he_writel(he_dev,
			RBP_THRESH(CONFIG_RBPL_THRESH) |
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			RBP_QSIZE(CONFIG_RBPL_SIZE - 1) |
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			RBP_INT_ENB,
						G0_RBPL_QI + (group * 32));

	/* rx buffer ready queue */

	he_dev->rbrq_base = pci_alloc_consistent(he_dev->pci_dev,
		CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq), &he_dev->rbrq_phys);
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	if (he_dev->rbrq_base == NULL) {
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		hprintk("failed to allocate rbrq\n");
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		return -ENOMEM;
	}
	memset(he_dev->rbrq_base, 0, CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq));

	he_dev->rbrq_head = he_dev->rbrq_base;
	he_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16));
	he_writel(he_dev, 0, G0_RBRQ_H + (group * 16));
	he_writel(he_dev,
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		RBRQ_THRESH(CONFIG_RBRQ_THRESH) | RBRQ_SIZE(CONFIG_RBRQ_SIZE - 1),
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						G0_RBRQ_Q + (group * 16));
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	if (irq_coalesce) {
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		hprintk("coalescing interrupts\n");
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		he_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7),
						G0_RBRQ_I + (group * 16));
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	} else
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		he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1),
						G0_RBRQ_I + (group * 16));

	/* tx buffer ready queue */

	he_dev->tbrq_base = pci_alloc_consistent(he_dev->pci_dev,
		CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq), &he_dev->tbrq_phys);
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	if (he_dev->tbrq_base == NULL) {
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		hprintk("failed to allocate tbrq\n");
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		return -ENOMEM;
	}
	memset(he_dev->tbrq_base, 0, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq));

	he_dev->tbrq_head = he_dev->tbrq_base;

	he_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16));
	he_writel(he_dev, 0, G0_TBRQ_H + (group * 16));
	he_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16));
	he_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16));

	return 0;
}

static int __init
he_init_irq(struct he_dev *he_dev)
{
	int i;

	/* 2.9.3.5  tail offset for each interrupt queue is located after the
		    end of the interrupt queue */

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	he_dev->irq_base = pci_alloc_consistent(he_dev->pci_dev,
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			(CONFIG_IRQ_SIZE+1) * sizeof(struct he_irq), &he_dev->irq_phys);
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	if (he_dev->irq_base == NULL) {
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		hprintk("failed to allocate irq\n");
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		return -ENOMEM;
	}
	he_dev->irq_tailoffset = (unsigned *)
					&he_dev->irq_base[CONFIG_IRQ_SIZE];
	*he_dev->irq_tailoffset = 0;
	he_dev->irq_head = he_dev->irq_base;
	he_dev->irq_tail = he_dev->irq_base;

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	for (i = 0; i < CONFIG_IRQ_SIZE; ++i)
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		he_dev->irq_base[i].isw = ITYPE_INVALID;

	he_writel(he_dev, he_dev->irq_phys, IRQ0_BASE);
	he_writel(he_dev,
		IRQ_SIZE(CONFIG_IRQ_SIZE) | IRQ_THRESH(CONFIG_IRQ_THRESH),
								IRQ0_HEAD);
	he_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL);
	he_writel(he_dev, 0x0, IRQ0_DATA);

	he_writel(he_dev, 0x0, IRQ1_BASE);
	he_writel(he_dev, 0x0, IRQ1_HEAD);
	he_writel(he_dev, 0x0, IRQ1_CNTL);
	he_writel(he_dev, 0x0, IRQ1_DATA);

	he_writel(he_dev, 0x0, IRQ2_BASE);
	he_writel(he_dev, 0x0, IRQ2_HEAD);
	he_writel(he_dev, 0x0, IRQ2_CNTL);
	he_writel(he_dev, 0x0, IRQ2_DATA);

	he_writel(he_dev, 0x0, IRQ3_BASE);
	he_writel(he_dev, 0x0, IRQ3_HEAD);
	he_writel(he_dev, 0x0, IRQ3_CNTL);
	he_writel(he_dev, 0x0, IRQ3_DATA);

	/* 2.9.3.2 interrupt queue mapping registers */

	he_writel(he_dev, 0x0, GRP_10_MAP);
	he_writel(he_dev, 0x0, GRP_32_MAP);
	he_writel(he_dev, 0x0, GRP_54_MAP);
	he_writel(he_dev, 0x0, GRP_76_MAP);

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	if (request_irq(he_dev->pci_dev->irq, he_irq_handler, SA_INTERRUPT|SA_SHIRQ, DEV_LABEL, he_dev)) {
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		hprintk("irq %d already in use\n", he_dev->pci_dev->irq);
		return -EINVAL;
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	}   
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	he_dev->irq = he_dev->pci_dev->irq;

	return 0;
}

static int __init
he_start(struct atm_dev *dev)
{
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	struct he_dev *he_dev;
	struct pci_dev *pci_dev;
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	u16 command;
	u32 gen_cntl_0, host_cntl, lb_swap;
	u8 cache_size, timer;
	
	unsigned err;
	unsigned int status, reg;
	int i, group;

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	he_dev = HE_DEV(dev);
	pci_dev = he_dev->pci_dev;
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	he_dev->membase = pci_dev->resource[0].start;
	HPRINTK("membase = 0x%lx  irq = %d.\n", he_dev->membase, pci_dev->irq);

	/*
	 * pci bus controller initialization 
	 */

	/* 4.3 pci bus controller-specific initialization */
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	if (pci_read_config_dword(pci_dev, GEN_CNTL_0, &gen_cntl_0) != 0) {
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		hprintk("can't read GEN_CNTL_0\n");
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		return -EINVAL;
	}
	gen_cntl_0 |= (MRL_ENB | MRM_ENB | IGNORE_TIMEOUT);
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	if (pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0) != 0) {
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		hprintk("can't write GEN_CNTL_0.\n");
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		return -EINVAL;
	}

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	if (pci_read_config_word(pci_dev, PCI_COMMAND, &command) != 0) {
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		hprintk("can't read PCI_COMMAND.\n");
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		return -EINVAL;
	}

	command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
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	if (pci_write_config_word(pci_dev, PCI_COMMAND, command) != 0) {
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		hprintk("can't enable memory.\n");
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		return -EINVAL;
	}

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	if (pci_read_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, &cache_size)) {
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		hprintk("can't read cache line size?\n");
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		return -EINVAL;
	}

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	if (cache_size < 16) {
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		cache_size = 16;
		if (pci_write_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, cache_size))
			hprintk("can't set cache line size to %d\n", cache_size);
	}

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	if (pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &timer)) {
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		hprintk("can't read latency timer?\n");
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		return -EINVAL;
	}

	/* from table 3.9
	 *
	 * LAT_TIMER = 1 + AVG_LAT + BURST_SIZE/BUS_SIZE
	 * 
	 * AVG_LAT: The average first data read/write latency [maximum 16 clock cycles]
	 * BURST_SIZE: 1536 bytes (read) for 622, 768 bytes (read) for 155 [192 clock cycles]
	 *
	 */ 
#define LAT_TIMER 209
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	if (timer < LAT_TIMER) {
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		HPRINTK("latency timer was %d, setting to %d\n", timer, LAT_TIMER);
		timer = LAT_TIMER;
		if (pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, timer))
			hprintk("can't set latency timer to %d\n", timer);
	}

	if (!(he_dev->membase = (unsigned long) ioremap(he_dev->membase, HE_REGMAP_SIZE))) {
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		hprintk("can't set up page mapping\n");
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		return -EINVAL;
	}
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	/* 4.4 card reset */
	he_writel(he_dev, 0x0, RESET_CNTL);
	he_writel(he_dev, 0xff, RESET_CNTL);

	udelay(16*1000);	/* 16 ms */
	status = he_readl(he_dev, RESET_CNTL);
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	if ((status & BOARD_RST_STATUS) == 0) {
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		hprintk("reset failed\n");
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		return -EINVAL;
	}

	/* 4.5 set bus width */
	host_cntl = he_readl(he_dev, HOST_CNTL);
	if (host_cntl & PCI_BUS_SIZE64)
		gen_cntl_0 |= ENBL_64;
	else
		gen_cntl_0 &= ~ENBL_64;

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	if (disable64 == 1) {
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		hprintk("disabling 64-bit pci bus transfers\n");
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		gen_cntl_0 &= ~ENBL_64;
	}

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	if (gen_cntl_0 & ENBL_64)
		hprintk("64-bit transfers enabled\n");
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	pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);

	/* 4.7 read prom contents */
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	for (i = 0; i < PROD_ID_LEN; ++i)
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		he_dev->prod_id[i] = read_prom_byte(he_dev, PROD_ID + i);

	he_dev->media = read_prom_byte(he_dev, MEDIA);

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	for (i = 0; i < 6; ++i)
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		dev->esi[i] = read_prom_byte(he_dev, MAC_ADDR + i);

	hprintk("%s%s, %x:%x:%x:%x:%x:%x\n",
				he_dev->prod_id,
					he_dev->media & 0x40 ? "SM" : "MM",
						dev->esi[0],
						dev->esi[1],
						dev->esi[2],
						dev->esi[3],
						dev->esi[4],
						dev->esi[5]);
	he_dev->atm_dev->link_rate = he_is622(he_dev) ?
						ATM_OC12_PCR : ATM_OC3_PCR;

	/* 4.6 set host endianess */
	lb_swap = he_readl(he_dev, LB_SWAP);
	if (he_is622(he_dev))
		lb_swap &= ~XFER_SIZE;		/* 4 cells */
	else
		lb_swap |= XFER_SIZE;		/* 8 cells */
#ifdef __BIG_ENDIAN
	lb_swap |= DESC_WR_SWAP | INTR_SWAP | BIG_ENDIAN_HOST;
#else
	lb_swap &= ~(DESC_WR_SWAP | INTR_SWAP | BIG_ENDIAN_HOST |
			DATA_WR_SWAP | DATA_RD_SWAP | DESC_RD_SWAP);
#endif /* __BIG_ENDIAN */
	he_writel(he_dev, lb_swap, LB_SWAP);

	/* 4.8 sdram controller initialization */
	he_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL);

	/* 4.9 initialize rnum value */
	lb_swap |= SWAP_RNUM_MAX(0xf);
	he_writel(he_dev, lb_swap, LB_SWAP);

	/* 4.10 initialize the interrupt queues */
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	if ((err = he_init_irq(he_dev)) != 0)
		return err;
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#ifdef USE_TASKLET
	tasklet_init(&he_dev->tasklet, he_tasklet, (unsigned long) he_dev);
#endif
	spin_lock_init(&he_dev->global_lock);

	/* 4.11 enable pci bus controller state machines */
	host_cntl |= (OUTFF_ENB | CMDFF_ENB |
				QUICK_RD_RETRY | QUICK_WR_RETRY | PERR_INT_ENB);
	he_writel(he_dev, host_cntl, HOST_CNTL);

	gen_cntl_0 |= INT_PROC_ENBL|INIT_ENB;
	pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);

	/*
	 * atm network controller initialization
	 */

	/* 5.1.1 generic configuration state */

	/*
	 *		local (cell) buffer memory map
	 *                    
	 *             HE155                          HE622
	 *                                                      
	 *        0 ____________1023 bytes  0 _______________________2047 bytes
	 *         |            |            |                   |   |
	 *         |  utility   |            |        rx0        |   |
	 *        5|____________|         255|___________________| u |
	 *        6|            |         256|                   | t |
	 *         |            |            |                   | i |
	 *         |    rx0     |     row    |        tx         | l |
	 *         |            |            |                   | i |
	 *         |            |         767|___________________| t |
	 *      517|____________|         768|                   | y |
	 * row  518|            |            |        rx1        |   |
	 *         |            |        1023|___________________|___|
	 *         |            |
	 *         |    tx      |
	 *         |            |
	 *         |            |
	 *     1535|____________|
	 *     1536|            |
	 *         |    rx1     |
	 *     2047|____________|
	 *
	 */

	/* total 4096 connections */
	he_dev->vcibits = CONFIG_DEFAULT_VCIBITS;
	he_dev->vpibits = CONFIG_DEFAULT_VPIBITS;

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	if (nvpibits != -1 && nvcibits != -1 && nvpibits+nvcibits != HE_MAXCIDBITS) {
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		hprintk("nvpibits + nvcibits != %d\n", HE_MAXCIDBITS);
		return -ENODEV;
	}

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	if (nvpibits != -1) {
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		he_dev->vpibits = nvpibits;
		he_dev->vcibits = HE_MAXCIDBITS - nvpibits;
	}

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	if (nvcibits != -1) {
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		he_dev->vcibits = nvcibits;
		he_dev->vpibits = HE_MAXCIDBITS - nvcibits;
	}


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	if (he_is622(he_dev)) {
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		he_dev->cells_per_row = 40;
		he_dev->bytes_per_row = 2048;
		he_dev->r0_numrows = 256;
		he_dev->tx_numrows = 512;
		he_dev->r1_numrows = 256;
		he_dev->r0_startrow = 0;
		he_dev->tx_startrow = 256;
		he_dev->r1_startrow = 768;
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	} else {
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		he_dev->cells_per_row = 20;
		he_dev->bytes_per_row = 1024;
		he_dev->r0_numrows = 512;
		he_dev->tx_numrows = 1018;
		he_dev->r1_numrows = 512;
		he_dev->r0_startrow = 6;
		he_dev->tx_startrow = 518;
		he_dev->r1_startrow = 1536;
	}

	he_dev->cells_per_lbuf = 4;
	he_dev->buffer_limit = 4;
	he_dev->r0_numbuffs = he_dev->r0_numrows *
				he_dev->cells_per_row / he_dev->cells_per_lbuf;
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	if (he_dev->r0_numbuffs > 2560)
		he_dev->r0_numbuffs = 2560;
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	he_dev->r1_numbuffs = he_dev->r1_numrows *
				he_dev->cells_per_row / he_dev->cells_per_lbuf;
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	if (he_dev->r1_numbuffs > 2560)
		he_dev->r1_numbuffs = 2560;
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	he_dev->tx_numbuffs = he_dev->tx_numrows *
				he_dev->cells_per_row / he_dev->cells_per_lbuf;
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	if (he_dev->tx_numbuffs > 5120)
		he_dev->tx_numbuffs = 5120;
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	/* 5.1.2 configure hardware dependent registers */

	he_writel(he_dev, 
		SLICE_X(0x2) | ARB_RNUM_MAX(0xf) | TH_PRTY(0x3) |
		RH_PRTY(0x3) | TL_PRTY(0x2) | RL_PRTY(0x1) |
		(he_is622(he_dev) ? BUS_MULTI(0x28) : BUS_MULTI(0x46)) |
		(he_is622(he_dev) ? NET_PREF(0x50) : NET_PREF(0x8c)),
								LBARB);

	he_writel(he_dev, BANK_ON |
		(he_is622(he_dev) ? (REF_RATE(0x384) | WIDE_DATA) : REF_RATE(0x150)),
								SDRAMCON);

	he_writel(he_dev,
		(he_is622(he_dev) ? RM_BANK_WAIT(1) : RM_BANK_WAIT(0)) |
						RM_RW_WAIT(1), RCMCONFIG);
	he_writel(he_dev,
		(he_is622(he_dev) ? TM_BANK_WAIT(2) : TM_BANK_WAIT(1)) |
						TM_RW_WAIT(1), TCMCONFIG);

	he_writel(he_dev, he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD, LB_CONFIG);

	he_writel(he_dev, 
		(he_is622(he_dev) ? UT_RD_DELAY(8) : UT_RD_DELAY(0)) |
		(he_is622(he_dev) ? RC_UT_MODE(0) : RC_UT_MODE(1)) |
		RX_VALVP(he_dev->vpibits) |
		RX_VALVC(he_dev->vcibits),			 RC_CONFIG);

	he_writel(he_dev, DRF_THRESH(0x20) |
		(he_is622(he_dev) ? TX_UT_MODE(0) : TX_UT_MODE(1)) |
		TX_VCI_MASK(he_dev->vcibits) |
		LBFREE_CNT(he_dev->tx_numbuffs), 		TX_CONFIG);

	he_writel(he_dev, 0x0, TXAAL5_PROTO);

	he_writel(he_dev, PHY_INT_ENB |
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		(he_is622(he_dev) ? PTMR_PRE(67 - 1) : PTMR_PRE(50 - 1)),
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								RH_CONFIG);

	/* 5.1.3 initialize connection memory */

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	for (i = 0; i < TCM_MEM_SIZE; ++i)
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		he_writel_tcm(he_dev, 0, i);

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	for (i = 0; i < RCM_MEM_SIZE; ++i)
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		he_writel_rcm(he_dev, 0, i);

	/*
	 *	transmit connection memory map
	 *
	 *                  tx memory
	 *          0x0 ___________________
	 *             |                   |
	 *             |                   |
	 *             |       TSRa        |
	 *             |                   |
	 *             |                   |
	 *       0x8000|___________________|
	 *             |                   |
	 *             |       TSRb        |
	 *       0xc000|___________________|
	 *             |                   |
	 *             |       TSRc        |
	 *       0xe000|___________________|
	 *             |       TSRd        |
	 *       0xf000|___________________|
	 *             |       tmABR       |
	 *      0x10000|___________________|
	 *             |                   |
	 *             |       tmTPD       |
	 *             |___________________|
	 *             |                   |
	 *                      ....
	 *      0x1ffff|___________________|
	 *
	 *
	 */

	he_writel(he_dev, CONFIG_TSRB, TSRB_BA);
	he_writel(he_dev, CONFIG_TSRC, TSRC_BA);
	he_writel(he_dev, CONFIG_TSRD, TSRD_BA);
	he_writel(he_dev, CONFIG_TMABR, TMABR_BA);
	he_writel(he_dev, CONFIG_TPDBA, TPD_BA);


	/*
	 *	receive connection memory map
	 *
	 *          0x0 ___________________
	 *             |                   |
	 *             |                   |
	 *             |       RSRa        |
	 *             |                   |
	 *             |                   |
	 *       0x8000|___________________|
	 *             |                   |
	 *             |             rx0/1 |
	 *             |       LBM         |   link lists of local
	 *             |             tx    |   buffer memory 
	 *             |                   |
	 *       0xd000|___________________|
	 *             |                   |
	 *             |      rmABR        |
	 *       0xe000|___________________|
	 *             |                   |
	 *             |       RSRb        |
	 *             |___________________|
	 *             |                   |
	 *                      ....
	 *       0xffff|___________________|
	 */

	he_writel(he_dev, 0x08000, RCMLBM_BA);
	he_writel(he_dev, 0x0e000, RCMRSRB_BA);
	he_writel(he_dev, 0x0d800, RCMABR_BA);

	/* 5.1.4 initialize local buffer free pools linked lists */

	he_init_rx_lbfp0(he_dev);
	he_init_rx_lbfp1(he_dev);

	he_writel(he_dev, 0x0, RLBC_H);
	he_writel(he_dev, 0x0, RLBC_T);
	he_writel(he_dev, 0x0, RLBC_H2);

	he_writel(he_dev, 512, RXTHRSH);	/* 10% of r0+r1 buffers */
	he_writel(he_dev, 256, LITHRSH); 	/* 5% of r0+r1 buffers */

	he_init_tx_lbfp(he_dev);

	he_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA);

	/* 5.1.5 initialize intermediate receive queues */

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	if (he_is622(he_dev)) {
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		he_writel(he_dev, 0x000f, G0_INMQ_S);
		he_writel(he_dev, 0x200f, G0_INMQ_L);

		he_writel(he_dev, 0x001f, G1_INMQ_S);
		he_writel(he_dev, 0x201f, G1_INMQ_L);

		he_writel(he_dev, 0x002f, G2_INMQ_S);
		he_writel(he_dev, 0x202f, G2_INMQ_L);

		he_writel(he_dev, 0x003f, G3_INMQ_S);
		he_writel(he_dev, 0x203f, G3_INMQ_L);

		he_writel(he_dev, 0x004f, G4_INMQ_S);
		he_writel(he_dev, 0x204f, G4_INMQ_L);

		he_writel(he_dev, 0x005f, G5_INMQ_S);
		he_writel(he_dev, 0x205f, G5_INMQ_L);

		he_writel(he_dev, 0x006f, G6_INMQ_S);
		he_writel(he_dev, 0x206f, G6_INMQ_L);

		he_writel(he_dev, 0x007f, G7_INMQ_S);
		he_writel(he_dev, 0x207f, G7_INMQ_L);
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	} else {
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		he_writel(he_dev, 0x0000, G0_INMQ_S);
		he_writel(he_dev, 0x0008, G0_INMQ_L);

		he_writel(he_dev, 0x0001, G1_INMQ_S);
		he_writel(he_dev, 0x0009, G1_INMQ_L);

		he_writel(he_dev, 0x0002, G2_INMQ_S);
		he_writel(he_dev, 0x000a, G2_INMQ_L);

		he_writel(he_dev, 0x0003, G3_INMQ_S);
		he_writel(he_dev, 0x000b, G3_INMQ_L);

		he_writel(he_dev, 0x0004, G4_INMQ_S);
		he_writel(he_dev, 0x000c, G4_INMQ_L);

		he_writel(he_dev, 0x0005, G5_INMQ_S);
		he_writel(he_dev, 0x000d, G5_INMQ_L);

		he_writel(he_dev, 0x0006, G6_INMQ_S);
		he_writel(he_dev, 0x000e, G6_INMQ_L);

		he_writel(he_dev, 0x0007, G7_INMQ_S);
		he_writel(he_dev, 0x000f, G7_INMQ_L);
	}

	/* 5.1.6 application tunable parameters */

	he_writel(he_dev, 0x0, MCC);
	he_writel(he_dev, 0x0, OEC);
	he_writel(he_dev, 0x0, DCC);
	he_writel(he_dev, 0x0, CEC);
	
	/* 5.1.7 cs block initialization */

	he_init_cs_block(he_dev);

	/* 5.1.8 cs block connection memory initialization */
	
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	if (he_init_cs_block_rcm(he_dev) < 0)
		return -ENOMEM;
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	/* 5.1.10 initialize host structures */

	he_init_tpdrq(he_dev);

#ifdef USE_TPD_POOL
	he_dev->tpd_pool = pci_pool_create("tpd", he_dev->pci_dev,
		sizeof(struct he_tpd), TPD_ALIGNMENT, 0);
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	if (he_dev->tpd_pool == NULL) {
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		hprintk("unable to create tpd pci_pool\n");
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		return -ENOMEM;         
	}

	INIT_LIST_HEAD(&he_dev->outstanding_tpds);
#else
	he_dev->tpd_base = (void *) pci_alloc_consistent(he_dev->pci_dev,
			CONFIG_NUMTPDS * sizeof(struct he_tpd), &he_dev->tpd_base_phys);
	if (!he_dev->tpd_base)
		return -ENOMEM;

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	for (i = 0; i < CONFIG_NUMTPDS; ++i) {
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		he_dev->tpd_base[i].status = (i << TPD_ADDR_SHIFT);
		he_dev->tpd_base[i].inuse = 0;
	}
		
	he_dev->tpd_head = he_dev->tpd_base;
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	he_dev->tpd_end = &he_dev->tpd_base[CONFIG_NUMTPDS - 1];
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#endif

	if (he_init_group(he_dev, 0) != 0)
		return -ENOMEM;

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	for (group = 1; group < HE_NUM_GROUPS; ++group) {
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		he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
		he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
		he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
		he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
						G0_RBPS_BS + (group * 32));

		he_writel(he_dev, 0x0, G0_RBPL_S + (group * 32));
		he_writel(he_dev, 0x0, G0_RBPL_T + (group * 32));
		he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
						G0_RBPL_QI + (group * 32));
		he_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32));

		he_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16));
		he_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16));
		he_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0),
						G0_RBRQ_Q + (group * 16));
		he_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16));

		he_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16));
		he_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16));
		he_writel(he_dev, TBRQ_THRESH(0x1),
						G0_TBRQ_THRESH + (group * 16));
		he_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16));
	}

	/* host status page */

	he_dev->hsp = pci_alloc_consistent(he_dev->pci_dev,
				sizeof(struct he_hsp), &he_dev->hsp_phys);
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	if (he_dev->hsp == NULL) {
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		hprintk("failed to allocate host status page\n");
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		return -ENOMEM;
	}
	memset(he_dev->hsp, 0, sizeof(struct he_hsp));
	he_writel(he_dev, he_dev->hsp_phys, HSP_BA);

	/* initialize framer */

#ifdef CONFIG_ATM_HE_USE_SUNI
	suni_init(he_dev->atm_dev);
	if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->start)
		he_dev->atm_dev->phy->start(he_dev->atm_dev);
#endif /* CONFIG_ATM_HE_USE_SUNI */

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	if (sdh) {
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		/* this really should be in suni.c but for now... */

		int val;

		val = he_phy_get(he_dev->atm_dev, SUNI_TPOP_APM);
		val = (val & ~SUNI_TPOP_APM_S) | ( 0x2 << SUNI_TPOP_APM_S_SHIFT);
		he_phy_put(he_dev->atm_dev, val, SUNI_TPOP_APM);
	}

	/* 5.1.12 enable transmit and receive */

	reg = he_readl_mbox(he_dev, CS_ERCTL0);
	reg |= TX_ENABLE|ER_ENABLE;
	he_writel_mbox(he_dev, reg, CS_ERCTL0);

	reg = he_readl(he_dev, RC_CONFIG);
	reg |= RX_ENABLE;
	he_writel(he_dev, reg, RC_CONFIG);

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	for (i = 0; i < HE_NUM_CS_STPER; ++i) {
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		he_dev->cs_stper[i].inuse = 0;
		he_dev->cs_stper[i].pcr = -1;
	}
	he_dev->total_bw = 0;


	/* atm linux initialization */

	he_dev->atm_dev->ci_range.vpi_bits = he_dev->vpibits;
	he_dev->atm_dev->ci_range.vci_bits = he_dev->vcibits;

	he_dev->irq_peak = 0;
	he_dev->rbrq_peak = 0;
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	he_dev->rbpl_peak = 0;
	he_dev->tbrq_peak = 0;
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	HPRINTK("hell bent for leather!\n");

	return 0;
}

static void
he_stop(struct he_dev *he_dev)
{
	u16 command;
	u32 gen_cntl_0, reg;
	struct pci_dev *pci_dev;

	pci_dev = he_dev->pci_dev;

	/* disable interrupts */

1599
	if (he_dev->membase) {
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		pci_read_config_dword(pci_dev, GEN_CNTL_0, &gen_cntl_0);
		gen_cntl_0 &= ~(INT_PROC_ENBL | INIT_ENB);
		pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0);

#ifdef USE_TASKLET
		tasklet_disable(&he_dev->tasklet);
#endif

		/* disable recv and transmit */

		reg = he_readl_mbox(he_dev, CS_ERCTL0);
		reg &= ~(TX_ENABLE|ER_ENABLE);
		he_writel_mbox(he_dev, reg, CS_ERCTL0);

		reg = he_readl(he_dev, RC_CONFIG);
		reg &= ~(RX_ENABLE);
		he_writel(he_dev, reg, RC_CONFIG);
	}

#ifdef CONFIG_ATM_HE_USE_SUNI
	if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->stop)
		he_dev->atm_dev->phy->stop(he_dev->atm_dev);
#endif /* CONFIG_ATM_HE_USE_SUNI */

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	if (he_dev->irq)
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		free_irq(he_dev->irq, he_dev);

	if (he_dev->irq_base)
		pci_free_consistent(he_dev->pci_dev, (CONFIG_IRQ_SIZE+1)
			* sizeof(struct he_irq), he_dev->irq_base, he_dev->irq_phys);

	if (he_dev->hsp)
		pci_free_consistent(he_dev->pci_dev, sizeof(struct he_hsp),
						he_dev->hsp, he_dev->hsp_phys);

1635
	if (he_dev->rbpl_base) {
1636
#ifdef USE_RBPL_POOL
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		for (i = 0; i < CONFIG_RBPL_SIZE; ++i) {
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			void *cpuaddr = he_dev->rbpl_virt[i].virt;
			dma_addr_t dma_handle = he_dev->rbpl_base[i].phys;

			pci_pool_free(he_dev->rbpl_pool, cpuaddr, dma_handle);
		}
#else
		pci_free_consistent(he_dev->pci_dev, CONFIG_RBPL_SIZE
			* CONFIG_RBPL_BUFSIZE, he_dev->rbpl_pages, he_dev->rbpl_pages_phys);
#endif
		pci_free_consistent(he_dev->pci_dev, CONFIG_RBPL_SIZE
			* sizeof(struct he_rbp), he_dev->rbpl_base, he_dev->rbpl_phys);
	}

#ifdef USE_RBPL_POOL
	if (he_dev->rbpl_pool)
		pci_pool_destroy(he_dev->rbpl_pool);
#endif

#ifdef USE_RBPS
1657
	if (he_dev->rbps_base) {
1658
#ifdef USE_RBPS_POOL
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		for (i = 0; i < CONFIG_RBPS_SIZE; ++i) {
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			void *cpuaddr = he_dev->rbps_virt[i].virt;
			dma_addr_t dma_handle = he_dev->rbps_base[i].phys;

			pci_pool_free(he_dev->rbps_pool, cpuaddr, dma_handle);
		}
#else
		pci_free_consistent(he_dev->pci_dev, CONFIG_RBPS_SIZE
			* CONFIG_RBPS_BUFSIZE, he_dev->rbps_pages, he_dev->rbps_pages_phys);
#endif
		pci_free_consistent(he_dev->pci_dev, CONFIG_RBPS_SIZE
			* sizeof(struct he_rbp), he_dev->rbps_base, he_dev->rbps_phys);
	}

#ifdef USE_RBPS_POOL
	if (he_dev->rbps_pool)
		pci_pool_destroy(he_dev->rbps_pool);
#endif

#endif /* USE_RBPS */

	if (he_dev->rbrq_base)
		pci_free_consistent(he_dev->pci_dev, CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq),
							he_dev->rbrq_base, he_dev->rbrq_phys);

	if (he_dev->tbrq_base)
		pci_free_consistent(he_dev->pci_dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
							he_dev->tbrq_base, he_dev->tbrq_phys);

	if (he_dev->tpdrq_base)
		pci_free_consistent(he_dev->pci_dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
							he_dev->tpdrq_base, he_dev->tpdrq_phys);

#ifdef USE_TPD_POOL
	if (he_dev->tpd_pool)
		pci_pool_destroy(he_dev->tpd_pool);
#else
	if (he_dev->tpd_base)
		pci_free_consistent(he_dev->pci_dev, CONFIG_NUMTPDS * sizeof(struct he_tpd),
							he_dev->tpd_base, he_dev->tpd_base_phys);
#endif

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	if (he_dev->pci_dev) {
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		pci_read_config_word(he_dev->pci_dev, PCI_COMMAND, &command);
		command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
		pci_write_config_word(he_dev->pci_dev, PCI_COMMAND, command);
	}
	
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	if (he_dev->membase)
		iounmap((void *) he_dev->membase);
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}

static struct he_tpd *
__alloc_tpd(struct he_dev *he_dev)
{
#ifdef USE_TPD_POOL
	struct he_tpd *tpd;
	dma_addr_t dma_handle; 

	tpd = pci_pool_alloc(he_dev->tpd_pool, SLAB_ATOMIC|SLAB_DMA, &dma_handle);              
	if (tpd == NULL)
		return NULL;
			
	tpd->status = TPD_ADDR(dma_handle);
	tpd->reserved = 0; 
	tpd->iovec[0].addr = 0; tpd->iovec[0].len = 0;
	tpd->iovec[1].addr = 0; tpd->iovec[1].len = 0;
	tpd->iovec[2].addr = 0; tpd->iovec[2].len = 0;

	return tpd;
#else
	int i;

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	for (i = 0; i < CONFIG_NUMTPDS; ++i) {
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		++he_dev->tpd_head;
		if (he_dev->tpd_head > he_dev->tpd_end) {
			he_dev->tpd_head = he_dev->tpd_base;
		}

		if (!he_dev->tpd_head->inuse) {
			he_dev->tpd_head->inuse = 1;
			he_dev->tpd_head->status &= TPD_MASK;
			he_dev->tpd_head->iovec[0].addr = 0; he_dev->tpd_head->iovec[0].len = 0;
			he_dev->tpd_head->iovec[1].addr = 0; he_dev->tpd_head->iovec[1].len = 0;
			he_dev->tpd_head->iovec[2].addr = 0; he_dev->tpd_head->iovec[2].len = 0;
			return he_dev->tpd_head;
		}
	}
	hprintk("out of tpds -- increase CONFIG_NUMTPDS (%d)\n", CONFIG_NUMTPDS);
	return NULL;
#endif
}

#define AAL5_LEN(buf,len) 						\
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			((((unsigned char *)(buf))[(len)-6] << 8) |	\
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				(((unsigned char *)(buf))[(len)-5]))

/* 2.10.1.2 receive
 *
 * aal5 packets can optionally return the tcp checksum in the lower
 * 16 bits of the crc (RSR0_TCP_CKSUM)
 */

#define TCP_CKSUM(buf,len) 						\
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			((((unsigned char *)(buf))[(len)-2] << 8) |	\
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				(((unsigned char *)(buf))[(len-1)]))

static int
he_service_rbrq(struct he_dev *he_dev, int group)
{
	struct he_rbrq *rbrq_tail = (struct he_rbrq *)
				((unsigned long)he_dev->rbrq_base |
					he_dev->hsp->group[group].rbrq_tail);
	struct he_rbp *rbp = NULL;
	unsigned cid, lastcid = -1;
	unsigned buf_len = 0;
	struct sk_buff *skb;
	struct atm_vcc *vcc = NULL;
	struct he_vcc *he_vcc;
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	struct he_iovec *iov;
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	int pdus_assembled = 0;
	int updated = 0;

1782
	read_lock(&vcc_sklist_lock);
1783
	while (he_dev->rbrq_head != rbrq_tail) {
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		++updated;

		HPRINTK("%p rbrq%d 0x%x len=%d cid=0x%x %s%s%s%s%s%s\n",
			he_dev->rbrq_head, group,
			RBRQ_ADDR(he_dev->rbrq_head),
			RBRQ_BUFLEN(he_dev->rbrq_head),
			RBRQ_CID(he_dev->rbrq_head),
			RBRQ_CRC_ERR(he_dev->rbrq_head) ? " CRC_ERR" : "",
			RBRQ_LEN_ERR(he_dev->rbrq_head) ? " LEN_ERR" : "",
			RBRQ_END_PDU(he_dev->rbrq_head) ? " END_PDU" : "",
			RBRQ_AAL5_PROT(he_dev->rbrq_head) ? " AAL5_PROT" : "",
			RBRQ_CON_CLOSED(he_dev->rbrq_head) ? " CON_CLOSED" : "",
			RBRQ_HBUF_ERR(he_dev->rbrq_head) ? " HBUF_ERR" : "");

#ifdef USE_RBPS
		if (RBRQ_ADDR(he_dev->rbrq_head) & RBP_SMALLBUF)
			rbp = &he_dev->rbps_base[RBP_INDEX(RBRQ_ADDR(he_dev->rbrq_head))];
		else
#endif
			rbp = &he_dev->rbpl_base[RBP_INDEX(RBRQ_ADDR(he_dev->rbrq_head))];
		
		buf_len = RBRQ_BUFLEN(he_dev->rbrq_head) * 4;
		cid = RBRQ_CID(he_dev->rbrq_head);

		if (cid != lastcid)
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			vcc = __find_vcc(he_dev, cid);
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		lastcid = cid;
1811

1812
		if (vcc == NULL) {
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			hprintk("vcc == NULL  (cid 0x%x)\n", cid);
			if (!RBRQ_HBUF_ERR(he_dev->rbrq_head))
					rbp->status &= ~RBP_LOANED;
					
			goto next_rbrq_entry;
		}

		he_vcc = HE_VCC(vcc);
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		if (he_vcc == NULL) {
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			hprintk("he_vcc == NULL  (cid 0x%x)\n", cid);
			if (!RBRQ_HBUF_ERR(he_dev->rbrq_head))
					rbp->status &= ~RBP_LOANED;
			goto next_rbrq_entry;
		}

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		if (RBRQ_HBUF_ERR(he_dev->rbrq_head)) {
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			hprintk("HBUF_ERR!  (cid 0x%x)\n", cid);
				atomic_inc(&vcc->stats->rx_drop);
			goto return_host_buffers;
		}

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		he_vcc->iov_tail->iov_base = RBRQ_ADDR(he_dev->rbrq_head);
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		he_vcc->iov_tail->iov_len = buf_len;
		he_vcc->pdu_len += buf_len;
		++he_vcc->iov_tail;

1839
		if (RBRQ_CON_CLOSED(he_dev->rbrq_head)) {
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			lastcid = -1;
			HPRINTK("wake_up rx_waitq  (cid 0x%x)\n", cid);
			wake_up(&he_vcc->rx_waitq);
			goto return_host_buffers;
		}

#ifdef notdef
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		if ((he_vcc->iov_tail - he_vcc->iov_head) > HE_MAXIOV) {
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			hprintk("iovec full!  cid 0x%x\n", cid);
			goto return_host_buffers;
		}
#endif
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		if (!RBRQ_END_PDU(he_dev->rbrq_head))
			goto next_rbrq_entry;
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		if (RBRQ_LEN_ERR(he_dev->rbrq_head)
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				|| RBRQ_CRC_ERR(he_dev->rbrq_head)) {
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			HPRINTK("%s%s (%d.%d)\n",
				RBRQ_CRC_ERR(he_dev->rbrq_head)
							? "CRC_ERR " : "",
				RBRQ_LEN_ERR(he_dev->rbrq_head)
							? "LEN_ERR" : "",
							vcc->vpi, vcc->vci);
			atomic_inc(&vcc->stats->rx_err);
			goto return_host_buffers;
		}

		skb = atm_alloc_charge(vcc, he_vcc->pdu_len + rx_skb_reserve,
							GFP_ATOMIC);
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		if (!skb) {
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			HPRINTK("charge failed (%d.%d)\n", vcc->vpi, vcc->vci);
			goto return_host_buffers;
		}

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		if (rx_skb_reserve > 0)
			skb_reserve(skb, rx_skb_reserve);
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		do_gettimeofday(&skb->stamp);

1879 1880
		for (iov = he_vcc->iov_head;
				iov < he_vcc->iov_tail; ++iov) {
1881
#ifdef USE_RBPS
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			if (iov->iov_base & RBP_SMALLBUF)
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				memcpy(skb_put(skb, iov->iov_len),
					he_dev->rbps_virt[RBP_INDEX(iov->iov_base)].virt, iov->iov_len);
			else
#endif
				memcpy(skb_put(skb, iov->iov_len),
					he_dev->rbpl_virt[RBP_INDEX(iov->iov_base)].virt, iov->iov_len);
		}

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		switch (vcc->qos.aal) {
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			case ATM_AAL0:
				/* 2.10.1.5 raw cell receive */
				skb->len = ATM_AAL0_SDU;
				skb->tail = skb->data + skb->len;
				break;
			case ATM_AAL5:
				/* 2.10.1.2 aal5 receive */

				skb->len = AAL5_LEN(skb->data, he_vcc->pdu_len);
				skb->tail = skb->data + skb->len;
#ifdef USE_CHECKSUM_HW
1903
				if (vcc->vpi == 0 && vcc->vci >= ATM_NOT_RSV_VCI) {
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					skb->ip_summed = CHECKSUM_HW;
					skb->csum = TCP_CKSUM(skb->data,
							he_vcc->pdu_len);
				}
#endif
				break;
		}

#ifdef should_never_happen
		if (skb->len > vcc->qos.rxtp.max_sdu)
			hprintk("pdu_len (%d) > vcc->qos.rxtp.max_sdu (%d)!  cid 0x%x\n", skb->len, vcc->qos.rxtp.max_sdu, cid);
#endif

#ifdef notdef
		ATM_SKB(skb)->vcc = vcc;
#endif
		vcc->push(vcc, skb);

		atomic_inc(&vcc->stats->rx);

return_host_buffers:
		++pdus_assembled;

1927 1928
		for (iov = he_vcc->iov_head;
				iov < he_vcc->iov_tail; ++iov) {
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#ifdef USE_RBPS
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			if (iov->iov_base & RBP_SMALLBUF)
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				rbp = &he_dev->rbps_base[RBP_INDEX(iov->iov_base)];
			else
#endif
				rbp = &he_dev->rbpl_base[RBP_INDEX(iov->iov_base)];

			rbp->status &= ~RBP_LOANED;
		}

		he_vcc->iov_tail = he_vcc->iov_head;
		he_vcc->pdu_len = 0;

next_rbrq_entry:
		he_dev->rbrq_head = (struct he_rbrq *)
				((unsigned long) he_dev->rbrq_base |
					RBRQ_MASK(++he_dev->rbrq_head));

	}
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	read_unlock(&vcc_sklist_lock);
1949

1950 1951 1952
	if (updated) {
		if (updated > he_dev->rbrq_peak)
			he_dev->rbrq_peak = updated;
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		he_writel(he_dev, RBRQ_MASK(he_dev->rbrq_head),
						G0_RBRQ_H + (group * 16));
#ifdef CONFIG_IA64_SGI_SN2
		(void) he_readl(he_dev, G0_RBRQ_H + (group * 16));
#endif
	}

	return pdus_assembled;
}

static void
he_service_tbrq(struct he_dev *he_dev, int group)
{
	struct he_tbrq *tbrq_tail = (struct he_tbrq *)
				((unsigned long)he_dev->tbrq_base |
					he_dev->hsp->group[group].tbrq_tail);
	struct he_tpd *tpd;
	int slot, updated = 0;
#ifdef USE_TPD_POOL
	struct list_head *p;
#endif

	/* 2.1.6 transmit buffer return queue */

1978
	while (he_dev->tbrq_head != tbrq_tail) {
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		++updated;

		HPRINTK("tbrq%d 0x%x%s%s\n",
			group,
			TBRQ_TPD(he_dev->tbrq_head), 
			TBRQ_EOS(he_dev->tbrq_head) ? " EOS" : "",
			TBRQ_MULTIPLE(he_dev->tbrq_head) ? " MULTIPLE" : "");
#ifdef USE_TPD_POOL
		tpd = NULL;
		p = &he_dev->outstanding_tpds;
1989
		while ((p = p->next) != &he_dev->outstanding_tpds) {
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			struct he_tpd *__tpd = list_entry(p, struct he_tpd, entry);
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			if (TPD_ADDR(__tpd->status) == TBRQ_TPD(he_dev->tbrq_head)) {
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				tpd = __tpd;
				list_del(&__tpd->entry);
				break;
			}
		}

1998
		if (tpd == NULL) {
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			hprintk("unable to locate tpd for dma buffer %x\n",
						TBRQ_TPD(he_dev->tbrq_head));
			goto next_tbrq_entry;
		}
#else
		tpd = &he_dev->tpd_base[ TPD_INDEX(TBRQ_TPD(he_dev->tbrq_head)) ];
#endif

2007
		if (TBRQ_EOS(he_dev->tbrq_head)) {
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			HPRINTK("wake_up(tx_waitq) cid 0x%x\n",
				he_mkcid(he_dev, tpd->vcc->vpi, tpd->vcc->vci));
			if (tpd->vcc)
				wake_up(&HE_VCC(tpd->vcc)->tx_waitq);

			goto next_tbrq_entry;
		}

2016
		for (slot = 0; slot < TPD_MAXIOV; ++slot) {
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			if (tpd->iovec[slot].addr)
				pci_unmap_single(he_dev->pci_dev,
					tpd->iovec[slot].addr,
					tpd->iovec[slot].len & TPD_LEN_MASK,
							PCI_DMA_TODEVICE);
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			if (tpd->iovec[slot].len & TPD_LST)
				break;
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		}

2027
		if (tpd->skb) {	/* && !TBRQ_MULTIPLE(he_dev->tbrq_head) */
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			if (tpd->vcc && tpd->vcc->pop)
				tpd->vcc->pop(tpd->vcc, tpd->skb);
			else
				dev_kfree_skb_any(tpd->skb);
		}

next_tbrq_entry:
#ifdef USE_TPD_POOL
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		if (tpd)
			pci_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));
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#else
		tpd->inuse = 0;
#endif
		he_dev->tbrq_head = (struct he_tbrq *)
				((unsigned long) he_dev->tbrq_base |
					TBRQ_MASK(++he_dev->tbrq_head));
	}

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	if (updated) {
		if (updated > he_dev->tbrq_peak)
			he_dev->tbrq_peak = updated;
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		he_writel(he_dev, TBRQ_MASK(he_dev->tbrq_head),
						G0_TBRQ_H + (group * 16));
#ifdef CONFIG_IA64_SGI_SN2
		(void) he_readl(he_dev, G0_TBRQ_H + (group * 16));
#endif
	}
}


static void
he_service_rbpl(struct he_dev *he_dev, int group)
{
	struct he_rbp *newtail;
	struct he_rbp *rbpl_head;
	int moved = 0;

	rbpl_head = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |
					RBPL_MASK(he_readl(he_dev, G0_RBPL_S)));

2069
	for (;;) {
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		newtail = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |
						RBPL_MASK(he_dev->rbpl_tail+1));

		/* table 3.42 -- rbpl_tail should never be set to rbpl_head */
		if ((newtail == rbpl_head) || (newtail->status & RBP_LOANED))
			break;

		newtail->status |= RBP_LOANED;
		he_dev->rbpl_tail = newtail;
		++moved;
	} 

	if (moved) {
		he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), G0_RBPL_T);
#ifdef CONFIG_IA64_SGI_SN2
2085
		(void) he_readl(he_dev, G0_RBPL_T);
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#endif
	}
}

#ifdef USE_RBPS
static void
he_service_rbps(struct he_dev *he_dev, int group)
{
	struct he_rbp *newtail;
	struct he_rbp *rbps_head;
	int moved = 0;

	rbps_head = (struct he_rbp *) ((unsigned long)he_dev->rbps_base |
					RBPS_MASK(he_readl(he_dev, G0_RBPS_S)));

2101
	for (;;) {
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		newtail = (struct he_rbp *) ((unsigned long)he_dev->rbps_base |
						RBPS_MASK(he_dev->rbps_tail+1));

		/* table 3.42 -- rbps_tail should never be set to rbps_head */
		if ((newtail == rbps_head) || (newtail->status & RBP_LOANED))
			break;

		newtail->status |= RBP_LOANED;
		he_dev->rbps_tail = newtail;
		++moved;
	} 

	if (moved) {
		he_writel(he_dev, RBPS_MASK(he_dev->rbps_tail), G0_RBPS_T);
#ifdef CONFIG_IA64_SGI_SN2
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		(void) he_readl(he_dev, G0_RBPS_T);
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#endif
	}
}
#endif /* USE_RBPS */

static void
he_tasklet(unsigned long data)
{
	unsigned long flags;
	struct he_dev *he_dev = (struct he_dev *) data;
	int group, type;
	int updated = 0;

	HPRINTK("tasklet (0x%lx)\n", data);
#ifdef USE_TASKLET
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	spin_lock_irqsave(&he_dev->global_lock, flags);
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#endif

2136
	while (he_dev->irq_head != he_dev->irq_tail) {
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		++updated;

		type = ITYPE_TYPE(he_dev->irq_head->isw);
		group = ITYPE_GROUP(he_dev->irq_head->isw);

2142
		switch (type) {
2143
			case ITYPE_RBRQ_THRESH:
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				HPRINTK("rbrq%d threshold\n", group);
				/* fall through */
2146
			case ITYPE_RBRQ_TIMER:
2147
				if (he_service_rbrq(he_dev, group)) {
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					he_service_rbpl(he_dev, group);
#ifdef USE_RBPS
					he_service_rbps(he_dev, group);
#endif /* USE_RBPS */
				}
				break;
			case ITYPE_TBRQ_THRESH:
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				HPRINTK("tbrq%d threshold\n", group);
				/* fall through */
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			case ITYPE_TPD_COMPLETE:
				he_service_tbrq(he_dev, group);
				break;
			case ITYPE_RBPL_THRESH:
				he_service_rbpl(he_dev, group);
				break;
			case ITYPE_RBPS_THRESH:
#ifdef USE_RBPS
				he_service_rbps(he_dev, group);
#endif /* USE_RBPS */
				break;
			case ITYPE_PHY:
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				HPRINTK("phy interrupt\n");
2170
#ifdef CONFIG_ATM_HE_USE_SUNI
2171
				spin_unlock_irqrestore(&he_dev->global_lock, flags);
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				if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->interrupt)
					he_dev->atm_dev->phy->interrupt(he_dev->atm_dev);
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				spin_lock_irqsave(&he_dev->global_lock, flags);
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#endif
				break;
			case ITYPE_OTHER:
2178
				switch (type|group) {
2179
					case ITYPE_PARITY:
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2180
						hprintk("parity error\n");
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						break;
					case ITYPE_ABORT:
						hprintk("abort 0x%x\n", he_readl(he_dev, ABORT_ADDR));
						break;
				}
				break;
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			case ITYPE_TYPE(ITYPE_INVALID):
				/* see 8.1.1 -- check all queues */
2189

2190
				HPRINTK("isw not updated 0x%x\n", he_dev->irq_head->isw);
2191

2192 2193
				he_service_rbrq(he_dev, 0);
				he_service_rbpl(he_dev, 0);
2194
#ifdef USE_RBPS
2195
				he_service_rbps(he_dev, 0);
2196
#endif /* USE_RBPS */
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				he_service_tbrq(he_dev, 0);
				break;
			default:
				hprintk("bad isw 0x%x?\n", he_dev->irq_head->isw);
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		}

		he_dev->irq_head->isw = ITYPE_INVALID;

		he_dev->irq_head = (struct he_irq *) NEXT_ENTRY(he_dev->irq_base, he_dev->irq_head, IRQ_MASK);
	}

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	if (updated) {
		if (updated > he_dev->irq_peak)
			he_dev->irq_peak = updated;
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		he_writel(he_dev,
			IRQ_SIZE(CONFIG_IRQ_SIZE) |
			IRQ_THRESH(CONFIG_IRQ_THRESH) |
			IRQ_TAIL(he_dev->irq_tail), IRQ0_HEAD);
		(void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata */
	}
#ifdef USE_TASKLET
2219
	spin_unlock_irqrestore(&he_dev->global_lock, flags);
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#endif
}

2223
static irqreturn_t
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he_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
{
	unsigned long flags;
	struct he_dev *he_dev = (struct he_dev * )dev_id;
	int handled = 0;

	if (he_dev == NULL)
		return IRQ_NONE;

2233
	spin_lock_irqsave(&he_dev->global_lock, flags);
2234 2235 2236 2237

	he_dev->irq_tail = (struct he_irq *) (((unsigned long)he_dev->irq_base) |
						(*he_dev->irq_tailoffset << 2));

2238
	if (he_dev->irq_tail == he_dev->irq_head) {
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2239
		HPRINTK("tailoffset not updated?\n");
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		he_dev->irq_tail = (struct he_irq *) ((unsigned long)he_dev->irq_base |
			((he_readl(he_dev, IRQ0_BASE) & IRQ_MASK) << 2));
		(void) he_readl(he_dev, INT_FIFO);	/* 8.1.2 controller errata */
	}

#ifdef DEBUG
	if (he_dev->irq_head == he_dev->irq_tail /* && !IRQ_PENDING */)
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2247
		hprintk("spurious (or shared) interrupt?\n");
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#endif

2250
	if (he_dev->irq_head != he_dev->irq_tail) {
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		handled = 1;
#ifdef USE_TASKLET
		tasklet_schedule(&he_dev->tasklet);
#else
		he_tasklet((unsigned long) he_dev);
#endif
		he_writel(he_dev, INT_CLEAR_A, INT_FIFO);
							/* clear interrupt */
#ifdef CONFIG_IA64_SGI_SN2
		(void) he_readl(he_dev, INT_FIFO);
#endif
	}
2263
	spin_unlock_irqrestore(&he_dev->global_lock, flags);
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	return IRQ_RETVAL(handled);

}

static __inline__ void
__enqueue_tpd(struct he_dev *he_dev, struct he_tpd *tpd, unsigned cid)
{
	struct he_tpdrq *new_tail;

	HPRINTK("tpdrq %p cid 0x%x -> tpdrq_tail %p\n",
					tpd, cid, he_dev->tpdrq_tail);

	/* new_tail = he_dev->tpdrq_tail; */
	new_tail = (struct he_tpdrq *) ((unsigned long) he_dev->tpdrq_base |
					TPDRQ_MASK(he_dev->tpdrq_tail+1));

	/*
	 * check to see if we are about to set the tail == head
	 * if true, update the head pointer from the adapter
	 * to see if this is really the case (reading the queue
	 * head for every enqueue would be unnecessarily slow)
	 */

2287
	if (new_tail == he_dev->tpdrq_head) {
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		he_dev->tpdrq_head = (struct he_tpdrq *)
			(((unsigned long)he_dev->tpdrq_base) |
				TPDRQ_MASK(he_readl(he_dev, TPDRQ_B_H)));

2292
		if (new_tail == he_dev->tpdrq_head) {
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			hprintk("tpdrq full (cid 0x%x)\n", cid);
			/*
			 * FIXME
			 * push tpd onto a transmit backlog queue
			 * after service_tbrq, service the backlog
			 * for now, we just drop the pdu
			 */
2300
			if (tpd->skb) {
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				if (tpd->vcc->pop)
					tpd->vcc->pop(tpd->vcc, tpd->skb);
				else
					dev_kfree_skb_any(tpd->skb);
				atomic_inc(&tpd->vcc->stats->tx_err);
			}
#ifdef USE_TPD_POOL
			pci_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));
#else
			tpd->inuse = 0;
#endif
			return;
		}
	}

	/* 2.1.5 transmit packet descriptor ready queue */
#ifdef USE_TPD_POOL
	list_add_tail(&tpd->entry, &he_dev->outstanding_tpds);
	he_dev->tpdrq_tail->tpd = TPD_ADDR(tpd->status);
#else
	he_dev->tpdrq_tail->tpd = he_dev->tpd_base_phys +
				(TPD_INDEX(tpd->status) * sizeof(struct he_tpd));
#endif
	he_dev->tpdrq_tail->cid = cid;
	wmb();

	he_dev->tpdrq_tail = new_tail;

	he_writel(he_dev, TPDRQ_MASK(he_dev->tpdrq_tail), TPDRQ_T);
#ifdef CONFIG_IA64_SGI_SN2
	(void) he_readl(he_dev, TPDRQ_T);
#endif
}

static int
he_open(struct atm_vcc *vcc, short vpi, int vci)
{
	unsigned long flags;
	struct he_dev *he_dev = HE_DEV(vcc->dev);
	struct he_vcc *he_vcc;
	int err = 0;
	unsigned cid, rsr0, rsr1, rsr4, tsr0, tsr0_aal, tsr4, period, reg, clock;

	
2345
	if ((err = atm_find_ci(vcc, &vpi, &vci))) {
2346 2347 2348
		HPRINTK("atm_find_ci err = %d\n", err);
		return err;
	}
2349 2350
	if (vci == ATM_VCI_UNSPEC || vpi == ATM_VPI_UNSPEC)
		return 0;
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	vcc->vpi = vpi;
	vcc->vci = vci;

	HPRINTK("open vcc %p %d.%d\n", vcc, vpi, vci);

	set_bit(ATM_VF_ADDR, &vcc->flags);

	cid = he_mkcid(he_dev, vpi, vci);

	he_vcc = (struct he_vcc *) kmalloc(sizeof(struct he_vcc), GFP_ATOMIC);
2361
	if (he_vcc == NULL) {
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2362
		hprintk("unable to allocate he_vcc during open\n");
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		return -ENOMEM;
	}

	he_vcc->iov_tail = he_vcc->iov_head;
	he_vcc->pdu_len = 0;
	he_vcc->rc_index = -1;

	init_waitqueue_head(&he_vcc->rx_waitq);
	init_waitqueue_head(&he_vcc->tx_waitq);

	HE_VCC(vcc) = he_vcc;

2375
	if (vcc->qos.txtp.traffic_class != ATM_NONE) {
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		int pcr_goal;

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		pcr_goal = atm_pcr_goal(&vcc->qos.txtp);
		if (pcr_goal == 0)
			pcr_goal = he_dev->atm_dev->link_rate;
		if (pcr_goal < 0)	/* means round down, technically */
			pcr_goal = -pcr_goal;
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		HPRINTK("open tx cid 0x%x pcr_goal %d\n", cid, pcr_goal);

2386
		switch (vcc->qos.aal) {
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			case ATM_AAL5:
				tsr0_aal = TSR0_AAL5;
				tsr4 = TSR4_AAL5;
				break;
			case ATM_AAL0:
				tsr0_aal = TSR0_AAL0_SDU;
				tsr4 = TSR4_AAL0_SDU;
				break;
			default:
				err = -EINVAL;
				goto open_failed;
		}

2400
		spin_lock_irqsave(&he_dev->global_lock, flags);
2401
		tsr0 = he_readl_tsr0(he_dev, cid);
2402
		spin_unlock_irqrestore(&he_dev->global_lock, flags);
2403

2404
		if (TSR0_CONN_STATE(tsr0) != 0) {
2405 2406 2407 2408 2409
			hprintk("cid 0x%x not idle (tsr0 = 0x%x)\n", cid, tsr0);
			err = -EBUSY;
			goto open_failed;
		}

2410
		switch (vcc->qos.txtp.traffic_class) {
2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428
			case ATM_UBR:
				/* 2.3.3.1 open connection ubr */

				tsr0 = TSR0_UBR | TSR0_GROUP(0) | tsr0_aal |
					TSR0_USE_WMIN | TSR0_UPDATE_GER;
				break;

			case ATM_CBR:
				/* 2.3.3.2 open connection cbr */

				/* 8.2.3 cbr scheduler wrap problem -- limit to 90% total link rate */
				if ((he_dev->total_bw + pcr_goal)
					> (he_dev->atm_dev->link_rate * 9 / 10))
				{
					err = -EBUSY;
					goto open_failed;
				}

2429
				spin_lock_irqsave(&he_dev->global_lock, flags);			/* also protects he_dev->cs_stper[] */
2430 2431

				/* find an unused cs_stper register */
2432
				for (reg = 0; reg < HE_NUM_CS_STPER; ++reg)
2433
					if (he_dev->cs_stper[reg].inuse == 0 || 
2434 2435
					    he_dev->cs_stper[reg].pcr == pcr_goal)
							break;
2436

2437
				if (reg == HE_NUM_CS_STPER) {
2438
					err = -EBUSY;
2439
					spin_unlock_irqrestore(&he_dev->global_lock, flags);
2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456
					goto open_failed;
				}

				he_dev->total_bw += pcr_goal;

				he_vcc->rc_index = reg;
				++he_dev->cs_stper[reg].inuse;
				he_dev->cs_stper[reg].pcr = pcr_goal;

				clock = he_is622(he_dev) ? 66667000 : 50000000;
				period = clock / pcr_goal;
				
				HPRINTK("rc_index = %d period = %d\n",
								reg, period);

				he_writel_mbox(he_dev, rate_to_atmf(period/2),
							CS_STPER0 + reg);
2457
				spin_unlock_irqrestore(&he_dev->global_lock, flags);
2458 2459 2460 2461 2462 2463 2464 2465 2466 2467

				tsr0 = TSR0_CBR | TSR0_GROUP(0) | tsr0_aal |
							TSR0_RC_INDEX(reg);

				break;
			default:
				err = -EINVAL;
				goto open_failed;
		}

2468
		spin_lock_irqsave(&he_dev->global_lock, flags);
2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489

		he_writel_tsr0(he_dev, tsr0, cid);
		he_writel_tsr4(he_dev, tsr4 | 1, cid);
		he_writel_tsr1(he_dev, TSR1_MCR(rate_to_atmf(0)) |
					TSR1_PCR(rate_to_atmf(pcr_goal)), cid);
		he_writel_tsr2(he_dev, TSR2_ACR(rate_to_atmf(pcr_goal)), cid);
		he_writel_tsr9(he_dev, TSR9_OPEN_CONN, cid);

		he_writel_tsr3(he_dev, 0x0, cid);
		he_writel_tsr5(he_dev, 0x0, cid);
		he_writel_tsr6(he_dev, 0x0, cid);
		he_writel_tsr7(he_dev, 0x0, cid);
		he_writel_tsr8(he_dev, 0x0, cid);
		he_writel_tsr10(he_dev, 0x0, cid);
		he_writel_tsr11(he_dev, 0x0, cid);
		he_writel_tsr12(he_dev, 0x0, cid);
		he_writel_tsr13(he_dev, 0x0, cid);
		he_writel_tsr14(he_dev, 0x0, cid);
#ifdef CONFIG_IA64_SGI_SN2
		(void) he_readl_tsr0(he_dev, cid);
#endif
2490
		spin_unlock_irqrestore(&he_dev->global_lock, flags);
2491 2492
	}

2493
	if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2494 2495 2496 2497 2498
		unsigned aal;

		HPRINTK("open rx cid 0x%x (rx_waitq %p)\n", cid,
		 				&HE_VCC(vcc)->rx_waitq);

2499
		switch (vcc->qos.aal) {
2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510
			case ATM_AAL5:
				aal = RSR0_AAL5;
				break;
			case ATM_AAL0:
				aal = RSR0_RAWCELL;
				break;
			default:
				err = -EINVAL;
				goto open_failed;
		}

2511
		spin_lock_irqsave(&he_dev->global_lock, flags);
2512 2513

		rsr0 = he_readl_rsr0(he_dev, cid);
2514
		if (rsr0 & RSR0_OPEN_CONN) {
2515
			spin_unlock_irqrestore(&he_dev->global_lock, flags);
2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532

			hprintk("cid 0x%x not idle (rsr0 = 0x%x)\n", cid, rsr0);
			err = -EBUSY;
			goto open_failed;
		}

#ifdef USE_RBPS
		rsr1 = RSR1_GROUP(0);
		rsr4 = RSR4_GROUP(0);
#else /* !USE_RBPS */
		rsr1 = RSR1_GROUP(0)|RSR1_RBPL_ONLY;
		rsr4 = RSR4_GROUP(0)|RSR4_RBPL_ONLY;
#endif /* USE_RBPS */
		rsr0 = vcc->qos.rxtp.traffic_class == ATM_UBR ? 
				(RSR0_EPD_ENABLE|RSR0_PPD_ENABLE) : 0;

#ifdef USE_CHECKSUM_HW
2533 2534
		if (vpi == 0 && vci >= ATM_NOT_RSV_VCI)
			rsr0 |= RSR0_TCP_CKSUM;
2535 2536 2537 2538 2539
#endif

		he_writel_rsr4(he_dev, rsr4, cid);
		he_writel_rsr1(he_dev, rsr1, cid);
		/* 5.1.11 last parameter initialized should be
2540
			  the open/closed indication in rsr0 */
2541 2542 2543 2544 2545 2546
		he_writel_rsr0(he_dev,
			rsr0 | RSR0_START_PDU | RSR0_OPEN_CONN | aal, cid);
#ifdef CONFIG_IA64_SGI_SN2
		(void) he_readl_rsr0(he_dev, cid);
#endif

2547
		spin_unlock_irqrestore(&he_dev->global_lock, flags);
2548 2549 2550 2551
	}

open_failed:

2552 2553 2554
	if (err) {
		if (he_vcc)
			kfree(he_vcc);
2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579
		clear_bit(ATM_VF_ADDR, &vcc->flags);
	}
	else
		set_bit(ATM_VF_READY, &vcc->flags);

	return err;
}

static void
he_close(struct atm_vcc *vcc)
{
	unsigned long flags;
	DECLARE_WAITQUEUE(wait, current);
	struct he_dev *he_dev = HE_DEV(vcc->dev);
	struct he_tpd *tpd;
	unsigned cid;
	struct he_vcc *he_vcc = HE_VCC(vcc);
#define MAX_RETRY 30
	int retry = 0, sleep = 1, tx_inuse;

	HPRINTK("close vcc %p %d.%d\n", vcc, vcc->vpi, vcc->vci);

	clear_bit(ATM_VF_READY, &vcc->flags);
	cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);

2580
	if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2581 2582 2583 2584 2585 2586 2587 2588
		int timeout;

		HPRINTK("close rx cid 0x%x\n", cid);

		/* 2.7.2.2 close receive operation */

		/* wait for previous close (if any) to finish */

2589
		spin_lock_irqsave(&he_dev->global_lock, flags);
2590
		while (he_readl(he_dev, RCC_STAT) & RCC_BUSY) {
2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602
			HPRINTK("close cid 0x%x RCC_BUSY\n", cid);
			udelay(250);
		}

		add_wait_queue(&he_vcc->rx_waitq, &wait);
		set_current_state(TASK_UNINTERRUPTIBLE);

		he_writel_rsr0(he_dev, RSR0_CLOSE_CONN, cid);
#ifdef CONFIG_IA64_SGI_SN2
		(void) he_readl_rsr0(he_dev, cid);
#endif
		he_writel_mbox(he_dev, cid, RXCON_CLOSE);
2603
		spin_unlock_irqrestore(&he_dev->global_lock, flags);
2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616

		timeout = schedule_timeout(30*HZ);

		remove_wait_queue(&he_vcc->rx_waitq, &wait);
		set_current_state(TASK_RUNNING);

		if (timeout == 0)
			hprintk("close rx timeout cid 0x%x\n", cid);

		HPRINTK("close rx cid 0x%x complete\n", cid);

	}

2617
	if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631
		volatile unsigned tsr4, tsr0;
		int timeout;

		HPRINTK("close tx cid 0x%x\n", cid);
		
		/* 2.1.2
		 *
		 * ... the host must first stop queueing packets to the TPDRQ
		 * on the connection to be closed, then wait for all outstanding
		 * packets to be transmitted and their buffers returned to the
		 * TBRQ. When the last packet on the connection arrives in the
		 * TBRQ, the host issues the close command to the adapter.
		 */

2632
		while (((tx_inuse = atomic_read(&vcc->sk->sk_wmem_alloc)) > 0) &&
2633
		       (retry < MAX_RETRY)) {
2634 2635
			set_current_state(TASK_UNINTERRUPTIBLE);
			(void) schedule_timeout(sleep);
2636 2637
			if (sleep < HZ)
				sleep = sleep * 2;
2638 2639 2640 2641

			++retry;
		}

2642 2643
		if (tx_inuse)
			hprintk("close tx cid 0x%x tx_inuse = %d\n", cid, tx_inuse);
2644 2645 2646

		/* 2.3.1.1 generic close operations with flush */

2647
		spin_lock_irqsave(&he_dev->global_lock, flags);
2648 2649 2650 2651 2652 2653
		he_writel_tsr4_upper(he_dev, TSR4_FLUSH_CONN, cid);
					/* also clears TSR4_SESSION_ENDED */
#ifdef CONFIG_IA64_SGI_SN2
		(void) he_readl_tsr4(he_dev, cid);
#endif

2654
		switch (vcc->qos.txtp.traffic_class) {
2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665
			case ATM_UBR:
				he_writel_tsr1(he_dev, 
					TSR1_MCR(rate_to_atmf(200000))
					| TSR1_PCR(0), cid);
				break;
			case ATM_CBR:
				he_writel_tsr14_upper(he_dev, TSR14_DELETE, cid);
				break;
		}

		tpd = __alloc_tpd(he_dev);
2666
		if (tpd == NULL) {
2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677
			hprintk("close tx he_alloc_tpd failed cid 0x%x\n", cid);
			goto close_tx_incomplete;
		}
		tpd->status |= TPD_EOS | TPD_INT;
		tpd->skb = NULL;
		tpd->vcc = vcc;
		wmb();

		add_wait_queue(&he_vcc->tx_waitq, &wait);
		set_current_state(TASK_UNINTERRUPTIBLE);
		__enqueue_tpd(he_dev, tpd, cid);
2678
		spin_unlock_irqrestore(&he_dev->global_lock, flags);
2679 2680 2681 2682 2683 2684

		timeout = schedule_timeout(30*HZ);

		remove_wait_queue(&he_vcc->tx_waitq, &wait);
		set_current_state(TASK_RUNNING);

2685 2686
		spin_lock_irqsave(&he_dev->global_lock, flags);

2687
		if (timeout == 0) {
2688 2689 2690 2691
			hprintk("close tx timeout cid 0x%x\n", cid);
			goto close_tx_incomplete;
		}

2692
		while (!((tsr4 = he_readl_tsr4(he_dev, cid)) & TSR4_SESSION_ENDED)) {
2693 2694 2695 2696
			HPRINTK("close tx cid 0x%x !TSR4_SESSION_ENDED (tsr4 = 0x%x)\n", cid, tsr4);
			udelay(250);
		}

2697
		while (TSR0_CONN_STATE(tsr0 = he_readl_tsr0(he_dev, cid)) != 0) {
2698 2699 2700 2701 2702 2703
			HPRINTK("close tx cid 0x%x TSR0_CONN_STATE != 0 (tsr0 = 0x%x)\n", cid, tsr0);
			udelay(250);
		}

close_tx_incomplete:

2704
		if (vcc->qos.txtp.traffic_class == ATM_CBR) {
2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715
			int reg = he_vcc->rc_index;

			HPRINTK("cs_stper reg = %d\n", reg);

			if (he_dev->cs_stper[reg].inuse == 0)
				hprintk("cs_stper[%d].inuse = 0!\n", reg);
			else
				--he_dev->cs_stper[reg].inuse;

			he_dev->total_bw -= he_dev->cs_stper[reg].pcr;
		}
2716
		spin_unlock_irqrestore(&he_dev->global_lock, flags);
2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741

		HPRINTK("close tx cid 0x%x complete\n", cid);
	}

	kfree(he_vcc);

	clear_bit(ATM_VF_ADDR, &vcc->flags);
}

static int
he_send(struct atm_vcc *vcc, struct sk_buff *skb)
{
	unsigned long flags;
	struct he_dev *he_dev = HE_DEV(vcc->dev);
	unsigned cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);
	struct he_tpd *tpd;
#ifdef USE_SCATTERGATHER
	int i, slot = 0;
#endif

#define HE_TPD_BUFSIZE 0xffff

	HPRINTK("send %d.%d\n", vcc->vpi, vcc->vci);

	if ((skb->len > HE_TPD_BUFSIZE) ||
2742
	    ((vcc->qos.aal == ATM_AAL0) && (skb->len != ATM_AAL0_SDU))) {
2743 2744 2745 2746 2747 2748 2749 2750 2751 2752
		hprintk("buffer too large (or small) -- %d bytes\n", skb->len );
		if (vcc->pop)
			vcc->pop(vcc, skb);
		else
			dev_kfree_skb_any(skb);
		atomic_inc(&vcc->stats->tx_err);
		return -EINVAL;
	}

#ifndef USE_SCATTERGATHER
2753
	if (skb_shinfo(skb)->nr_frags) {
Chas Williams's avatar
Chas Williams committed
2754
		hprintk("no scatter/gather support\n");
2755 2756 2757 2758 2759 2760 2761 2762
		if (vcc->pop)
			vcc->pop(vcc, skb);
		else
			dev_kfree_skb_any(skb);
		atomic_inc(&vcc->stats->tx_err);
		return -EINVAL;
	}
#endif
2763
	spin_lock_irqsave(&he_dev->global_lock, flags);
2764 2765

	tpd = __alloc_tpd(he_dev);
2766
	if (tpd == NULL) {
2767 2768 2769 2770 2771
		if (vcc->pop)
			vcc->pop(vcc, skb);
		else
			dev_kfree_skb_any(skb);
		atomic_inc(&vcc->stats->tx_err);
2772
		spin_unlock_irqrestore(&he_dev->global_lock, flags);
2773 2774 2775 2776 2777
		return -ENOMEM;
	}

	if (vcc->qos.aal == ATM_AAL5)
		tpd->status |= TPD_CELLTYPE(TPD_USERCELL);
2778
	else {
2779 2780 2781 2782 2783 2784
		char *pti_clp = (void *) (skb->data + 3);
		int clp, pti;

		pti = (*pti_clp & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT; 
		clp = (*pti_clp & ATM_HDR_CLP);
		tpd->status |= TPD_CELLTYPE(pti);
2785 2786
		if (clp)
			tpd->status |= TPD_CLP;
2787 2788 2789 2790 2791 2792 2793 2794 2795 2796

		skb_pull(skb, ATM_AAL0_SDU - ATM_CELL_PAYLOAD);
	}

#ifdef USE_SCATTERGATHER
	tpd->iovec[slot].addr = pci_map_single(he_dev->pci_dev, skb->data,
				skb->len - skb->data_len, PCI_DMA_TODEVICE);
	tpd->iovec[slot].len = skb->len - skb->data_len;
	++slot;

2797
	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2798 2799
		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

2800
		if (slot == TPD_MAXIOV) {	/* queue tpd; start new tpd */
2801 2802 2803 2804 2805 2806 2807
			tpd->vcc = vcc;
			tpd->skb = NULL;	/* not the last fragment
						   so dont ->push() yet */
			wmb();

			__enqueue_tpd(he_dev, tpd, cid);
			tpd = __alloc_tpd(he_dev);
2808
			if (tpd == NULL) {
2809 2810 2811 2812 2813
				if (vcc->pop)
					vcc->pop(vcc, skb);
				else
					dev_kfree_skb_any(skb);
				atomic_inc(&vcc->stats->tx_err);
2814
				spin_unlock_irqrestore(&he_dev->global_lock, flags);
2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828
				return -ENOMEM;
			}
			tpd->status |= TPD_USERCELL;
			slot = 0;
		}

		tpd->iovec[slot].addr = pci_map_single(he_dev->pci_dev,
			(void *) page_address(frag->page) + frag->page_offset,
				frag->size, PCI_DMA_TODEVICE);
		tpd->iovec[slot].len = frag->size;
		++slot;

	}

2829
	tpd->iovec[slot - 1].len |= TPD_LST;
2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841
#else
	tpd->address0 = pci_map_single(he_dev->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
	tpd->length0 = skb->len | TPD_LST;
#endif
	tpd->status |= TPD_INT;

	tpd->vcc = vcc;
	tpd->skb = skb;
	wmb();
	ATM_SKB(skb)->vcc = vcc;

	__enqueue_tpd(he_dev, tpd, cid);
2842
	spin_unlock_irqrestore(&he_dev->global_lock, flags);
2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856

	atomic_inc(&vcc->stats->tx);

	return 0;
}

static int
he_ioctl(struct atm_dev *atm_dev, unsigned int cmd, void *arg)
{
	unsigned long flags;
	struct he_dev *he_dev = HE_DEV(atm_dev);
	struct he_ioctl_reg reg;
	int err = 0;

2857
	switch (cmd) {
2858
		case HE_GET_REG:
2859 2860
			if (!capable(CAP_NET_ADMIN))
				return -EPERM;
2861

2862 2863 2864 2865
			if (copy_from_user(&reg, (struct he_ioctl_reg *) arg,
						sizeof(struct he_ioctl_reg)))
				return -EFAULT;
			
2866
			spin_lock_irqsave(&he_dev->global_lock, flags);
2867
			switch (reg.type) {
2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886
				case HE_REGTYPE_PCI:
					reg.val = he_readl(he_dev, reg.addr);
					break;
				case HE_REGTYPE_RCM:
					reg.val =
						he_readl_rcm(he_dev, reg.addr);
					break;
				case HE_REGTYPE_TCM:
					reg.val =
						he_readl_tcm(he_dev, reg.addr);
					break;
				case HE_REGTYPE_MBOX:
					reg.val =
						he_readl_mbox(he_dev, reg.addr);
					break;
				default:
					err = -EINVAL;
					break;
			}
2887
			spin_unlock_irqrestore(&he_dev->global_lock, flags);
2888
			if (err == 0)
2889 2890 2891
				if (copy_to_user((struct he_ioctl_reg *) arg, &reg,
							sizeof(struct he_ioctl_reg)))
					return -EFAULT;
2892 2893 2894 2895 2896 2897
			break;
		default:
#ifdef CONFIG_ATM_HE_USE_SUNI
			if (atm_dev->phy && atm_dev->phy->ioctl)
				err = atm_dev->phy->ioctl(atm_dev, cmd, arg);
#else /* CONFIG_ATM_HE_USE_SUNI */
2898
			err = -EINVAL;
2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913
#endif /* CONFIG_ATM_HE_USE_SUNI */
			break;
	}

	return err;
}

static void
he_phy_put(struct atm_dev *atm_dev, unsigned char val, unsigned long addr)
{
	unsigned long flags;
	struct he_dev *he_dev = HE_DEV(atm_dev);

	HPRINTK("phy_put(val 0x%x, addr 0x%lx)\n", val, addr);

2914 2915
	spin_lock_irqsave(&he_dev->global_lock, flags);
	he_writel(he_dev, val, FRAMER + (addr*4));
2916 2917 2918
#ifdef CONFIG_IA64_SGI_SN2
	(void) he_readl(he_dev, FRAMER + (addr*4));
#endif
2919
	spin_unlock_irqrestore(&he_dev->global_lock, flags);
2920 2921
}
 
2922
	
2923 2924 2925 2926 2927 2928 2929
static unsigned char
he_phy_get(struct atm_dev *atm_dev, unsigned long addr)
{ 
	unsigned long flags;
	struct he_dev *he_dev = HE_DEV(atm_dev);
	unsigned reg;

2930 2931 2932
	spin_lock_irqsave(&he_dev->global_lock, flags);
	reg = he_readl(he_dev, FRAMER + (addr*4));
	spin_unlock_irqrestore(&he_dev->global_lock, flags);
2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946

	HPRINTK("phy_get(addr 0x%lx) =0x%x\n", addr, reg);
	return reg;
}

static int
he_proc_read(struct atm_dev *dev, loff_t *pos, char *page)
{
	unsigned long flags;
	struct he_dev *he_dev = HE_DEV(dev);
	int left, i;
#ifdef notdef
	struct he_rbrq *rbrq_tail;
	struct he_tpdrq *tpdrq_head;
2947
	int rbpl_head, rbpl_tail;
2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962
#endif
	static long mcc = 0, oec = 0, dcc = 0, cec = 0;


	left = *pos;
	if (!left--)
		return sprintf(page, "%s\n", version);

	if (!left--)
		return sprintf(page, "%s%s\n\n",
			he_dev->prod_id, he_dev->media & 0x40 ? "SM" : "MM");

	if (!left--)
		return sprintf(page, "Mismatched Cells  VPI/VCI Not Open  Dropped Cells  RCM Dropped Cells\n");

2963
	spin_lock_irqsave(&he_dev->global_lock, flags);
2964 2965 2966 2967
	mcc += he_readl(he_dev, MCC);
	oec += he_readl(he_dev, OEC);
	dcc += he_readl(he_dev, DCC);
	cec += he_readl(he_dev, CEC);
2968
	spin_unlock_irqrestore(&he_dev->global_lock, flags);
2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991

	if (!left--)
		return sprintf(page, "%16ld  %16ld  %13ld  %17ld\n\n", 
							mcc, oec, dcc, cec);

	if (!left--)
		return sprintf(page, "irq_size = %d  inuse = ?  peak = %d\n",
				CONFIG_IRQ_SIZE, he_dev->irq_peak);

	if (!left--)
		return sprintf(page, "tpdrq_size = %d  inuse = ?\n",
						CONFIG_TPDRQ_SIZE);

	if (!left--)
		return sprintf(page, "rbrq_size = %d  inuse = ?  peak = %d\n",
				CONFIG_RBRQ_SIZE, he_dev->rbrq_peak);

	if (!left--)
		return sprintf(page, "tbrq_size = %d  peak = %d\n",
					CONFIG_TBRQ_SIZE, he_dev->tbrq_peak);


#ifdef notdef
2992 2993
	rbpl_head = RBPL_MASK(he_readl(he_dev, G0_RBPL_S));
	rbpl_tail = RBPL_MASK(he_readl(he_dev, G0_RBPL_T));
2994 2995

	inuse = rbpl_head - rbpl_tail;
2996 2997
	if (inuse < 0)
		inuse += CONFIG_RBPL_SIZE * sizeof(struct he_rbp);
2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037
	inuse /= sizeof(struct he_rbp);

	if (!left--)
		return sprintf(page, "rbpl_size = %d  inuse = %d\n\n",
						CONFIG_RBPL_SIZE, inuse);
#endif

	if (!left--)
		return sprintf(page, "rate controller periods (cbr)\n                 pcr  #vc\n");

	for (i = 0; i < HE_NUM_CS_STPER; ++i)
		if (!left--)
			return sprintf(page, "cs_stper%-2d  %8ld  %3d\n", i,
						he_dev->cs_stper[i].pcr,
						he_dev->cs_stper[i].inuse);

	if (!left--)
		return sprintf(page, "total bw (cbr): %d  (limit %d)\n",
			he_dev->total_bw, he_dev->atm_dev->link_rate * 10 / 9);

	return 0;
}

/* eeprom routines  -- see 4.7 */

u8
read_prom_byte(struct he_dev *he_dev, int addr)
{
	u32 val = 0, tmp_read = 0;
	int i, j = 0;
	u8 byte_read = 0;

	val = readl(he_dev->membase + HOST_CNTL);
	val &= 0xFFFFE0FF;
       
	/* Turn on write enable */
	val |= 0x800;
	he_writel(he_dev, val, HOST_CNTL);
       
	/* Send READ instruction */
3038
	for (i = 0; i < sizeof(readtab)/sizeof(readtab[0]); i++) {
3039 3040 3041 3042
		he_writel(he_dev, val | readtab[i], HOST_CNTL);
		udelay(EEPROM_DELAY);
	}
       
3043 3044
	/* Next, we need to send the byte address to read from */
	for (i = 7; i >= 0; i--) {
3045 3046 3047 3048 3049 3050
		he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
		udelay(EEPROM_DELAY);
		he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
		udelay(EEPROM_DELAY);
	}
       
3051
	j = 0;
3052 3053 3054 3055 3056

	val &= 0xFFFFF7FF;      /* Turn off write enable */
	he_writel(he_dev, val, HOST_CNTL);
       
	/* Now, we can read data from the EEPROM by clocking it in */
3057
	for (i = 7; i >= 0; i--) {
3058
		he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
3059 3060 3061 3062
		udelay(EEPROM_DELAY);
		tmp_read = he_readl(he_dev, HOST_CNTL);
		byte_read |= (unsigned char)
			   ((tmp_read & ID_DOUT) >> ID_DOFFSET << i);
3063 3064 3065 3066 3067 3068 3069
		he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
		udelay(EEPROM_DELAY);
	}
       
	he_writel(he_dev, val | ID_CS, HOST_CNTL);
	udelay(EEPROM_DELAY);

3070
	return byte_read;
3071 3072
}

3073
MODULE_LICENSE("GPL");
3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088
MODULE_AUTHOR("chas williams <chas@cmf.nrl.navy.mil>");
MODULE_DESCRIPTION("ForeRunnerHE ATM Adapter driver");
MODULE_PARM(disable64, "h");
MODULE_PARM_DESC(disable64, "disable 64-bit pci bus transfers");
MODULE_PARM(nvpibits, "i");
MODULE_PARM_DESC(nvpibits, "numbers of bits for vpi (default 0)");
MODULE_PARM(nvcibits, "i");
MODULE_PARM_DESC(nvcibits, "numbers of bits for vci (default 12)");
MODULE_PARM(rx_skb_reserve, "i");
MODULE_PARM_DESC(rx_skb_reserve, "padding for receive skb (default 16)");
MODULE_PARM(irq_coalesce, "i");
MODULE_PARM_DESC(irq_coalesce, "use interrupt coalescing (default 1)");
MODULE_PARM(sdh, "i");
MODULE_PARM_DESC(sdh, "use SDH framing (default 0)");

3089
static struct pci_device_id he_pci_tbl[] = {
3090 3091
	{ PCI_VENDOR_ID_FORE, PCI_DEVICE_ID_FORE_HE, PCI_ANY_ID, PCI_ANY_ID,
	  0, 0, 0 },
3092
	{ 0, }
3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103
};

static struct pci_driver he_driver = {
	.name =		"he",
	.probe =	he_init_one,
	.remove =	__devexit_p(he_remove_one),
	.id_table =	he_pci_tbl,
};

static int __init he_init(void)
{
3104
	return pci_module_init(&he_driver);
3105 3106 3107 3108
}

static void __exit he_cleanup(void)
{
3109
	pci_unregister_driver(&he_driver);
3110 3111 3112 3113
}

module_init(he_init);
module_exit(he_cleanup);