amdgpu_ttm.c 67 KB
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/*
 * Copyright 2009 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
 *    Dave Airlie
 */
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#include <linux/dma-mapping.h>
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#include <linux/iommu.h>
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#include <linux/hmm.h>
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#include <linux/pagemap.h>
#include <linux/sched/task.h>
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#include <linux/sched/mm.h>
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#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/swap.h>
#include <linux/swiotlb.h>
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#include <linux/dma-buf.h>
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#include <linux/sizes.h>
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#include <drm/ttm/ttm_bo_api.h>
#include <drm/ttm/ttm_bo_driver.h>
#include <drm/ttm/ttm_placement.h>
#include <drm/ttm/ttm_module.h>
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#include <drm/drm_debugfs.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "amdgpu_object.h"
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#include "amdgpu_trace.h"
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#include "amdgpu_amdkfd.h"
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#include "amdgpu_sdma.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_atomfirmware.h"
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#include "bif/bif_4_1_d.h"

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#define AMDGPU_TTM_VRAM_MAX_DW_READ	(size_t)128

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static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
				   struct ttm_tt *ttm,
				   struct ttm_resource *bo_mem);
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static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
				      struct ttm_tt *ttm);
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static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
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				    unsigned int type,
				    uint64_t size)
74
{
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	return ttm_range_man_init(&adev->mman.bdev, type,
				  false, size >> PAGE_SHIFT);
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}

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/**
 * amdgpu_evict_flags - Compute placement flags
 *
 * @bo: The buffer object to evict
 * @placement: Possible destination(s) for evicted BO
 *
 * Fill in placement data when ttm_bo_evict() is called
 */
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static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
				struct ttm_placement *placement)
{
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	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
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	struct amdgpu_bo *abo;
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	static const struct ttm_place placements = {
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		.fpfn = 0,
		.lpfn = 0,
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		.mem_type = TTM_PL_SYSTEM,
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		.flags = 0
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	};

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	/* Don't handle scatter gather BOs */
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	if (bo->type == ttm_bo_type_sg) {
		placement->num_placement = 0;
		placement->num_busy_placement = 0;
		return;
	}

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	/* Object isn't an AMDGPU object so ignore */
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	if (!amdgpu_bo_is_amdgpu_bo(bo)) {
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		placement->placement = &placements;
		placement->busy_placement = &placements;
		placement->num_placement = 1;
		placement->num_busy_placement = 1;
		return;
	}
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	abo = ttm_to_amdgpu_bo(bo);
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	switch (bo->mem.mem_type) {
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	case AMDGPU_PL_GDS:
	case AMDGPU_PL_GWS:
	case AMDGPU_PL_OA:
		placement->num_placement = 0;
		placement->num_busy_placement = 0;
		return;

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	case TTM_PL_VRAM:
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		if (!adev->mman.buffer_funcs_enabled) {
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			/* Move to system memory */
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			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
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		} else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
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			   !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
			   amdgpu_bo_in_cpu_visible_vram(abo)) {
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			/* Try evicting to the CPU inaccessible part of VRAM
			 * first, but only set GTT as busy placement, so this
			 * BO will be evicted to GTT rather than causing other
			 * BOs to be evicted from VRAM
			 */
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			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
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							 AMDGPU_GEM_DOMAIN_GTT);
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			abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
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			abo->placements[0].lpfn = 0;
			abo->placement.busy_placement = &abo->placements[1];
			abo->placement.num_busy_placement = 1;
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		} else {
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			/* Move to GTT memory */
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			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
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		}
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		break;
	case TTM_PL_TT:
	default:
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		amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
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		break;
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	}
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	*placement = abo->placement;
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}

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/**
 * amdgpu_verify_access - Verify access for a mmap call
 *
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 * @bo:	The buffer object to map
 * @filp: The file pointer from the process performing the mmap
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 *
 * This is called by ttm_bo_mmap() to verify whether a process
 * has the right to mmap a BO to their process space.
 */
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static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
{
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	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
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	/*
	 * Don't verify access for KFD BOs. They don't have a GEM
	 * object associated with them.
	 */
	if (abo->kfd_bo)
		return 0;

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	if (amdgpu_ttm_tt_get_usermm(bo->ttm))
		return -EPERM;
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	return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
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					  filp->private_data);
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}

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/**
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 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 *
 * @bo: The bo to assign the memory to.
 * @mm_node: Memory manager node for drm allocator.
 * @mem: The region where the bo resides.
 *
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 */
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static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
				    struct drm_mm_node *mm_node,
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				    struct ttm_resource *mem)
193
{
194
	uint64_t addr = 0;
195

196
	if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
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		addr = mm_node->start << PAGE_SHIFT;
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		addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
						mem->mem_type);
200
	}
201
	return addr;
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}

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/**
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 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 * @offset. It also modifies the offset to be within the drm_mm_node returned
 *
 * @mem: The region where the bo resides.
 * @offset: The offset that drm_mm_node is used for finding.
 *
211
 */
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static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
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					       uint64_t *offset)
214
{
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	struct drm_mm_node *mm_node = mem->mm_node;
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	while (*offset >= (mm_node->size << PAGE_SHIFT)) {
		*offset -= (mm_node->size << PAGE_SHIFT);
		++mm_node;
	}
	return mm_node;
}
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/**
 * amdgpu_ttm_map_buffer - Map memory into the GART windows
 * @bo: buffer object to map
 * @mem: memory object to map
 * @mm_node: drm_mm node object to map
 * @num_pages: number of pages to map
 * @offset: offset into @mm_node where to start
 * @window: which GART window to use
 * @ring: DMA ring to use for the copy
 * @tmz: if we should setup a TMZ enabled mapping
 * @addr: resulting address inside the MC address space
 *
 * Setup one of the GART windows to access a specific piece of memory or return
 * the physical address for local memory.
 */
static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
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				 struct ttm_resource *mem,
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				 struct drm_mm_node *mm_node,
				 unsigned num_pages, uint64_t offset,
				 unsigned window, struct amdgpu_ring *ring,
				 bool tmz, uint64_t *addr)
{
	struct amdgpu_device *adev = ring->adev;
	struct amdgpu_job *job;
	unsigned num_dw, num_bytes;
	struct dma_fence *fence;
	uint64_t src_addr, dst_addr;
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	void *cpu_addr;
252
	uint64_t flags;
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	unsigned int i;
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	int r;

	BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
	       AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);

	/* Map only what can't be accessed directly */
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	if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
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		*addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
		return 0;
	}

	*addr = adev->gmc.gart_start;
	*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
		AMDGPU_GPU_PAGE_SIZE;
	*addr += offset & ~PAGE_MASK;

	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
	num_bytes = num_pages * 8;

	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
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				     AMDGPU_IB_POOL_DELAYED, &job);
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	if (r)
		return r;

	src_addr = num_dw * 4;
	src_addr += job->ibs[0].gpu_addr;

	dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
	dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
				dst_addr, num_bytes, false);

	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
	WARN_ON(job->ibs[0].length_dw > num_dw);

	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
	if (tmz)
		flags |= AMDGPU_PTE_TMZ;

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	cpu_addr = &job->ibs[0].ptr[num_dw];

	if (mem->mem_type == TTM_PL_TT) {
		dma_addr_t *dma_address;

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		dma_address = &bo->ttm->dma_address[offset >> PAGE_SHIFT];
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		r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
				    cpu_addr);
		if (r)
			goto error_free;
	} else {
		dma_addr_t dma_address;

		dma_address = (mm_node->start << PAGE_SHIFT) + offset;
		dma_address += adev->vm_manager.vram_base_offset;

		for (i = 0; i < num_pages; ++i) {
			r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
					    &dma_address, flags, cpu_addr);
			if (r)
				goto error_free;

			dma_address += PAGE_SIZE;
		}
	}
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	r = amdgpu_job_submit(job, &adev->mman.entity,
			      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
	if (r)
		goto error_free;

	dma_fence_put(fence);

	return r;

error_free:
	amdgpu_job_free(job);
	return r;
}

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/**
 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
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 * @adev: amdgpu device
 * @src: buffer/address where to read from
 * @dst: buffer/address where to write to
 * @size: number of bytes to copy
 * @tmz: if a secure copy should be used
 * @resv: resv object to sync to
 * @f: Returns the last fence if multiple jobs are submitted.
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 *
 * The function copies @size bytes from {src->mem + src->offset} to
 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 * move and different for a BO to BO copy.
 *
 */
int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
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			       const struct amdgpu_copy_mem *src,
			       const struct amdgpu_copy_mem *dst,
351
			       uint64_t size, bool tmz,
352
			       struct dma_resv *resv,
353
			       struct dma_fence **f)
354
{
355 356 357 358
	const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
					AMDGPU_GPU_PAGE_SIZE);

	uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
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	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
360
	struct drm_mm_node *src_mm, *dst_mm;
361
	struct dma_fence *fence = NULL;
362
	int r = 0;
363

364
	if (!adev->mman.buffer_funcs_enabled) {
365 366 367 368
		DRM_ERROR("Trying to move memory with ring turned off.\n");
		return -EINVAL;
	}

369
	src_offset = src->offset;
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	if (src->mem->mm_node) {
		src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
		src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
	} else {
		src_mm = NULL;
		src_node_size = ULLONG_MAX;
	}
377

378
	dst_offset = dst->offset;
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	if (dst->mem->mm_node) {
		dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
		dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
	} else {
		dst_mm = NULL;
		dst_node_size = ULLONG_MAX;
	}
386

387
	mutex_lock(&adev->mman.gtt_window_lock);
388 389

	while (size) {
390 391
		uint32_t src_page_offset = src_offset & ~PAGE_MASK;
		uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
392
		struct dma_fence *next;
393 394
		uint32_t cur_size;
		uint64_t from, to;
395

396 397 398
		/* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
		 * begins at an offset, then adjust the size accordingly
		 */
399 400 401
		cur_size = max(src_page_offset, dst_page_offset);
		cur_size = min(min3(src_node_size, dst_node_size, size),
			       (uint64_t)(GTT_MAX_BYTES - cur_size));
402 403 404 405 406 407 408

		/* Map src to window 0 and dst to window 1. */
		r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
					  PFN_UP(cur_size + src_page_offset),
					  src_offset, 0, ring, tmz, &from);
		if (r)
			goto error;
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		r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
					  PFN_UP(cur_size + dst_page_offset),
					  dst_offset, 1, ring, tmz, &to);
		if (r)
			goto error;
415

416
		r = amdgpu_copy_buffer(ring, from, to, cur_size,
417
				       resv, &next, false, true, tmz);
418 419 420
		if (r)
			goto error;

421
		dma_fence_put(fence);
422 423
		fence = next;

424 425
		size -= cur_size;
		if (!size)
426 427
			break;

428 429
		src_node_size -= cur_size;
		if (!src_node_size) {
430 431 432
			++src_mm;
			src_node_size = src_mm->size << PAGE_SHIFT;
			src_offset = 0;
433
		} else {
434
			src_offset += cur_size;
435
		}
436

437 438
		dst_node_size -= cur_size;
		if (!dst_node_size) {
439 440 441
			++dst_mm;
			dst_node_size = dst_mm->size << PAGE_SHIFT;
			dst_offset = 0;
442
		} else {
443
			dst_offset += cur_size;
444 445
		}
	}
446
error:
447
	mutex_unlock(&adev->mman.gtt_window_lock);
448 449 450 451 452 453
	if (f)
		*f = dma_fence_get(fence);
	dma_fence_put(fence);
	return r;
}

454 455 456
/**
 * amdgpu_move_blit - Copy an entire buffer to another buffer
 *
457 458
 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 * help move buffers to and from VRAM.
459
 */
460
static int amdgpu_move_blit(struct ttm_buffer_object *bo,
461
			    bool evict,
462 463
			    struct ttm_resource *new_mem,
			    struct ttm_resource *old_mem)
464 465
{
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
466
	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
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	struct amdgpu_copy_mem src, dst;
	struct dma_fence *fence = NULL;
	int r;

	src.bo = bo;
	dst.bo = bo;
	src.mem = old_mem;
	dst.mem = new_mem;
	src.offset = 0;
	dst.offset = 0;

	r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
				       new_mem->num_pages << PAGE_SHIFT,
480
				       amdgpu_bo_encrypted(abo),
481
				       bo->base.resv, &fence);
482 483
	if (r)
		goto error;
484

485 486
	/* clear the space being freed */
	if (old_mem->mem_type == TTM_PL_VRAM &&
487
	    (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
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		struct dma_fence *wipe_fence = NULL;

		r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
				       NULL, &wipe_fence);
		if (r) {
			goto error;
		} else if (wipe_fence) {
			dma_fence_put(fence);
			fence = wipe_fence;
		}
	}

500 501
	/* Always block for VM page tables before committing the new location */
	if (bo->type == ttm_bo_type_kernel)
502
		r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
503
	else
504
		r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
505
	dma_fence_put(fence);
506
	return r;
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error:
	if (fence)
510 511
		dma_fence_wait(fence, false);
	dma_fence_put(fence);
512
	return r;
513 514
}

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/**
 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 *
 * Called by amdgpu_bo_move().
 */
520 521
static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
				struct ttm_operation_ctx *ctx,
522
				struct ttm_resource *new_mem)
523
{
524 525
	struct ttm_resource *old_mem = &bo->mem;
	struct ttm_resource tmp_mem;
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	struct ttm_place placements;
	struct ttm_placement placement;
	int r;

530
	/* create space/pages for new_mem in GTT space */
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	tmp_mem = *new_mem;
	tmp_mem.mm_node = NULL;
	placement.num_placement = 1;
	placement.placement = &placements;
	placement.num_busy_placement = 1;
	placement.busy_placement = &placements;
	placements.fpfn = 0;
538
	placements.lpfn = 0;
539
	placements.mem_type = TTM_PL_TT;
540
	placements.flags = 0;
541
	r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
542
	if (unlikely(r)) {
543
		pr_err("Failed to find GTT space for blit from VRAM\n");
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		return r;
	}

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	r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
	if (unlikely(r))
		goto out_cleanup;

551
	/* Bind the memory to the GTT space */
552
	r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
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	if (unlikely(r)) {
		goto out_cleanup;
	}
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	/* blit VRAM to GTT */
558
	r = amdgpu_move_blit(bo, evict, &tmp_mem, old_mem);
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	if (unlikely(r)) {
		goto out_cleanup;
	}
562

563
	r = ttm_bo_wait_ctx(bo, ctx);
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	if (unlikely(r))
		goto out_cleanup;

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	amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
	ttm_resource_free(bo, &bo->mem);
569
	ttm_bo_assign_mem(bo, new_mem);
570
out_cleanup:
571
	ttm_resource_free(bo, &tmp_mem);
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	return r;
}

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/**
 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 *
 * Called by amdgpu_bo_move().
 */
580 581
static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
				struct ttm_operation_ctx *ctx,
582
				struct ttm_resource *new_mem)
583
{
584 585
	struct ttm_resource *old_mem = &bo->mem;
	struct ttm_resource tmp_mem;
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	struct ttm_placement placement;
	struct ttm_place placements;
	int r;

590
	/* make space in GTT for old_mem buffer */
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	tmp_mem = *new_mem;
	tmp_mem.mm_node = NULL;
	placement.num_placement = 1;
	placement.placement = &placements;
	placement.num_busy_placement = 1;
	placement.busy_placement = &placements;
	placements.fpfn = 0;
598
	placements.lpfn = 0;
599
	placements.mem_type = TTM_PL_TT;
600
	placements.flags = 0;
601
	r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
602
	if (unlikely(r)) {
603
		pr_err("Failed to find GTT space for blit to VRAM\n");
604 605
		return r;
	}
606 607

	/* move/bind old memory to GTT space */
608 609 610 611 612
	r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
	if (unlikely(r))
		return r;

	r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
613 614 615
	if (unlikely(r)) {
		goto out_cleanup;
	}
616

617
	ttm_bo_assign_mem(bo, &tmp_mem);
618
	/* copy to VRAM */
619
	r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
620 621 622 623
	if (unlikely(r)) {
		goto out_cleanup;
	}
out_cleanup:
624
	ttm_resource_free(bo, &tmp_mem);
625 626 627
	return r;
}

628 629 630 631 632 633
/**
 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 *
 * Called by amdgpu_bo_move()
 */
static bool amdgpu_mem_visible(struct amdgpu_device *adev,
634
			       struct ttm_resource *mem)
635 636 637 638 639 640 641 642 643
{
	struct drm_mm_node *nodes = mem->mm_node;

	if (mem->mem_type == TTM_PL_SYSTEM ||
	    mem->mem_type == TTM_PL_TT)
		return true;
	if (mem->mem_type != TTM_PL_VRAM)
		return false;

644
	/* ttm_resource_ioremap only supports contiguous memory */
645 646 647 648 649 650 651
	if (nodes->size != mem->num_pages)
		return false;

	return ((nodes->start + nodes->size) << PAGE_SHIFT)
		<= adev->gmc.visible_vram_size;
}

652 653 654 655 656
/**
 * amdgpu_bo_move - Move a buffer object to a new memory location
 *
 * Called by ttm_bo_handle_move_mem()
 */
657 658
static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
			  struct ttm_operation_ctx *ctx,
659
			  struct ttm_resource *new_mem)
660 661
{
	struct amdgpu_device *adev;
662
	struct amdgpu_bo *abo;
663
	struct ttm_resource *old_mem = &bo->mem;
664 665
	int r;

666 667 668 669 670 671
	if (new_mem->mem_type == TTM_PL_TT) {
		r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
		if (r)
			return r;
	}

672 673
	amdgpu_bo_move_notify(bo, evict, new_mem);

674
	/* Can't move a pinned BO */
675
	abo = ttm_to_amdgpu_bo(bo);
676
	if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
677 678
		return -EINVAL;

679
	adev = amdgpu_ttm_adev(bo->bdev);
680

681
	if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
682
		ttm_bo_move_null(bo, new_mem);
683 684
		return 0;
	}
685 686
	if (old_mem->mem_type == TTM_PL_SYSTEM &&
	    new_mem->mem_type == TTM_PL_TT) {
687
		ttm_bo_move_null(bo, new_mem);
688 689
		return 0;
	}
690 691

	if (old_mem->mem_type == TTM_PL_TT &&
692
	    new_mem->mem_type == TTM_PL_SYSTEM) {
693
		r = ttm_bo_wait_ctx(bo, ctx);
694
		if (r)
695
			goto fail;
696 697 698

		amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
		ttm_resource_free(bo, &bo->mem);
699 700 701
		ttm_bo_assign_mem(bo, new_mem);
		return 0;
	}
702

703 704 705 706 707 708 709
	if (old_mem->mem_type == AMDGPU_PL_GDS ||
	    old_mem->mem_type == AMDGPU_PL_GWS ||
	    old_mem->mem_type == AMDGPU_PL_OA ||
	    new_mem->mem_type == AMDGPU_PL_GDS ||
	    new_mem->mem_type == AMDGPU_PL_GWS ||
	    new_mem->mem_type == AMDGPU_PL_OA) {
		/* Nothing to save here */
710
		ttm_bo_move_null(bo, new_mem);
711 712
		return 0;
	}
713

714 715
	if (!adev->mman.buffer_funcs_enabled) {
		r = -ENODEV;
716
		goto memcpy;
717
	}
718 719 720

	if (old_mem->mem_type == TTM_PL_VRAM &&
	    new_mem->mem_type == TTM_PL_SYSTEM) {
721
		r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
722 723
	} else if (old_mem->mem_type == TTM_PL_SYSTEM &&
		   new_mem->mem_type == TTM_PL_VRAM) {
724
		r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
725
	} else {
726
		r = amdgpu_move_blit(bo, evict,
727
				     new_mem, old_mem);
728 729 730 731
	}

	if (r) {
memcpy:
732 733 734 735
		/* Check that all memory is CPU accessible */
		if (!amdgpu_mem_visible(adev, old_mem) ||
		    !amdgpu_mem_visible(adev, new_mem)) {
			pr_err("Move buffer fallback to memcpy unavailable\n");
736
			goto fail;
737
		}
738 739 740

		r = ttm_bo_move_memcpy(bo, ctx, new_mem);
		if (r)
741
			goto fail;
742 743
	}

744 745 746 747 748 749 750 751 752
	if (bo->type == ttm_bo_type_device &&
	    new_mem->mem_type == TTM_PL_VRAM &&
	    old_mem->mem_type != TTM_PL_VRAM) {
		/* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
		 * accesses the BO after it's moved.
		 */
		abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
	}

753 754 755
	/* update statistics */
	atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
	return 0;
756 757 758 759 760
fail:
	swap(*new_mem, bo->mem);
	amdgpu_bo_move_notify(bo, false, new_mem);
	swap(*new_mem, bo->mem);
	return r;
761 762
}

763 764 765 766 767
/**
 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 *
 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 */
768
static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
769
{
770
	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
771
	struct drm_mm_node *mm_node = mem->mm_node;
772
	size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
773 774 775 776 777 778 779 780 781 782

	switch (mem->mem_type) {
	case TTM_PL_SYSTEM:
		/* system memory */
		return 0;
	case TTM_PL_TT:
		break;
	case TTM_PL_VRAM:
		mem->bus.offset = mem->start << PAGE_SHIFT;
		/* check if it's visible */
783
		if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
784
			return -EINVAL;
785 786
		/* Only physically contiguous buffers apply. In a contiguous
		 * buffer, size of the first mm_node would match the number of
787
		 * pages in ttm_resource.
788 789 790 791 792 793
		 */
		if (adev->mman.aper_base_kaddr &&
		    (mm_node->size == mem->num_pages))
			mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
					mem->bus.offset;

794
		mem->bus.offset += adev->gmc.aper_base;
795
		mem->bus.is_iomem = true;
796
		mem->bus.caching = ttm_write_combined;
797 798 799 800 801 802 803
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

804 805 806
static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
					   unsigned long page_offset)
{
807
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
808
	uint64_t offset = (page_offset << PAGE_SHIFT);
809
	struct drm_mm_node *mm;
810

811
	mm = amdgpu_find_mm_node(&bo->mem, &offset);
812 813
	offset += adev->gmc.aper_base;
	return mm->start + (offset >> PAGE_SHIFT);
814 815
}

816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836
/**
 * amdgpu_ttm_domain_start - Returns GPU start address
 * @adev: amdgpu device object
 * @type: type of the memory
 *
 * Returns:
 * GPU start address of a memory domain
 */

uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
{
	switch (type) {
	case TTM_PL_TT:
		return adev->gmc.gart_start;
	case TTM_PL_VRAM:
		return adev->gmc.vram_start;
	}

	return 0;
}

837 838 839 840
/*
 * TTM backend functions.
 */
struct amdgpu_ttm_tt {
841
	struct ttm_tt	ttm;
842
	struct drm_gem_object	*gobj;
843 844
	u64			offset;
	uint64_t		userptr;
845
	struct task_struct	*usertask;
846
	uint32_t		userflags;
847
	bool			bound;
848
#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
849
	struct hmm_range	*range;
850
#endif
851 852
};

853
#ifdef CONFIG_DRM_AMDGPU_USERPTR
854
/**
855 856
 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 * memory and start HMM tracking CPU page table update
857
 *
858 859
 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 * once afterwards to stop HMM tracking
860
 */
861
int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
862
{
863
	struct ttm_tt *ttm = bo->tbo.ttm;
864
	struct amdgpu_ttm_tt *gtt = (void *)ttm;
865
	unsigned long start = gtt->userptr;
866 867
	struct vm_area_struct *vma;
	struct hmm_range *range;
868 869
	unsigned long timeout;
	struct mm_struct *mm;
870
	unsigned long i;
871
	int r = 0;
872

873 874 875
	mm = bo->notifier.mm;
	if (unlikely(!mm)) {
		DRM_DEBUG_DRIVER("BO is not registered?\n");
876
		return -EFAULT;
877
	}
878

879 880 881 882
	/* Another get_user_pages is running at the same time?? */
	if (WARN_ON(gtt->range))
		return -EFAULT;

883
	if (!mmget_not_zero(mm)) /* Happens during process shutdown */
884 885
		return -ESRCH;

886 887
	range = kzalloc(sizeof(*range), GFP_KERNEL);
	if (unlikely(!range)) {
888
		r = -ENOMEM;
889 890
		goto out;
	}
891 892 893
	range->notifier = &bo->notifier;
	range->start = bo->notifier.interval_tree.start;
	range->end = bo->notifier.interval_tree.last + 1;
894
	range->default_flags = HMM_PFN_REQ_FAULT;
895
	if (!amdgpu_ttm_tt_is_readonly(ttm))
896
		range->default_flags |= HMM_PFN_REQ_WRITE;
897

898 899 900
	range->hmm_pfns = kvmalloc_array(ttm->num_pages,
					 sizeof(*range->hmm_pfns), GFP_KERNEL);
	if (unlikely(!range->hmm_pfns)) {
901 902
		r = -ENOMEM;
		goto out_free_ranges;
903
	}
904

905
	mmap_read_lock(mm);
906 907 908
	vma = find_vma(mm, start);
	if (unlikely(!vma || start < vma->vm_start)) {
		r = -EFAULT;
909
		goto out_unlock;
910
	}
911
	if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
912
		vma->vm_file)) {
913
		r = -EPERM;
914
		goto out_unlock;
915
	}
916
	mmap_read_unlock(mm);
917
	timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
918

919 920
retry:
	range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
921

922
	mmap_read_lock(mm);
923
	r = hmm_range_fault(range);
924
	mmap_read_unlock(mm);
925
	if (unlikely(r)) {
926 927 928 929
		/*
		 * FIXME: This timeout should encompass the retry from
		 * mmu_interval_read_retry() as well.
		 */
930
		if (r == -EBUSY && !time_after(jiffies, timeout))
931
			goto retry;
932
		goto out_free_pfns;
933
	}
934

935 936 937 938 939 940
	/*
	 * Due to default_flags, all pages are HMM_PFN_VALID or
	 * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
	 * the notifier_lock, and mmu_interval_read_retry() must be done first.
	 */
	for (i = 0; i < ttm->num_pages; i++)
941
		pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
942 943

	gtt->range = range;
944
	mmput(mm);
945

946
	return 0;
947

948
out_unlock:
949
	mmap_read_unlock(mm);
950
out_free_pfns:
951
	kvfree(range->hmm_pfns);
952
out_free_ranges:
953
	kfree(range);
954
out:
955
	mmput(mm);
956 957 958
	return r;
}

959
/**
960 961
 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 * Check if the pages backing this ttm range have been invalidated
962
 *
963
 * Returns: true if pages are still valid
964
 */
965
bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
966
{
967
	struct amdgpu_ttm_tt *gtt = (void *)ttm;
968
	bool r = false;
969

970 971
	if (!gtt || !gtt->userptr)
		return false;
972

973
	DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
974
		gtt->userptr, ttm->num_pages);
975

976
	WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
977 978
		"No user pages to check\n");

979
	if (gtt->range) {
980 981 982 983 984 985
		/*
		 * FIXME: Must always hold notifier_lock for this, and must
		 * not ignore the return code.
		 */
		r = mmu_interval_read_retry(gtt->range->notifier,
					 gtt->range->notifier_seq);
986
		kvfree(gtt->range->hmm_pfns);
987 988
		kfree(gtt->range);
		gtt->range = NULL;
989
	}
990

991
	return !r;
992
}
993
#endif
994

995
/**
996
 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
997
 *
998
 * Called by amdgpu_cs_list_validate(). This creates the page list
999 1000
 * that backs user memory and will ultimately be mapped into the device
 * address space.
1001
 */
1002
void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
1003
{
1004
	unsigned long i;
1005

1006
	for (i = 0; i < ttm->num_pages; ++i)
1007
		ttm->pages[i] = pages ? pages[i] : NULL;
1008 1009
}

1010
/**
1011
 * amdgpu_ttm_tt_pin_userptr - 	prepare the sg table with the user pages
1012 1013 1014
 *
 * Called by amdgpu_ttm_backend_bind()
 **/
1015 1016
static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
				     struct ttm_tt *ttm)
1017
{
1018
	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1019 1020 1021 1022 1023 1024 1025
	struct amdgpu_ttm_tt *gtt = (void *)ttm;
	int r;

	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
	enum dma_data_direction direction = write ?
		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;

1026
	/* Allocate an SG array and squash pages into it */
1027 1028 1029 1030 1031 1032
	r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
				      ttm->num_pages << PAGE_SHIFT,
				      GFP_KERNEL);
	if (r)
		goto release_sg;

1033
	/* Map SG to device */
1034 1035
	r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
	if (r)
1036 1037
		goto release_sg;

1038
	/* convert SG to linear array of pages and dma addresses */
1039 1040 1041 1042 1043 1044 1045 1046 1047 1048
	drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
					 gtt->ttm.dma_address, ttm->num_pages);

	return 0;

release_sg:
	kfree(ttm->sg);
	return r;
}

1049 1050 1051
/**
 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 */
1052 1053
static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
					struct ttm_tt *ttm)
1054
{
1055
	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1056 1057 1058 1059 1060 1061 1062 1063 1064 1065
	struct amdgpu_ttm_tt *gtt = (void *)ttm;

	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
	enum dma_data_direction direction = write ?
		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;

	/* double check that we don't free the table twice */
	if (!ttm->sg->sgl)
		return;

1066
	/* unmap the pages mapped to the device */
1067
	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1068
	sg_free_table(ttm->sg);
1069

1070
#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1071 1072 1073 1074 1075
	if (gtt->range) {
		unsigned long i;

		for (i = 0; i < ttm->num_pages; i++) {
			if (ttm->pages[i] !=
1076
			    hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1077 1078 1079 1080 1081
				break;
		}

		WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
	}
1082
#endif
1083 1084
}

1085
static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1086 1087 1088 1089 1090 1091 1092 1093
				struct ttm_buffer_object *tbo,
				uint64_t flags)
{
	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
	struct ttm_tt *ttm = tbo->ttm;
	struct amdgpu_ttm_tt *gtt = (void *)ttm;
	int r;

1094 1095 1096
	if (amdgpu_bo_encrypted(abo))
		flags |= AMDGPU_PTE_TMZ;

1097
	if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1098 1099 1100 1101 1102 1103 1104
		uint64_t page_idx = 1;

		r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
				ttm->pages, gtt->ttm.dma_address, flags);
		if (r)
			goto gart_bind_fail;

1105 1106 1107 1108
		/* The memory type of the first page defaults to UC. Now
		 * modify the memory type to NC from the second page of
		 * the BO onward.
		 */
1109 1110
		flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
		flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123

		r = amdgpu_gart_bind(adev,
				gtt->offset + (page_idx << PAGE_SHIFT),
				ttm->num_pages - page_idx,
				&ttm->pages[page_idx],
				&(gtt->ttm.dma_address[page_idx]), flags);
	} else {
		r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
				     ttm->pages, gtt->ttm.dma_address, flags);
	}

gart_bind_fail:
	if (r)
1124
		DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
1125 1126 1127 1128 1129
			  ttm->num_pages, gtt->offset);

	return r;
}

1130 1131 1132 1133 1134 1135
/**
 * amdgpu_ttm_backend_bind - Bind GTT memory
 *
 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 * This handles binding GTT memory to the device address space.
 */
1136 1137
static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
				   struct ttm_tt *ttm,
1138
				   struct ttm_resource *bo_mem)
1139
{
1140
	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1141
	struct amdgpu_ttm_tt *gtt = (void*)ttm;
1142
	uint64_t flags;
1143
	int r = 0;
1144

1145 1146 1147 1148 1149 1150
	if (!bo_mem)
		return -EINVAL;

	if (gtt->bound)
		return 0;

1151
	if (gtt->userptr) {
1152
		r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
1153 1154 1155 1156 1157
		if (r) {
			DRM_ERROR("failed to pin userptr\n");
			return r;
		}
	}
1158
	if (!ttm->num_pages) {
1159
		WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
1160 1161 1162 1163 1164 1165 1166 1167
		     ttm->num_pages, bo_mem, ttm);
	}

	if (bo_mem->mem_type == AMDGPU_PL_GDS ||
	    bo_mem->mem_type == AMDGPU_PL_GWS ||
	    bo_mem->mem_type == AMDGPU_PL_OA)
		return -EINVAL;

1168 1169
	if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
		gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1170
		return 0;
1171
	}
1172

1173
	/* compute PTE flags relevant to this BO memory */
1174
	flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1175 1176

	/* bind pages into GART page tables */
1177
	gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1178
	r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1179 1180
		ttm->pages, gtt->ttm.dma_address, flags);

1181
	if (r)
1182
		DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
1183
			  ttm->num_pages, gtt->offset);
1184
	gtt->bound = true;
1185
	return r;
1186 1187
}

1188 1189 1190
/**
 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
 */
1191
int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1192
{
1193
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1194
	struct ttm_operation_ctx ctx = { false, false };
1195
	struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1196
	struct ttm_resource tmp;
1197 1198
	struct ttm_placement placement;
	struct ttm_place placements;
1199
	uint64_t addr, flags;
1200 1201
	int r;

1202
	if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1203 1204
		return 0;

1205 1206 1207 1208
	addr = amdgpu_gmc_agp_addr(bo);
	if (addr != AMDGPU_BO_INVALID_OFFSET) {
		bo->mem.start = addr >> PAGE_SHIFT;
	} else {
1209

1210 1211 1212 1213 1214 1215 1216 1217 1218
		/* allocate GART space */
		tmp = bo->mem;
		tmp.mm_node = NULL;
		placement.num_placement = 1;
		placement.placement = &placements;
		placement.num_busy_placement = 1;
		placement.busy_placement = &placements;
		placements.fpfn = 0;
		placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1219 1220
		placements.mem_type = TTM_PL_TT;
		placements.flags = bo->mem.placement;
1221 1222 1223 1224

		r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
		if (unlikely(r))
			return r;
1225

1226 1227
		/* compute PTE flags for this buffer object */
		flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1228

1229
		/* Bind pages */
1230
		gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1231 1232
		r = amdgpu_ttm_gart_bind(adev, bo, flags);
		if (unlikely(r)) {
1233
			ttm_resource_free(bo, &tmp);
1234 1235 1236
			return r;
		}

1237
		ttm_resource_free(bo, &bo->mem);
1238
		bo->mem = tmp;
1239
	}
1240

1241
	return 0;
1242 1243
}

1244 1245 1246 1247 1248 1249
/**
 * amdgpu_ttm_recover_gart - Rebind GTT pages
 *
 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
 * rebind GTT pages during a GPU reset.
 */
1250
int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1251
{
1252
	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1253
	uint64_t flags;
1254 1255
	int r;

1256
	if (!tbo->ttm)
1257 1258
		return 0;

1259 1260 1261
	flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
	r = amdgpu_ttm_gart_bind(adev, tbo, flags);

1262
	return r;
1263 1264
}

1265 1266 1267 1268 1269 1270
/**
 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
 *
 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
 * ttm_tt_destroy().
 */
1271 1272
static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
				      struct ttm_tt *ttm)
1273
{
1274
	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1275
	struct amdgpu_ttm_tt *gtt = (void *)ttm;
1276
	int r;
1277

1278 1279 1280
	if (!gtt->bound)
		return;

1281
	/* if the pages have userptr pinning then clear that first */
1282
	if (gtt->userptr)
1283
		amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1284

1285
	if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1286
		return;
1287

1288
	/* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1289
	r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1290
	if (r)
1291
		DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1292
			  gtt->ttm.num_pages, gtt->offset);
1293
	gtt->bound = false;
1294 1295
}

1296 1297
static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
				       struct ttm_tt *ttm)
1298 1299 1300
{
	struct amdgpu_ttm_tt *gtt = (void *)ttm;

1301
	amdgpu_ttm_backend_unbind(bdev, ttm);
1302
	ttm_tt_destroy_common(bdev, ttm);
1303 1304 1305
	if (gtt->usertask)
		put_task_struct(gtt->usertask);

1306
	ttm_tt_fini(&gtt->ttm);
1307 1308 1309
	kfree(gtt);
}

1310 1311 1312 1313 1314 1315 1316
/**
 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
 *
 * @bo: The buffer object to create a GTT ttm_tt object around
 *
 * Called by ttm_tt_create().
 */
1317 1318
static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
					   uint32_t page_flags)
1319
{
1320
	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1321
	struct amdgpu_ttm_tt *gtt;
1322
	enum ttm_caching caching;
1323 1324 1325 1326 1327

	gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
	if (gtt == NULL) {
		return NULL;
	}
1328
	gtt->gobj = &bo->base;
1329

1330 1331 1332 1333 1334
	if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
		caching = ttm_write_combined;
	else
		caching = ttm_cached;

1335
	/* allocate space for the uninitialized page entries */
1336
	if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1337 1338 1339
		kfree(gtt);
		return NULL;
	}
1340
	return &gtt->ttm;
1341 1342
}

1343 1344 1345 1346 1347 1348
/**
 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
 *
 * Map the pages of a ttm_tt object to an address space visible
 * to the underlying device.
 */
1349 1350 1351
static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
				  struct ttm_tt *ttm,
				  struct ttm_operation_ctx *ctx)
1352
{
1353
	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1354 1355
	struct amdgpu_ttm_tt *gtt = (void *)ttm;

1356
	/* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1357
	if (gtt && gtt->userptr) {
1358
		ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1359 1360 1361 1362 1363 1364 1365
		if (!ttm->sg)
			return -ENOMEM;

		ttm->page_flags |= TTM_PAGE_FLAG_SG;
		return 0;
	}

1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378
	if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
		if (!ttm->sg) {
			struct dma_buf_attachment *attach;
			struct sg_table *sgt;

			attach = gtt->gobj->import_attach;
			sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
			if (IS_ERR(sgt))
				return PTR_ERR(sgt);

			ttm->sg = sgt;
		}

1379
		drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1380 1381
						 gtt->ttm.dma_address,
						 ttm->num_pages);
1382
		return 0;
1383 1384
	}

1385
	return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1386 1387
}

1388 1389 1390 1391 1392 1393
/**
 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
 *
 * Unmaps pages of a ttm_tt object from the device address space and
 * unpopulates the page array backing it.
 */
1394 1395
static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev,
				     struct ttm_tt *ttm)
1396 1397
{
	struct amdgpu_ttm_tt *gtt = (void *)ttm;
1398
	struct amdgpu_device *adev;
1399 1400

	if (gtt && gtt->userptr) {
1401
		amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1402 1403 1404 1405 1406
		kfree(ttm->sg);
		ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
		return;
	}

1407 1408 1409 1410 1411 1412 1413 1414 1415 1416
	if (ttm->sg && gtt->gobj->import_attach) {
		struct dma_buf_attachment *attach;

		attach = gtt->gobj->import_attach;
		dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
		ttm->sg = NULL;
		return;
	}

	if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1417 1418
		return;

1419
	adev = amdgpu_ttm_adev(bdev);
1420
	return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1421 1422
}

1423
/**
1424 1425
 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
 * task
1426
 *
1427
 * @bo: The ttm_buffer_object to bind this userptr to
1428 1429 1430 1431 1432 1433
 * @addr:  The address in the current tasks VM space to use
 * @flags: Requirements of userptr object.
 *
 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
 * to current task
 */
1434 1435
int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
			      uint64_t addr, uint32_t flags)
1436
{
1437
	struct amdgpu_ttm_tt *gtt;
1438

1439 1440 1441 1442 1443 1444
	if (!bo->ttm) {
		/* TODO: We want a separate TTM object type for userptrs */
		bo->ttm = amdgpu_ttm_tt_create(bo, 0);
		if (bo->ttm == NULL)
			return -ENOMEM;
	}
1445

1446
	gtt = (void*)bo->ttm;
1447 1448
	gtt->userptr = addr;
	gtt->userflags = flags;
1449 1450 1451 1452 1453 1454

	if (gtt->usertask)
		put_task_struct(gtt->usertask);
	gtt->usertask = current->group_leader;
	get_task_struct(gtt->usertask);

1455 1456 1457
	return 0;
}

1458 1459 1460
/**
 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
 */
1461
struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1462 1463 1464 1465
{
	struct amdgpu_ttm_tt *gtt = (void *)ttm;

	if (gtt == NULL)
1466
		return NULL;
1467

1468 1469 1470 1471
	if (gtt->usertask == NULL)
		return NULL;

	return gtt->usertask->mm;
1472 1473
}

1474
/**
1475 1476
 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
 * address range for the current task.
1477 1478
 *
 */
1479 1480 1481 1482 1483 1484
bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
				  unsigned long end)
{
	struct amdgpu_ttm_tt *gtt = (void *)ttm;
	unsigned long size;

1485
	if (gtt == NULL || !gtt->userptr)
1486 1487
		return false;

1488 1489 1490
	/* Return false if no part of the ttm_tt object lies within
	 * the range
	 */
1491
	size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1492 1493 1494 1495 1496 1497
	if (gtt->userptr > end || gtt->userptr + size <= start)
		return false;

	return true;
}

1498
/**
1499
 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1500
 */
1501
bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1502 1503 1504 1505 1506 1507
{
	struct amdgpu_ttm_tt *gtt = (void *)ttm;

	if (gtt == NULL || !gtt->userptr)
		return false;

1508
	return true;
1509 1510
}

1511 1512 1513
/**
 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
 */
1514 1515 1516 1517 1518 1519 1520 1521 1522 1523
bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
{
	struct amdgpu_ttm_tt *gtt = (void *)ttm;

	if (gtt == NULL)
		return false;

	return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
}

1524
/**
1525
 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1526 1527 1528
 *
 * @ttm: The ttm_tt object to compute the flags for
 * @mem: The memory registry backing this ttm_tt object
1529 1530
 *
 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1531
 */
1532
uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1533
{
1534
	uint64_t flags = 0;
1535 1536 1537 1538

	if (mem && mem->mem_type != TTM_PL_SYSTEM)
		flags |= AMDGPU_PTE_VALID;

1539
	if (mem && mem->mem_type == TTM_PL_TT) {
1540 1541
		flags |= AMDGPU_PTE_SYSTEM;

1542
		if (ttm->caching == ttm_cached)
1543 1544
			flags |= AMDGPU_PTE_SNOOPED;
	}
1545

1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557
	return flags;
}

/**
 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
 *
 * @ttm: The ttm_tt object to compute the flags for
 * @mem: The memory registry backing this ttm_tt object

 * Figure out the flags to use for a VM PTE (Page Table Entry).
 */
uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1558
				 struct ttm_resource *mem)
1559 1560 1561
{
	uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);

1562
	flags |= adev->gart.gart_pte_flags;
1563 1564 1565 1566 1567 1568 1569 1570
	flags |= AMDGPU_PTE_READABLE;

	if (!amdgpu_ttm_tt_is_readonly(ttm))
		flags |= AMDGPU_PTE_WRITEABLE;

	return flags;
}

1571
/**
1572 1573
 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
 * object.
1574
 *
1575 1576 1577
 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1578 1579
 * used to clean out a memory space.
 */
1580 1581 1582
static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
					    const struct ttm_place *place)
{
1583 1584
	unsigned long num_pages = bo->mem.num_pages;
	struct drm_mm_node *node = bo->mem.mm_node;
1585
	struct dma_resv_list *flist;
1586 1587 1588
	struct dma_fence *f;
	int i;

1589
	if (bo->type == ttm_bo_type_kernel &&
1590
	    !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1591 1592
		return false;

1593 1594 1595 1596
	/* If bo is a KFD BO, check if the bo belongs to the current process.
	 * If true, then return false as any KFD process needs all its BOs to
	 * be resident to run successfully
	 */
1597
	flist = dma_resv_get_list(bo->base.resv);
1598 1599 1600
	if (flist) {
		for (i = 0; i < flist->shared_count; ++i) {
			f = rcu_dereference_protected(flist->shared[i],
1601
				dma_resv_held(bo->base.resv));
1602 1603 1604 1605
			if (amdkfd_fence_check_mm(f, current->mm))
				return false;
		}
	}
1606

1607 1608
	switch (bo->mem.mem_type) {
	case TTM_PL_TT:
1609 1610 1611
		if (amdgpu_bo_is_amdgpu_bo(bo) &&
		    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
			return false;
1612
		return true;
1613

1614
	case TTM_PL_VRAM:
1615 1616 1617 1618 1619 1620 1621 1622 1623
		/* Check each drm MM node individually */
		while (num_pages) {
			if (place->fpfn < (node->start + node->size) &&
			    !(place->lpfn && place->lpfn <= node->start))
				return true;

			num_pages -= node->size;
			++node;
		}
1624
		return false;
1625

1626 1627
	default:
		break;
1628 1629 1630 1631 1632
	}

	return ttm_bo_eviction_valuable(bo, place);
}

1633
/**
1634
 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1635 1636 1637 1638 1639 1640 1641 1642 1643 1644
 *
 * @bo:  The buffer object to read/write
 * @offset:  Offset into buffer object
 * @buf:  Secondary buffer to write/read from
 * @len: Length in bytes of access
 * @write:  true if writing
 *
 * This is used to access VRAM that backs a buffer object via MMIO
 * access for debugging purposes.
 */
1645 1646 1647 1648
static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
				    unsigned long offset,
				    void *buf, int len, int write)
{
1649
	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1650
	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1651
	struct drm_mm_node *nodes;
1652 1653 1654 1655 1656 1657 1658 1659
	uint32_t value = 0;
	int ret = 0;
	uint64_t pos;
	unsigned long flags;

	if (bo->mem.mem_type != TTM_PL_VRAM)
		return -EIO;

1660 1661 1662
	pos = offset;
	nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
	pos += (nodes->start << PAGE_SHIFT);
1663

1664
	while (len && pos < adev->gmc.mc_vram_size) {
1665
		uint64_t aligned_pos = pos & ~(uint64_t)3;
1666
		uint64_t bytes = 4 - (pos & 3);
1667 1668 1669 1670 1671 1672 1673 1674
		uint32_t shift = (pos & 3) * 8;
		uint32_t mask = 0xffffffff << shift;

		if (len < bytes) {
			mask &= 0xffffffff >> (bytes - len) * 8;
			bytes = len;
		}

1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696
		if (mask != 0xffffffff) {
			spin_lock_irqsave(&adev->mmio_idx_lock, flags);
			WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
			WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
			if (!write || mask != 0xffffffff)
				value = RREG32_NO_KIQ(mmMM_DATA);
			if (write) {
				value &= ~mask;
				value |= (*(uint32_t *)buf << shift) & mask;
				WREG32_NO_KIQ(mmMM_DATA, value);
			}
			spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
			if (!write) {
				value = (value & mask) >> shift;
				memcpy(buf, &value, bytes);
			}
		} else {
			bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
			bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);

			amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
						  bytes, write);
1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711
		}

		ret += bytes;
		buf = (uint8_t *)buf + bytes;
		pos += bytes;
		len -= bytes;
		if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
			++nodes;
			pos = (nodes->start << PAGE_SHIFT);
		}
	}

	return ret;
}

1712 1713 1714 1715 1716 1717
static void
amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
{
	amdgpu_bo_move_notify(bo, false, NULL);
}

1718 1719 1720 1721
static struct ttm_bo_driver amdgpu_bo_driver = {
	.ttm_tt_create = &amdgpu_ttm_tt_create,
	.ttm_tt_populate = &amdgpu_ttm_tt_populate,
	.ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1722
	.ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1723
	.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1724 1725 1726
	.evict_flags = &amdgpu_evict_flags,
	.move = &amdgpu_bo_move,
	.verify_access = &amdgpu_verify_access,
1727
	.delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1728
	.release_notify = &amdgpu_bo_release_notify,
1729
	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1730
	.io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1731 1732
	.access_memory = &amdgpu_ttm_access_memory,
	.del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1733 1734
};

1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746
/*
 * Firmware Reservation functions
 */
/**
 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
 *
 * @adev: amdgpu_device pointer
 *
 * free fw reserved vram if it has been reserved.
 */
static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
{
1747 1748
	amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
		NULL, &adev->mman.fw_vram_usage_va);
1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759
}

/**
 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
 *
 * @adev: amdgpu_device pointer
 *
 * create bo vram reservation from fw.
 */
static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
{
1760 1761
	uint64_t vram_size = adev->gmc.visible_vram_size;

1762 1763
	adev->mman.fw_vram_usage_va = NULL;
	adev->mman.fw_vram_usage_reserved_bo = NULL;
1764

1765 1766
	if (adev->mman.fw_vram_usage_size == 0 ||
	    adev->mman.fw_vram_usage_size > vram_size)
1767
		return 0;
1768

1769
	return amdgpu_bo_create_kernel_at(adev,
1770 1771
					  adev->mman.fw_vram_usage_start_offset,
					  adev->mman.fw_vram_usage_size,
1772
					  AMDGPU_GEM_DOMAIN_VRAM,
1773 1774
					  &adev->mman.fw_vram_usage_reserved_bo,
					  &adev->mman.fw_vram_usage_va);
1775
}
1776

1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798
/*
 * Memoy training reservation functions
 */

/**
 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
 *
 * @adev: amdgpu_device pointer
 *
 * free memory training reserved vram if it has been reserved.
 */
static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
{
	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;

	ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
	amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
	ctx->c2p_bo = NULL;

	return 0;
}

1799
static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1800
{
1801
	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1802

1803
	memset(ctx, 0, sizeof(*ctx));
1804

1805
	ctx->c2p_train_data_offset =
1806
		ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1807 1808 1809 1810 1811 1812 1813 1814 1815
	ctx->p2c_train_data_offset =
		(adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
	ctx->train_data_size =
		GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
	
	DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
			ctx->train_data_size,
			ctx->p2c_train_data_offset,
			ctx->c2p_train_data_offset);
1816 1817
}

1818 1819 1820
/*
 * reserve TMR memory at the top of VRAM which holds
 * IP Discovery data and is protected by PSP.
1821
 */
1822
static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1823 1824 1825
{
	int ret;
	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1826
	bool mem_train_support = false;
1827

1828
	if (!amdgpu_sriov_vf(adev)) {
1829
		ret = amdgpu_mem_train_support(adev);
1830
		if (ret == 1)
1831
			mem_train_support = true;
1832
		else if (ret == -1)
1833 1834
			return -EINVAL;
		else
1835
			DRM_DEBUG("memory training does not support!\n");
1836 1837
	}

1838 1839 1840 1841 1842 1843 1844
	/*
	 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
	 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
	 *
	 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
	 * discovery data and G6 memory training data respectively
	 */
1845
	adev->mman.discovery_tmr_size =
1846
		amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1847 1848
	if (!adev->mman.discovery_tmr_size)
		adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1849 1850 1851 1852 1853

	if (mem_train_support) {
		/* reserve vram for mem train according to TMR location */
		amdgpu_ttm_training_data_block_init(adev);
		ret = amdgpu_bo_create_kernel_at(adev,
1854 1855 1856 1857 1858
					 ctx->c2p_train_data_offset,
					 ctx->train_data_size,
					 AMDGPU_GEM_DOMAIN_VRAM,
					 &ctx->c2p_bo,
					 NULL);
1859 1860 1861 1862
		if (ret) {
			DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
			amdgpu_ttm_training_reserve_vram_fini(adev);
			return ret;
1863
		}
1864
		ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1865
	}
1866 1867

	ret = amdgpu_bo_create_kernel_at(adev,
1868 1869
				adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
				adev->mman.discovery_tmr_size,
1870
				AMDGPU_GEM_DOMAIN_VRAM,
1871
				&adev->mman.discovery_memory,
1872
				NULL);
1873
	if (ret) {
1874
		DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1875
		amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1876
		return ret;
1877 1878 1879 1880 1881
	}

	return 0;
}

1882
/**
1883 1884
 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
 * gtt/vram related fields.
1885 1886 1887 1888 1889 1890
 *
 * This initializes all of the memory space pools that the TTM layer
 * will need such as the GTT space (system memory mapped to the device),
 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
 * can be mapped per VMID.
 */
1891 1892
int amdgpu_ttm_init(struct amdgpu_device *adev)
{
1893
	uint64_t gtt_size;
1894
	int r;
1895
	u64 vis_vram_limit;
1896

1897 1898
	mutex_init(&adev->mman.gtt_window_lock);

1899
	/* No others user of address space so set it to 0 */
1900
	r = ttm_bo_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1901 1902
			       adev_to_drm(adev)->anon_inode->i_mapping,
			       adev_to_drm(adev)->vma_offset_manager,
1903
			       adev->need_swiotlb,
1904
			       dma_addressing_limited(adev->dev));
1905 1906 1907 1908 1909
	if (r) {
		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
		return r;
	}
	adev->mman.initialized = true;
1910 1911 1912 1913

	/* We opt to avoid OOM on system pages allocations */
	adev->mman.bdev.no_retry = true;

1914
	/* Initialize VRAM pool with all of VRAM divided into pages */
1915
	r = amdgpu_vram_mgr_init(adev);
1916 1917 1918 1919
	if (r) {
		DRM_ERROR("Failed initializing VRAM heap.\n");
		return r;
	}
1920 1921 1922 1923

	/* Reduce size of CPU-visible VRAM if requested */
	vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
	if (amdgpu_vis_vram_limit > 0 &&
1924 1925
	    vis_vram_limit <= adev->gmc.visible_vram_size)
		adev->gmc.visible_vram_size = vis_vram_limit;
1926

1927
	/* Change the size here instead of the init above so only lpfn is affected */
1928
	amdgpu_ttm_set_buffer_funcs_status(adev, false);
1929 1930 1931 1932
#ifdef CONFIG_64BIT
	adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
						adev->gmc.visible_vram_size);
#endif
1933

1934 1935 1936 1937
	/*
	 *The reserved vram for firmware must be pinned to the specified
	 *place on the VRAM, so reserve it early.
	 */
1938
	r = amdgpu_ttm_fw_reserve_vram_init(adev);
1939 1940 1941 1942
	if (r) {
		return r;
	}

1943
	/*
1944 1945 1946
	 * only NAVI10 and onwards ASIC support for IP discovery.
	 * If IP discovery enabled, a block of memory should be
	 * reserved for IP discovey.
1947
	 */
1948
	if (adev->mman.discovery_bin) {
1949
		r = amdgpu_ttm_reserve_tmr(adev);
1950 1951 1952
		if (r)
			return r;
	}
1953

1954 1955 1956 1957
	/* allocate memory as required for VGA
	 * This is used for VGA emulation and pre-OS scanout buffers to
	 * avoid display artifacts while transitioning between pre-OS
	 * and driver.  */
1958
	r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1959
				       AMDGPU_GEM_DOMAIN_VRAM,
1960
				       &adev->mman.stolen_vga_memory,
1961
				       NULL);
1962 1963
	if (r)
		return r;
1964 1965
	r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
				       adev->mman.stolen_extended_size,
1966
				       AMDGPU_GEM_DOMAIN_VRAM,
1967
				       &adev->mman.stolen_extended_memory,
1968
				       NULL);
1969 1970
	if (r)
		return r;
1971

1972
	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1973
		 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1974

1975 1976
	/* Compute GTT size, either bsaed on 3/4th the size of RAM size
	 * or whatever the user passed on module init */
1977 1978 1979 1980
	if (amdgpu_gtt_size == -1) {
		struct sysinfo si;

		si_meminfo(&si);
1981
		gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1982
			       adev->gmc.mc_vram_size),
1983 1984 1985
			       ((uint64_t)si.totalram * si.mem_unit * 3/4));
	}
	else
1986
		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1987 1988

	/* Initialize GTT memory pool */
1989
	r = amdgpu_gtt_mgr_init(adev, gtt_size);
1990 1991 1992 1993 1994
	if (r) {
		DRM_ERROR("Failed initializing GTT heap.\n");
		return r;
	}
	DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1995
		 (unsigned)(gtt_size / (1024 * 1024)));
1996

1997
	/* Initialize various on-chip memory pools */
1998
	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1999 2000 2001
	if (r) {
		DRM_ERROR("Failed initializing GDS heap.\n");
		return r;
2002 2003
	}

2004
	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
2005 2006 2007
	if (r) {
		DRM_ERROR("Failed initializing gws heap.\n");
		return r;
2008 2009
	}

2010
	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
2011 2012 2013
	if (r) {
		DRM_ERROR("Failed initializing oa heap.\n");
		return r;
2014 2015 2016 2017 2018
	}

	return 0;
}

2019
/**
2020
 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2021
 */
2022 2023
void amdgpu_ttm_late_init(struct amdgpu_device *adev)
{
2024
	/* return the VGA stolen memory (if any) back to VRAM */
2025 2026 2027
	if (!adev->mman.keep_stolen_vga_memory)
		amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
	amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
2028 2029
}

2030 2031 2032
/**
 * amdgpu_ttm_fini - De-initialize the TTM memory pools
 */
2033 2034 2035 2036
void amdgpu_ttm_fini(struct amdgpu_device *adev)
{
	if (!adev->mman.initialized)
		return;
2037

2038
	amdgpu_ttm_training_reserve_vram_fini(adev);
2039
	/* return the stolen vga memory back to VRAM */
2040 2041
	if (adev->mman.keep_stolen_vga_memory)
		amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2042
	/* return the IP Discovery TMR memory back to VRAM */
2043
	amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
2044
	amdgpu_ttm_fw_reserve_vram_fini(adev);
2045

2046 2047 2048
	if (adev->mman.aper_base_kaddr)
		iounmap(adev->mman.aper_base_kaddr);
	adev->mman.aper_base_kaddr = NULL;
2049

2050 2051
	amdgpu_vram_mgr_fini(adev);
	amdgpu_gtt_mgr_fini(adev);
2052 2053 2054
	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2055 2056 2057 2058 2059
	ttm_bo_device_release(&adev->mman.bdev);
	adev->mman.initialized = false;
	DRM_INFO("amdgpu: ttm finalized\n");
}

2060 2061 2062 2063 2064 2065 2066 2067 2068 2069
/**
 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
 *
 * @adev: amdgpu_device pointer
 * @enable: true when we can use buffer functions.
 *
 * Enable/disable use of buffer functions during suspend/resume. This should
 * only be called at bootup or when userspace isn't running.
 */
void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2070
{
2071
	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2072
	uint64_t size;
2073
	int r;
2074

2075
	if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2076
	    adev->mman.buffer_funcs_enabled == enable)
2077 2078
		return;

2079 2080
	if (enable) {
		struct amdgpu_ring *ring;
2081
		struct drm_gpu_scheduler *sched;
2082 2083

		ring = adev->mman.buffer_funcs_ring;
2084 2085
		sched = &ring->sched;
		r = drm_sched_entity_init(&adev->mman.entity,
2086
					  DRM_SCHED_PRIORITY_KERNEL, &sched,
2087
					  1, NULL);
2088 2089 2090 2091 2092 2093
		if (r) {
			DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
				  r);
			return;
		}
	} else {
2094
		drm_sched_entity_destroy(&adev->mman.entity);
2095 2096
		dma_fence_put(man->move);
		man->move = NULL;
2097 2098
	}

2099
	/* this just adjusts TTM size idea, which sets lpfn to the correct value */
2100 2101 2102 2103
	if (enable)
		size = adev->gmc.real_vram_size;
	else
		size = adev->gmc.visible_vram_size;
2104
	man->size = size >> PAGE_SHIFT;
2105
	adev->mman.buffer_funcs_enabled = enable;
2106 2107
}

2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137
static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
{
	struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
	vm_fault_t ret;

	ret = ttm_bo_vm_reserve(bo, vmf);
	if (ret)
		return ret;

	ret = amdgpu_bo_fault_reserve_notify(bo);
	if (ret)
		goto unlock;

	ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
				       TTM_BO_VM_NUM_PREFAULT, 1);
	if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
		return ret;

unlock:
	dma_resv_unlock(bo->base.resv);
	return ret;
}

static struct vm_operations_struct amdgpu_ttm_vm_ops = {
	.fault = amdgpu_ttm_fault,
	.open = ttm_bo_vm_open,
	.close = ttm_bo_vm_close,
	.access = ttm_bo_vm_access
};

2138 2139
int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
{
2140
	struct drm_file *file_priv = filp->private_data;
2141
	struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
2142
	int r;
2143

2144 2145 2146
	r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
	if (unlikely(r != 0))
		return r;
2147

2148 2149
	vma->vm_ops = &amdgpu_ttm_vm_ops;
	return 0;
2150 2151
}

2152 2153
int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
		       uint64_t dst_offset, uint32_t byte_count,
2154
		       struct dma_resv *resv,
2155
		       struct dma_fence **fence, bool direct_submit,
2156
		       bool vm_needs_flush, bool tmz)
2157
{
2158 2159
	enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
		AMDGPU_IB_POOL_DELAYED;
2160
	struct amdgpu_device *adev = ring->adev;
2161 2162
	struct amdgpu_job *job;

2163 2164 2165 2166 2167
	uint32_t max_bytes;
	unsigned num_loops, num_dw;
	unsigned i;
	int r;

2168
	if (direct_submit && !ring->sched.ready) {
2169 2170 2171 2172
		DRM_ERROR("Trying to move memory with ring turned off.\n");
		return -EINVAL;
	}

2173 2174
	max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
	num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2175
	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2176

2177
	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2178
	if (r)
2179
		return r;
2180

2181
	if (vm_needs_flush) {
2182
		job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2183 2184
		job->vm_needs_flush = true;
	}
2185
	if (resv) {
2186
		r = amdgpu_sync_resv(adev, &job->sync, resv,
2187 2188
				     AMDGPU_SYNC_ALWAYS,
				     AMDGPU_FENCE_OWNER_UNDEFINED);
2189 2190 2191 2192
		if (r) {
			DRM_ERROR("sync failed (%d).\n", r);
			goto error_free;
		}
2193 2194 2195 2196 2197
	}

	for (i = 0; i < num_loops; i++) {
		uint32_t cur_size_in_bytes = min(byte_count, max_bytes);

2198
		amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2199
					dst_offset, cur_size_in_bytes, tmz);
2200 2201 2202 2203 2204 2205

		src_offset += cur_size_in_bytes;
		dst_offset += cur_size_in_bytes;
		byte_count -= cur_size_in_bytes;
	}

2206 2207
	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
	WARN_ON(job->ibs[0].length_dw > num_dw);
2208 2209 2210
	if (direct_submit)
		r = amdgpu_job_submit_direct(job, ring, fence);
	else
2211
		r = amdgpu_job_submit(job, &adev->mman.entity,
2212
				      AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2213 2214
	if (r)
		goto error_free;
2215

2216
	return r;
2217

2218
error_free:
2219
	amdgpu_job_free(job);
2220
	DRM_ERROR("Error scheduling IBs (%d)\n", r);
2221
	return r;
2222 2223
}

2224
int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2225
		       uint32_t src_data,
2226
		       struct dma_resv *resv,
2227
		       struct dma_fence **fence)
2228
{
2229
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2230
	uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2231 2232
	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;

2233 2234
	struct drm_mm_node *mm_node;
	unsigned long num_pages;
2235
	unsigned int num_loops, num_dw;
2236 2237

	struct amdgpu_job *job;
2238 2239
	int r;

2240
	if (!adev->mman.buffer_funcs_enabled) {
2241 2242 2243 2244
		DRM_ERROR("Trying to clear memory with ring turned off.\n");
		return -EINVAL;
	}

2245
	if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2246
		r = amdgpu_ttm_alloc_gart(&bo->tbo);
2247 2248 2249 2250
		if (r)
			return r;
	}

2251 2252 2253 2254
	num_pages = bo->tbo.num_pages;
	mm_node = bo->tbo.mem.mm_node;
	num_loops = 0;
	while (num_pages) {
2255
		uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2256

2257
		num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2258 2259 2260
		num_pages -= mm_node->size;
		++mm_node;
	}
2261
	num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2262 2263

	/* for IB padding */
2264
	num_dw += 64;
2265

2266 2267
	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
				     &job);
2268 2269 2270 2271 2272
	if (r)
		return r;

	if (resv) {
		r = amdgpu_sync_resv(adev, &job->sync, resv,
2273 2274
				     AMDGPU_SYNC_ALWAYS,
				     AMDGPU_FENCE_OWNER_UNDEFINED);
2275 2276 2277 2278 2279 2280
		if (r) {
			DRM_ERROR("sync failed (%d).\n", r);
			goto error_free;
		}
	}

2281 2282
	num_pages = bo->tbo.num_pages;
	mm_node = bo->tbo.mem.mm_node;
2283

2284
	while (num_pages) {
2285
		uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2286
		uint64_t dst_addr;
2287

2288
		dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
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		while (byte_count) {
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			uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
							   max_bytes);
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			amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
						dst_addr, cur_size_in_bytes);
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			dst_addr += cur_size_in_bytes;
			byte_count -= cur_size_in_bytes;
		}

		num_pages -= mm_node->size;
		++mm_node;
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	}

	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
	WARN_ON(job->ibs[0].length_dw > num_dw);
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	r = amdgpu_job_submit(job, &adev->mman.entity,
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			      AMDGPU_FENCE_OWNER_UNDEFINED, fence);
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	if (r)
		goto error_free;

	return 0;

error_free:
	amdgpu_job_free(job);
	return r;
}

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#if defined(CONFIG_DEBUG_FS)

static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
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	unsigned ttm_pl = (uintptr_t)node->info_ent->data;
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	struct drm_device *dev = node->minor->dev;
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	struct amdgpu_device *adev = drm_to_adev(dev);
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	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
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	struct drm_printer p = drm_seq_file_printer(m);
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	man->func->debug(man, &p);
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	return 0;
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}

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static int amdgpu_ttm_pool_debugfs(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *)m->private;
	struct drm_device *dev = node->minor->dev;
	struct amdgpu_device *adev = drm_to_adev(dev);

	return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
}

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static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
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	{"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
	{"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
	{"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
	{"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
	{"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
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	{"ttm_page_pool", amdgpu_ttm_pool_debugfs, 0, NULL},
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};

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/**
 * amdgpu_ttm_vram_read - Linear read access to VRAM
 *
 * Accesses VRAM via MMIO for debugging purposes.
 */
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static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
				    size_t size, loff_t *pos)
{
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	struct amdgpu_device *adev = file_inode(f)->i_private;
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	ssize_t result = 0;

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

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	if (*pos >= adev->gmc.mc_vram_size)
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		return -ENXIO;

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	size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
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	while (size) {
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		size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
		uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
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		amdgpu_device_vram_access(adev, *pos, value, bytes, false);
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		if (copy_to_user(buf, value, bytes))
			return -EFAULT;
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		result += bytes;
		buf += bytes;
		*pos += bytes;
		size -= bytes;
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	}

	return result;
}

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/**
 * amdgpu_ttm_vram_write - Linear write access to VRAM
 *
 * Accesses VRAM via MMIO for debugging purposes.
 */
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static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
				    size_t size, loff_t *pos)
{
	struct amdgpu_device *adev = file_inode(f)->i_private;
	ssize_t result = 0;
	int r;

	if (size & 0x3 || *pos & 0x3)
		return -EINVAL;

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	if (*pos >= adev->gmc.mc_vram_size)
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		return -ENXIO;

	while (size) {
		unsigned long flags;
		uint32_t value;

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		if (*pos >= adev->gmc.mc_vram_size)
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			return result;

		r = get_user(value, (uint32_t *)buf);
		if (r)
			return r;

		spin_lock_irqsave(&adev->mmio_idx_lock, flags);
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		WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
		WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
		WREG32_NO_KIQ(mmMM_DATA, value);
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		spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);

		result += 4;
		buf += 4;
		*pos += 4;
		size -= 4;
	}

	return result;
}

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static const struct file_operations amdgpu_ttm_vram_fops = {
	.owner = THIS_MODULE,
	.read = amdgpu_ttm_vram_read,
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	.write = amdgpu_ttm_vram_write,
	.llseek = default_llseek,
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};

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#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS

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/**
 * amdgpu_ttm_gtt_read - Linear read access to GTT memory
 */
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static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
				   size_t size, loff_t *pos)
{
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	struct amdgpu_device *adev = file_inode(f)->i_private;
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	ssize_t result = 0;
	int r;

	while (size) {
		loff_t p = *pos / PAGE_SIZE;
		unsigned off = *pos & ~PAGE_MASK;
		size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
		struct page *page;
		void *ptr;

		if (p >= adev->gart.num_cpu_pages)
			return result;

		page = adev->gart.pages[p];
		if (page) {
			ptr = kmap(page);
			ptr += off;

			r = copy_to_user(buf, ptr, cur_size);
			kunmap(adev->gart.pages[p]);
		} else
			r = clear_user(buf, cur_size);

		if (r)
			return -EFAULT;

		result += cur_size;
		buf += cur_size;
		*pos += cur_size;
		size -= cur_size;
	}

	return result;
}

static const struct file_operations amdgpu_ttm_gtt_fops = {
	.owner = THIS_MODULE,
	.read = amdgpu_ttm_gtt_read,
	.llseek = default_llseek
};

#endif

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/**
 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
 *
 * This function is used to read memory that has been mapped to the
 * GPU and the known addresses are not physical addresses but instead
 * bus addresses (e.g., what you'd put in an IB or ring buffer).
 */
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static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
				 size_t size, loff_t *pos)
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{
	struct amdgpu_device *adev = file_inode(f)->i_private;
	struct iommu_domain *dom;
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	ssize_t result = 0;
	int r;
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2504
	/* retrieve the IOMMU domain if any for this device */
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	dom = iommu_get_domain_for_dev(adev->dev);
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	while (size) {
		phys_addr_t addr = *pos & PAGE_MASK;
		loff_t off = *pos & ~PAGE_MASK;
		size_t bytes = PAGE_SIZE - off;
		unsigned long pfn;
		struct page *p;
		void *ptr;

		bytes = bytes < size ? bytes : size;

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		/* Translate the bus address to a physical address.  If
		 * the domain is NULL it means there is no IOMMU active
		 * and the address translation is the identity
		 */
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		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;

		pfn = addr >> PAGE_SHIFT;
		if (!pfn_valid(pfn))
			return -EPERM;

		p = pfn_to_page(pfn);
		if (p->mapping != adev->mman.bdev.dev_mapping)
			return -EPERM;

		ptr = kmap(p);
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		r = copy_to_user(buf, ptr + off, bytes);
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		kunmap(p);
		if (r)
			return -EFAULT;

		size -= bytes;
		*pos += bytes;
		result += bytes;
	}

	return result;
}

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/**
 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
 *
 * This function is used to write memory that has been mapped to the
 * GPU and the known addresses are not physical addresses but instead
 * bus addresses (e.g., what you'd put in an IB or ring buffer).
 */
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static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
				 size_t size, loff_t *pos)
{
	struct amdgpu_device *adev = file_inode(f)->i_private;
	struct iommu_domain *dom;
	ssize_t result = 0;
	int r;
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	dom = iommu_get_domain_for_dev(adev->dev);
2561

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	while (size) {
		phys_addr_t addr = *pos & PAGE_MASK;
		loff_t off = *pos & ~PAGE_MASK;
		size_t bytes = PAGE_SIZE - off;
		unsigned long pfn;
		struct page *p;
		void *ptr;

		bytes = bytes < size ? bytes : size;
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		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;

		pfn = addr >> PAGE_SHIFT;
		if (!pfn_valid(pfn))
			return -EPERM;

		p = pfn_to_page(pfn);
		if (p->mapping != adev->mman.bdev.dev_mapping)
			return -EPERM;

		ptr = kmap(p);
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		r = copy_from_user(ptr + off, buf, bytes);
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		kunmap(p);
		if (r)
			return -EFAULT;

		size -= bytes;
		*pos += bytes;
		result += bytes;
	}

	return result;
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}

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static const struct file_operations amdgpu_ttm_iomem_fops = {
2597
	.owner = THIS_MODULE,
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	.read = amdgpu_iomem_read,
	.write = amdgpu_iomem_write,
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	.llseek = default_llseek
};
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static const struct {
	char *name;
	const struct file_operations *fops;
	int domain;
} ttm_debugfs_entries[] = {
	{ "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
	{ "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
#endif
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	{ "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
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};

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#endif

2617
int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
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{
#if defined(CONFIG_DEBUG_FS)
	unsigned count;

2622
	struct drm_minor *minor = adev_to_drm(adev)->primary;
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	struct dentry *ent, *root = minor->debugfs_root;

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	for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
		ent = debugfs_create_file(
				ttm_debugfs_entries[count].name,
				S_IFREG | S_IRUGO, root,
				adev,
				ttm_debugfs_entries[count].fops);
		if (IS_ERR(ent))
			return PTR_ERR(ent);
		if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
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			i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2635
		else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2636
			i_size_write(ent->d_inode, adev->gmc.gart_size);
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		adev->mman.debugfs_entries[count] = ent;
	}
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	count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
	return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
#else
	return 0;
#endif
}