• Ville Syrjälä's avatar
    drm/i915: Two stage watermarks for g4x · 04548cba
    Ville Syrjälä authored
    Implement proper two stage watermark programming for g4x. As with
    other pre-SKL platforms, the watermark registers aren't double
    buffered on g4x. Hence we must sequence the watermark update
    carefully around plane updates.
    
    The code is quite heavily modelled on the VLV/CHV code, with some
    fairly significant differences due to the different hardware
    architecture:
    * g4x doesn't use inverted watermark values
    * CxSR actually affects the watermarks since it controls memory self
      refresh in addition to the max FIFO mode
    * A further HPLL SR mode is possible with higher memory wakeup
      latency
    * g4x has FBC2 and so it also has FBC watermarks
    * max FIFO mode for primary plane only (cursor is allowed, sprite is not)
    * g4x has no manual FIFO repartitioning
    * some TLB miss related workarounds are needed for the watermarks
    
    Actually the hardware is quite similar to ILK+ in many ways. The
    most visible differences are in the actual watermakr register
    layout. ILK revamped that part quite heavily whereas g4x is still
    using the layout inherited from earlier platforms.
    
    Note that we didn't previously enable the HPLL SR on g4x. So in order
    to not introduce too many functional changes in this patch I've not
    actually enabled it here either, even though the code is now fully
    ready for it. We'll enable it separately later on.
    Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Link: http://patchwork.freedesktop.org/patch/msgid/20170421181432.15216-13-ville.syrjala@linux.intel.comReviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
    04548cba
intel_drv.h 64.5 KB