• Huacai Chen's avatar
    MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENT · 1e820da3
    Huacai Chen authored
    New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A R1,
    Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as FTLB,
    L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User Local
    register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer), Fast
    TLB refill support, etc.
    
    This patch introduce a config option, CONFIG_LOONGSON3_ENHANCEMENT, to
    enable those enhancements which are not probed at run time. If you want
    a generic kernel to run on all Loongson 3 machines, please say 'N'
    here. If you want a high-performance kernel to run on new Loongson 3
    machines only, please say 'Y' here.
    
    Some additional explanations:
    1) SFB locates between core and L1 cache, it causes memory access out
       of order, so writel/outl (and other similar functions) need a I/O
       reorder barrier.
    2) Loongson 3 has a bug that di instruction can not save the irqflag,
       so arch_local_irq_save() is modified. Since CPU_MIPSR2 is selected
       by CONFIG_LOONGSON3_ENHANCEMENT, generic kernel doesn't use ei/di
       at all.
    3) CPU_HAS_PREFETCH is selected by CONFIG_LOONGSON3_ENHANCEMENT, so
       MIPS_CPU_PREFETCH (used by uasm) probing is also put in this patch.
    Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
    Cc: Aurelien Jarno <aurelien@aurel32.net>
    Cc: Steven J . Hill <sjhill@realitydiluted.com>
    Cc: Fuxin Zhang <zhangfx@lemote.com>
    Cc: Zhangjin Wu <wuzhangjin@gmail.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/12755/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    1e820da3
io.h 18.8 KB