[Why]
As SDMA0_SEM_WAIT_FAIL_TIMER_CNTL is a PF-only register,
L1 would block this register for VF access.

[How]
VF do not program it.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>