• Shengzhou Liu's avatar
    powerpc/fsl-booke: Add device tree support for T1024/T1023 SoC · ec66a97d
    Shengzhou Liu authored
    The T1024 SoC includes the following function and features:
    - Two 64-bit Power architecture e5500 cores, up to 1.4GHz
    - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
    - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
    - Data Path Acceleration Architecture (DPAA) incorporating acceleration
    - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
    - High-speed peripheral interfaces
      - Three PCI Express 2.0 controllers
    - Additional peripheral interfaces
      - One SATA 2.0 controller
      - Two USB 2.0 controllers with integrated PHY
      - Enhanced secure digital host controller (SD/eSDHC/eMMC)
      - Enhanced serial peripheral interface (eSPI)
      - Four I2C controllers
      - Four 2-pin UARTs or two 4-pin UARTs
      - Integrated Flash Controller supporting NAND and NOR flash
    - Two 8-channel DMA engines
    - Multicore programmable interrupt controller (PIC)
    - LCD interface (DIU) with 12 bit dual data rate
    - QUICC Engine block supporting TDM, HDLC, and UART
    - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
    - Support for hardware virtualization and partitioning enforcement
    - QorIQ Platform's Trust Architecture 2.0
    Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
    [scottwood@freescale.com: whitespace fixes]
    Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
    ec66a97d
t1024si-post.dtsi 3 KB