• Babu Moger's avatar
    x86/resctrl: Fix memory bandwidth counter width for AMD · 2c18bd52
    Babu Moger authored
    Memory bandwidth is calculated reading the monitoring counter
    at two intervals and calculating the delta. It is the software’s
    responsibility to read the count often enough to avoid having
    the count roll over _twice_ between reads.
    
    The current code hardcodes the bandwidth monitoring counter's width
    to 24 bits for AMD. This is due to default base counter width which
    is 24. Currently, AMD does not implement the CPUID 0xF.[ECX=1]:EAX
    to adjust the counter width. But, the AMD hardware supports much
    wider bandwidth counter with the default width of 44 bits.
    
    Kernel reads these monitoring counters every 1 second and adjusts the
    counter value for overflow. With 24 bits and scale value of 64 for AMD,
    it can only measure up to 1GB/s without overflowing. For the rates
    above 1GB/s this will fail to measure the bandwidth.
    
    Fix the issue setting the default width to 44 bits by adjusting the
    offset.
    
    AMD future products will implement CPUID 0xF.[ECX=1]:EAX.
    
     [ bp: Let the line stick out and drop {}-brackets around a single
       statement. ]
    
    Fixes: 4d05bf71 ("x86/resctrl: Introduce AMD QOS feature")
    Signed-off-by: default avatarBabu Moger <babu.moger@amd.com>
    Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
    Link: https://lkml.kernel.org/r/159129975546.62538.5656031125604254041.stgit@naples-babu.amd.com
    2c18bd52
core.c 24.8 KB