• Andy Shevchenko's avatar
    dmaengine: hsu: correct use of channel status register · 4f4bc0ab
    Andy Shevchenko authored
    There is a typo in documentation regarding to descriptor empty bit (DESCE)
    which is set to 1 when descriptor is empty. Thus, status register at the end of
    a transfer usually returns all DESCE bits set and thus it will never be zero.
    
    Moreover, there are 2 bits (CDESC) that encode current descriptor, on which
    interrupt has been asserted. In case when we have few descriptors programmed we
    might have non-zero value.
    
    Remove DESCE and CDESC bits from DMA channel status register (HSU_CH_SR) when
    reading it.
    
    Fixes: 2b49e0c5 ("dmaengine: append hsu DMA driver")
    Cc: stable@vger.kernel.org
    Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
    Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
    4f4bc0ab
hsu.h 3.09 KB