• Maciej W. Rozycki's avatar
    MIPS: DECstation I/O ASIC DMA interrupt classes · 0fabe102
    Maciej W. Rozycki authored
    This change complements commits d0da7c002f7b2a93582187a9e3f73891a01d8ee4
    [MIPS: DEC: Convert to new irq_chip functions] and
    5359b938 [MIPS: DECstation I/O ASIC DMA
    interrupt handling fix] and implements automatic handling of the two
    classes of DMA interrupts the I/O ASIC implements, informational and
    errors.
    
    Informational DMA interrupts do not stop the transfer and use the
    `handle_edge_irq' handler that clears the request right away so that
    another request may be recorded while the previous is being handled.
    
    DMA error interrupts stop the transfer and require a corrective action
    before DMA can be reenabled.  Therefore they use the `handle_fasteoi_irq'
    handler that only clears the request on the way out.  Because MIPS
    processor interrupt inputs, one of which the I/O ASIC's interrupt
    controller is cascaded to, are level-triggered it is recommended that
    error DMA interrupt action handlers are registered with the IRQF_ONESHOT
    flag set so that they are run with the interrupt line masked.
    
    This change removes the export of clear_ioasic_dma_irq that now does not
    have to be called by device drivers to clear interrupts explicitly
    anymore.  Originally these interrupts were cleared in the .end handler of
    the `irq_chip' structure, before it was removed.
    Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/5874/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    0fabe102
ioasic.h 862 Bytes