• Dong Aisheng's avatar
    clk: imx: fix pll clock parents · f83d3163
    Dong Aisheng authored
    pllx_bypass_src mux shouldn't be the parent of pllx clock
    since it's only valid when when pllx BYPASS bit is set.
    Thus it is actually one parent of pllx_bypass only.
    
    Instead, pllx parent should be fixed to osc according to
    reference manual.
    Other plls have the same issue.
    
    e.g. before fix, the pll tree is:
    osc                                      6            6    24000000          0 0
       pll1_bypass_src                       0            0    24000000          0 0
          pll1                               0            0   792000000          0 0
             pll1_bypass                     0            0   792000000          0 0
                pll1_sys                     0            0   792000000          0 0
    
    After the fix, it's:
    osc                                      6            6    24000000          0 0
       pll1                                  0            0   792000000          0 0
          pll1_bypass                        0            0   792000000          0 0
             pll1_sys                        0            0   792000000          0 0
    Signed-off-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
    Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
    f83d3163
clk-imx6sl.c 29.1 KB