• Thierry Reding's avatar
    clk: tegra: Squash sor1 safe/brick/src into a single mux · c1273af4
    Thierry Reding authored
    The sor1 clock on Tegra210 is structured in the following way:
    
        +-------+
        | pllp  |---+
        +-------+   |    +--------------+       +-----------+
                    +----|              |       | sor_safe  |
        +-------+        |              |       +-----------+
        | plld  |--------|              |             |
        +-------+        |              |       +-----------+
                         |   sor1_src   |-------|           |
        +-------+        |              |       +-----------+
        | plld2 |--------|              |             |
        +-------+        |              |             |
                    +----|              |             |
        +-------+   |    +--------------+             |
        | clkm  |---+                           +-----------+
        +-------+        +--------------+       |           |
                         |  sor1_brick  |-------|   sor1    |
                         +--------------+       |           |
                                                +-----------+
    
    This is impractical to represent in a clock tree, though, because there
    is no name for the mux that has sor_safe and sor1_src as parents. It is
    also much more cumbersome to deal with the additional mux because users
    of these clocks (the display driver) would have to juggle with an extra
    mux for no real reason.
    
    To simply things, the above is squashed into two muxes instead, so that
    it looks like this:
    
        +-------+
        | pllp  |---+
        +-------+   |    +--------------+       +-----------+
                    +----|              |       | sor_safe  |
        +-------+        |              |       +-----------+
        | plld  |--------|              |             |
        +-------+        |              |       +-----------+
                         |   sor1_src   |-------|   sor1    |
        +-------+        |              |       +-----------+
        | plld2 |--------|              |           |   |
        +-------+        |              |           |   |
                    +----|              |           |   |
        +-------+   |    +--------------+           |   |
        | clkm  |---+                               |   |
        +-------+        +--------------+           |   |
                         |  sor1_brick  |-----------+---+
                         +--------------+
    
    This still very accurately represents the hardware. Note that sor1 has
    sor1_brick as input twice, that's because bit 1 in the mux selects the
    sor1_brick irrespective of bit 0.
    Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
    c1273af4
clk-id.h 6.09 KB