• Iwo Mergler's avatar
    mtd: tests: test for multi-bit error correction · 3cf06f4f
    Iwo Mergler authored
    This tests ECC biterror recovery on a single NAND page. Mostly intended
    to test ECC hardware and low-level NAND driver.
    
    There are two test modes:
    
        0 - artificially inserting bit errors until the ECC fails
            This is the default method and fairly quick. It should
            be independent of the quality of the FLASH.
    
        1 - re-writing the same pattern repeatedly until the ECC fails.
            This method relies on the physics of NAND FLASH to eventually
            generate '0' bits if '1' has been written sufficient times. Depending
            on the NAND, the first bit errors will appear after 1000 or
            more writes and then will usually snowball, reaching the limits
            of the ECC quickly.
    
    The test stops after 10000 cycles, should your FLASH be exceptionally
    good and not generate bit errors before that. Try a different page
    offset in that case.
    
    Please note that neither of these tests will significantly 'use up' any FLASH
    endurance. Only a maximum of two erase operations will be performed.
    Signed-off-by: default avatarIwo Mergler <Iwo.Mergler@netcommwireless.com.au>
    Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
    Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
    3cf06f4f
Makefile 392 Bytes