• Suman Anna's avatar
    remoteproc: k3-r5: Add a remoteproc driver for R5F subsystem · 6dedbd1d
    Suman Anna authored
    The TI K3 family of SoCs typically have one or more dual-core Arm Cortex
    R5F processor clusters/subsystems (R5FSS). This R5F subsystem/cluster
    can be configured at boot time to be either run in a LockStep mode or in
    an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem
    has 64 KB each Tightly-Coupled Memory (TCM) internal memories for each
    core split between two banks - TCMA and TCMB (further interleaved into
    two banks). The subsystem does not have an MMU, but has a Region Address
    Translater (RAT) module that is accessible only from the R5Fs for providing
    translations between 32-bit CPU addresses into larger system bus addresses.
    
    Add a remoteproc driver to support this subsystem to be able to load and
    boot the R5F cores primarily in LockStep mode. The code also includes the
    base support for Split mode. Error Recovery and Power Management features
    are not currently supported. Loading support includes the internal TCMs
    and DDR. RAT support is left for a future patch, and as such the reserved
    memory carveout regions are all expected to be using memory regions within
    the first 2 GB.
    
    The R5F remote processors do not have an MMU, and so require fixed memory
    carveout regions matching the firmware image addresses. Support for this
    is provided by mandating multiple memory regions to be attached to the
    remoteproc device. The first memory region will be used to serve as the
    DMA pool for all dynamic allocations like the vrings and vring buffers.
    The remaining memory regions are mapped into the kernel at device probe
    time, and are used to provide address translations for firmware image
    segments without the need for any RSC_CARVEOUT entries. Any firmware
    image using memory outside of the supplied reserved memory carveout
    regions will be errored out.
    
    The R5F processors on TI K3 SoCs require a specific sequence for booting
    and shutting down the processors. This sequence is also dependent on the
    mode (LockStep or Split) the R5F cluster is configured for. The R5F cores
    have a Memory Protection Unit (MPU) that has a default configuration that
    does not allow the cores to run out of DDR out of reset. This is resolved
    by using the TCMs for boot-strapping code that applies the appropriate
    executable permissions on desired DDR memory. The loading into the TCMs
    requires that the resets be released first with the cores in halted state.
    The Power Sleep Controller (PSC) module on K3 SoCs requires that the cores
    be in WFI/WFE states with no active bus transactions before the cores can
    be put back into reset. Support for this is provided by using the newly
    introduced .prepare() and .unprepare() ops in the remoteproc core. The
    .prepare() ops is invoked before any loading, and the .unprepare() ops
    is invoked after the remoteproc resource cleanup. The R5F core resets
    are deasserted in .prepare() and asserted in .unprepare(), and the cores
    themselves are started and halted in .start() and .stop() ops. This
    ensures symmetric usage and allows the R5F cores state machine to be
    maintained properly between using the sysfs 'state' variable, bind/unbind
    and regular module load/unload flows.
    
    The subsystem is represented as a single remoteproc in LockStep mode, and
    as two remoteprocs in Split mode. The driver uses various TI-SCI interfaces
    to talk to the System Controller (DMSC) for managing configuration, power
    and reset management of these cores. IPC between the A53 cores and the R5
    cores is supported through the virtio rpmsg stack using shared memory and
    OMAP Mailboxes.
    
    The AM65x SoCs typically have a single R5FSS in the MCU voltage domain. The
    J721E SoCs uses a slightly revised IP and typically have three R5FSSs, with
    one cluster present within the MCU voltage domain (MCU_R5FSS0), and the
    remaining two clusters present in the MAIN voltage domain (MAIN_R5FSS0 and
    MAIN_R5FSS1). The integration of these clusters on J721E SoC is also
    slightly different in that these IPs do support an actual local reset line,
    while they are a no-op on AM65x SoCs.
    Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
    Reviewed-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
    Link: https://lore.kernel.org/r/20201002234234.20704-3-s-anna@ti.comSigned-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
    6dedbd1d
Makefile 1.52 KB