• Ville Syrjälä's avatar
    drm/i915: Update RAWCLK_FREQ register on VLV/CHV · 19ab4ed3
    Ville Syrjälä authored
    I just noticed that VLV/CHV have a RAWCLK_FREQ register just like PCH
    platforms. It lives in the display power well, so we should update it
    when enabling the power well.
    
    Interestingly the BIOS seems to leave it at the reset value (125) which
    doesn't match the rawclk frequency on VLV/CHV (200 MHz). As always with
    these register, the spec is extremely vague what the register does. All
    it says is: "This is used to generate a divided down clock for
    miscellaneous timers in display." Based on a quick test, at least AUX
    and PWM appear to be unaffected by this.
    
    But since the register is there, let's configure it in accordance with
    the spec.
    
    Note that we have to move intel_update_rawclk() to occur before we
    touch the power wells, so that the dev_priv->rawclk_freq is already
    populated when the disp2 enable hook gets called for the first time.
    I think this should be safe to do on other platforms as well.
    
    Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
    Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Link: http://patchwork.freedesktop.org/patch/msgid/1461768202-17544-1-git-send-email-ville.syrjala@linux.intel.comReviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
    19ab4ed3
intel_display.c 456 KB