• Tomi Valkeinen's avatar
    clk: divider: fix rate calculation for fractional rates · b11d282d
    Tomi Valkeinen authored
    clk-divider.c does not calculate the rates consistently at the moment.
    
    As an example, on OMAP3 we have a clock divider with a source clock of
    864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are:
    
    6: 144000000
    7: 123428571.428571...
    8: 108000000
    
    Calling clk_round_rate() with the rate in the first column will give the
    rate in the second column:
    
    144000000 -> 144000000
    143999999 -> 123428571
    123428572 -> 123428571
    123428571 -> 108000000
    
    Note how clk_round_rate() returns 123428571 for rates from 123428572 to
    143999999, which is mathematically correct, but when clk_round_rate() is
    called with 123428571, the returned value is surprisingly 108000000.
    
    This means that the following code works a bit oddly:
    
    rate = clk_round_rate(clk, 123428572);
    clk_set_rate(clk, rate);
    
    As clk_set_rate() also does clock rate rounding, the result is that the
    clock is set to the rate of 108000000, not 123428571 returned by the
    clk_round_rate.
    
    This patch changes the clk-divider.c to use DIV_ROUND_UP when
    calculating the rate. This gives the following behavior which fixes the
    inconsistency:
    
    144000000 -> 144000000
    143999999 -> 123428572
    123428572 -> 123428572
    123428571 -> 108000000
    Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
    Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
    b11d282d
clk-divider.c 9.18 KB