-
Thierry Reding authored
Add the top-level pcie-controller node for the Tegra20 SoC. Tegra20 has two root ports that can use different lane layouts. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com> [swarren: split DT changes into a separate patch from the main driver] Signed-off-by: Stephen Warren <swarren@nvidia.com>
1b62b611