Add PHY configuration registers for single link DP with 100MHz reference
clock and NO_SSC.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20210728145454.15945-7-sjakhade@cadence.comSigned-off-by: Vinod Koul <vkoul@kernel.org>