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Matthew Vick authored
In rare circumstances, it's possible a descriptor writeback will occur before a timestamped Tx packet will go out on the wire, leading to the driver believing the hardware failed to timestamp the packet. Schedule a work item for 82576 and use the available time sync interrupt registers on 82580 and above to account for this. Cc: Richard Cochran <richardcochran@gmail.com> Signed-off-by:
Matthew Vick <matthew.vick@intel.com> Tested-by:
Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by:
Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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