• Gautham R. Shenoy's avatar
    cpuidle: pseries: Fixup exit latency for CEDE(0) · d947fb4c
    Gautham R. Shenoy authored
    We are currently assuming that CEDE(0) has exit latency 10us, since
    there is no way for us to query from the platform. However, if the
    wakeup latency of an Extended CEDE state is smaller than 10us, then we
    can be sure that the exit latency of CEDE(0) cannot be more than that.
    
    In this patch, we fix the exit latency of CEDE(0) if we discover an
    Extended CEDE state with wakeup latency smaller than 10us.
    
    Benchmark results:
    
    On POWER8, this patch does not have any impact since the advertized
    latency of Extended CEDE (1) is 30us which is higher than the default
    latency of CEDE (0) which is 10us.
    
    On POWER9 we see improvement the single-threaded performance of
    ebizzy, and no regression in the wakeup latency or the number of
    context-switches.
    
    ebizzy:
    2 ebizzy threads bound to the same big-core. 25% improvement in the
    avg records/s with patch.
    
      x without_patch
      * with_patch
          N           Min           Max        Median           Avg        Stddev
      x  10       2491089       5834307       5398375       4244335     1596244.9
      *  10       2893813       5834474       5832448     5327281.3     1055941.4
    
    context_switch2:
    There is no major regression observed with this patch as seen from the
    context_switch2 benchmark.
    
    context_switch2 across CPU0 CPU1 (Both belong to same big-core, but
    different small cores). We observe a minor 0.14% regression in the
    number of context-switches (higher is better).
    
      x without_patch
      * with_patch
          N           Min           Max        Median           Avg        Stddev
      x 500        348872        362236        354712     354745.69      2711.827
      * 500        349422        361452        353942      354215.4     2576.9258
    
      Difference at 99.0% confidence
        -530.288 +/- 430.963
        -0.149484% +/- 0.121485%
        (Student's t, pooled s = 2645.24)
    
    context_switch2 across CPU0 CPU8 (Different big-cores). We observe a
    0.37% improvement in the number of context-switches (higher is
    better).
    
      x without_patch
      * with_patch
          N           Min           Max        Median           Avg        Stddev
      x 500        287956        294940        288896     288977.23     646.59295
      * 500        288300        294646        289582     290064.76     1161.9992
    
      Difference at 99.0% confidence
        1087.53 +/- 153.194
        0.376337% +/- 0.0530125%
        (Student's t, pooled s = 940.299)
    
    schbench:
    No major difference could be seen until the 99.9th percentile.
    
    Without-patch:
      Latency percentiles (usec)
            50.0th: 29
            75.0th: 39
            90.0th: 49
            95.0th: 59
            *99.0th: 13104
            99.5th: 14672
            99.9th: 15824
            min=0, max=17993
    
    With-patch:
      Latency percentiles (usec)
            50.0th: 29
            75.0th: 40
            90.0th: 50
            95.0th: 61
            *99.0th: 13648
            99.5th: 14768
            99.9th: 15664
            min=0, max=29812
    Signed-off-by: default avatarGautham R. Shenoy <ego@linux.vnet.ibm.com>
    [mpe: Minor formatting]
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    Link: https://lore.kernel.org/r/1596087177-30329-4-git-send-email-ego@linux.vnet.ibm.com
    d947fb4c
cpuidle-pseries.c 11.5 KB