• Paul Burton's avatar
    MIPS: Use queued read/write locks (qrwlock) · 25da4e9d
    Paul Burton authored
    This patch switches MIPS to make use of generically implemented queued
    read/write locks, rather than the custom implementation used previously.
    This allows us to drop a whole load of inline assembly, share more
    generic code, and is also a performance win.
    
    Results from running the AIM7 short workload on a MIPS Creator Ci40 (ie.
    2 core 2 thread interAptiv CPU clocked at 546MHz) with v4.12-rc4
    pistachio_defconfig, with ftrace disabled due to a current bug, and both
    with & without use of queued rwlocks & spinlocks:
    
      Forks | v4.12-rc4 | +qlocks  | Change
     -------|-----------|----------|--------
         10 | 52630.32  | 53316.31 | +1.01%
         20 | 51777.80  | 52623.15 | +1.02%
         30 | 51645.92  | 52517.26 | +1.02%
         40 | 51634.88  | 52419.89 | +1.02%
         50 | 51506.75  | 52307.81 | +1.02%
         60 | 51500.74  | 52322.72 | +1.02%
         70 | 51434.81  | 52288.60 | +1.02%
         80 | 51423.22  | 52434.85 | +1.02%
         90 | 51428.65  | 52410.10 | +1.02%
    
    The kernels used for these tests also had my "MIPS: Hardcode cpu_has_*
    where known at compile time due to ISA" patch applied, which allows the
    kernel_uses_llsc checks in cmpxchg() & xchg() to be optimised away at
    compile time.
    Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/16357/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    25da4e9d
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