• chris hyser's avatar
    sparc64: Enable setting "relaxed ordering" in IOMMU mappings · aa7bde1a
    chris hyser authored
    Enable relaxed ordering for memory writes in IOMMU TSB entry from
    dma_4v_alloc_coherent(), dma_4v_map_page() and dma_4v_map_sg() when
    dma_attrs DMA_ATTR_WEAK_ORDERING is set. This requires PCI IOMMU I/O
    Translation Services version 2.0 API.
    
    Many PCIe devices allow enabling relaxed-ordering (memory writes bypassing
    other memory writes) for various DMA buffers. A notable exception is the
    Mellanox mlx4 IB adapter. Due to the nature of x86 HW this appears to have
    little performance impact there. On SPARC HW however, this results in major
    performance degradation getting only about 3Gbps. Enabling RO in the IOMMU
    entries corresponding to mlx4 data buffers increases the throughput to
    about 13 Gbps.
    
    Orabug: 19245907
    Signed-off-by: default avatarChris Hyser <chris.hyser@oracle.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    aa7bde1a
hypervisor.h 98.3 KB