• Chris Metcalf's avatar
    tile: fast-path unaligned memory access for tilegx · 2f9ac29e
    Chris Metcalf authored
    This change enables unaligned userspace memory access via a kernel
    fast path on tilegx.  The kernel tracks user PC/instruction pairs
    per-thread using a direct-mapped cache in userspace.  The cache
    maps those PC/instruction pairs to JIT'ed instruction sequences that
    load or store using byte-wide load store intructions and then
    synthesize 2-, 4- or 8-byte load or store results.  Once an
    instruction has been seen to generate an unaligned access once,
    subsequent hits on that instruction typically require overhead
    of only around 50 cycles if cache and TLB is hot.
    
    We support the prctl() PR_GET_UNALIGN / PR_SET_UNALIGN sys call to
    enable or disable unaligned fixups on a per-process basis.
    
    To do this we pull some of the tilepro unaligned support out of the
    single_step.c file; tilepro uses instruction disassembly for both
    single-step and unaligned access support.  Since tilegx actually has
    hardware singlestep support, though, it's cleaner to keep the tilegx
    unaligned access code in a separate file.  While we're at it,
    properly rename the tilepro-specific types, etc., to have tilepro
    suffixes instead of generic tile suffixes.
    Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
    2f9ac29e
processor.h 10.6 KB